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Optimized Hardware Implementation of Enhanced TRIPLE-DES using Cluster LUT and Pipelining on SPARTEN FPGA

Authors :
Noha Hussen
Amany Sarhan
Marwa Fayez
Source :
International Journal of Computer Applications. 164:5-14
Publication Year :
2017
Publisher :
Foundation of Computer Science, 2017.

Subjects

Subjects :
Triple DES
Software pipelining
Computer architecture
Computer science
Lookup table
Cluster (physics)
Field-programmable gate array

Details

ISSN :
09758887
Volume :
164
Database :
OpenAIRE
Journal :
International Journal of Computer Applications
Accession number :
edsair.doi...........925dddfe034e4a18568e9d3ea5954a1a
Full Text :
https://doi.org/10.5120/ijca2017913608
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