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Aging-Aware Gate-Level Modeling for Circuit Reliability Analysis

Authors :
Ru Huang
Zuodong Zhang
Zhe Zhang
Joddy Wang
Dehuang Wu
Xuguang Shen
Runsheng Wang
Jiayang Zhang
Source :
IEEE Transactions on Electron Devices. 68:4201-4207
Publication Year :
2021
Publisher :
Institute of Electrical and Electronics Engineers (IEEE), 2021.

Abstract

Due to severer transistor aging at nanoscale, circuit design margin becomes extremely tight for advanced technology nodes. Thus, reliability-aware circuit design is urgently needed. In this article, a new framework to perform aging-aware static timing analysis (STA) is presented for reliability analysis. The key parts of aging-aware STA flows are workload analysis and aged delay/transition calculation. For the workload analysis, a new analytical stress probability (SP) calculation model is proposed, which considers the floating effect and signal correlations. For aged delay/transition calculation, a new aging-aware model is developed, which is accessible to large industrial libraries. The results show that the proposed model achieves high accuracy in the degradation estimation and aged-path-delay calculation. Due to its high accuracy and scalability, the proposed framework is a promising solution that is compatible with commercial Electronic Design Automation (EDA) tools.

Details

ISSN :
15579646 and 00189383
Volume :
68
Database :
OpenAIRE
Journal :
IEEE Transactions on Electron Devices
Accession number :
edsair.doi...........9e2de172f165729e4c80d7a3082f2577
Full Text :
https://doi.org/10.1109/ted.2021.3096171