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Constraining and biasing are frequently used techniques to enhance the quality of randomized vector generation. In this paper, we present a novel method that combines constraints and input biasing in automatic bit-vector generation for block-level functional verification of digital designs, which is implemented in a tool called SimGen. Vector generation in SimGen is confined to a legal input space that is defined by constraints symbolically represented in Binary Decision Diagrams (BDDs). A constraint involving state variables in the design defines a state-dependent legal input space. Input biasing can also depend on the state of the design. The effect of constraints and input biasing are combined to form what we called the constrained probabilities of input vectors. An algorithm is developed to efficiently generate input vectors on-the-fly during simulation. The vector generation is a one-pass process, i.e., no backtracking or retry is needed. Also, we describe methods of minimizing the constraint BDDs in an effort to reduce the simulation-time overhead of SimGen. Furthermore we discuss the application of SimGen to a set of commercial design blocks.