An investigation of FinFET single-event latch-up characteristic and mitigation method

FinFET technology compared with planar have an increased sensitivity to single-event latch-up. TCAD simulation demonstrates that the reduction in width of MOSFET, thickness of shallow trench isolation (STI) and nMOS-to-pMOS lateral spacing will reduce the holding voltage, critical charge and increase the current gain of parasitic CMOS Silicon Controlled Rectifier (SCR). Through circuit analysis, it found that the change of parasitic vertical and horizontal resistance is mainly responsible for aforementioned phenomena. In addition, we found that the common protective measures such as guard rings spacing and epitaxial substrate become increasingly difficult. Based on the current preventive methods, we think that appropriate increasing the doping depth or the width of guard rings will improve protection from Single-Event Latch-up (SEL). Moreover, we verify the effectiveness of our methods by TCAD simulation and discuss the feasibility.