Failure rate calculation for NMOS devices under multiple failure mechanisms

Authors :: Xin Liu
Shi Qian
Zhenwei Zhou
Yunfei En
Wang Xiaohan
Source :: Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).
Publication Year :: 2013
Publisher :: IEEE, 2013.
Abstract: The failure rate for NMOS devices is modelled by sum-of-failure-rate, i.e., the one for HCI mechanism and the one for TDDB failure mechanism. The least squares method is used to estimate the unknown parameters in HCI failure rate model and TDDB failure rate model, respectively. The hypothesis tests show that the regression model for HCI (TDDB) has good fitness and high significance. These results are verified by a numerical example.

Subjects :: Engineering
Reliability (semiconductor)
business.industry
MOSFET
Failure rate
Time-dependent gate oxide breakdown
Regression analysis
Multiple failure
business
NMOS logic
Reliability engineering
Statistical hypothesis testing

Database :: OpenAIRE
Journal :: Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)
Accession number :: edsair.doi...........c77e3a7d2896e8d96ccf6d1e379157c5
Full Text :: https://doi.org/10.1109/ipfa.2013.6599182