Search

In this paper, we show a new bandstop filter circuit topology. Unlike conventional bandstop filter circuit topologies, the new circuit topology has inter-resonator coupling structures. The presence of these inter-resonator coupling structures enables convenient switching from a bandstop to a bandpass filter. Using the new bandstop filter topology, this paper demonstrates a design of a frequency-agile bandstop-to-bandpass switchable filter. The filter is composed of tunable substrate-integrated cavity resonators and can be switched to have either a bandstop or bandpass response. Switching is achieved by turning on and off switches placed within the filter structure. A prototype of the proposed design is fabricated and the concept is verified experimentally. [ABSTRACT FROM AUTHOR]

This paper proposes a design technique for the implementation of a class- EM power amplifier (PA). Class- EM mode of operation has been proposed as an improved version of class-E in terms of efficiency and power gain, provided that the current fall time of switch is an appreciable portion of a period; the frequency of operation is high enough that the switching time of transistor can no longer be considered instantaneous. A novel approach for harmonic injection required for class- EM operation is proposed, followed by the system of equations and the design methodology governing the proposed circuit. As a proof of concept and verification of the proposed design method, a class- EM PA is designed and implemented in 0.25- \mu \textm gallium arsenide pHEMT technology. The fabricated class- EM PA operates at 2.4 GHz and delivers a power of 30 dBm to the load, with the power-added efficiency of 60% and a 14-dB power gain. [ABSTRACT FROM PUBLISHER]

Integrated oscillators with octave frequency tuning range (FTR) are desirable for wireless transceivers supporting multiple frequency bands. In this paper, we describe a wide-FTR CMOS voltage-controlled oscillator (VCO) based on a novel area-efficient series resonator mode-switching scheme that preserves resonator quality factor $Q$ across the entire octave tuning range. This allows the CMOS VCO to simultaneously achieving wide FTR, area efficiency, and low phase noise, demonstrating state-of-the-art figure of merit (FoM) for > 10-GHz octave-tuning range VCOs. We also analyze the relationship between $Q$ and FTR across common resonator band-switching schemes, quantifying performance limits and highlighting the benefits of using mode-switching for wide-FTR VCOs. The proposed approach is demonstrated through a 6.4–14-GHz (74.6% FTR) VCO implemented in 65-nm CMOS that achieves 186–188-dB VCO FoM, demonstrating good FoM across the entire FTR. The scalability of this approach toward achieving even larger FTR is also demonstrated by a triple-mode 2.2–8.7-GHz (119% FTR) CMOS VCO. Area efficiency of the proposed mode-switching scheme is demonstrated by the state-of-the-art 197-dB FoM area achieved by the 14-GHz VCO. [ABSTRACT FROM AUTHOR]

A self-biased CMOS analog mixer for ultra-wideband (UWB) applications is presented in this paper. The proposed mixer is complementary and self-biased, and has lower power consumption, superior isolation, and larger bandwidth. The proposed low-power, down conversion mixer is designed and fabricated in UMC 0.18\mu \textm CMOS technology. The measurement results show that it can operate at UWB frequencies that range from 1 to 6 GHz. The proposed mixer provides a maximum conversion gain of 13 dB, −4.5 dBm of third-order input intercept point, and a minimum double sideband noise figure of 12 dB. The maximum values of the measured local oscillator LO-to-RF, RF-to-IF, and LO-to-IF isolations are 50, 45, and 52 dB, respectively. [ABSTRACT FROM PUBLISHER]

In this paper, a highly efficient class-G supply modulator targeting high-power wideband envelope tracking applications is presented. The maximum output power using a 50% duty cycle at 100-MHz switching frequency is 62 W for a switching between 30 and 50 V delivered in a 25- $\Omega $ load. The modulator including its driver circuit reaches an overall efficiency in the range of 97%–88% for switching frequencies from dc to 100 MHz for passive loads in a wide range. The modulator is designed to operate at various supply voltage levels and is evaluated within the range from 20 to 50 V while powering loads from 25 to 100 $\Omega $ . The modulator is characterized in terms of efficiency, switching frequency, and nonlinearities. [ABSTRACT FROM PUBLISHER]

This paper reports on tunable 2- and 3-pole bandpass filters with a wide frequency tuning range (tuning ratio >3) and a constant bandwidth using switchable varactor-tuned resonators. The wide center frequency tuning range is obtained using p-i-n diodes to switch in and out quarter-wavelength ( \lambda /4) or half-wavelength ( \lambda /2) resonators for low-band or high-band modes, without increasing the tuning capacitance range of the varactors. A combination of electric and magnetic coupling is utilized to realize a near constant absolute bandwidth across the tuning range. A switchable feed line with a fixed matching capacitance is used to realize the external coupling. Two filters are designed and fabricated on a Duroid substrate with \varepsilon r = 2.2 and h =0.787 mm. For the 2-pole filter, the center frequency is tuned from 550 to 1900 MHz while maintaining a 3-dB bandwidth of 92 ± 6 MHz, insertion loss of 3.2~4.4 dB, and return loss of better than 15 dB. For the 3-pole filter, the center frequency is tuned from 540 to 1800 MHz while maintaining a 3-dB bandwidth of 89 ± 4 MHz, insertion loss of 4~5.4 dB, and return loss of better than 12 dB. For both filter types, the third-order intercept point and 1-dB compression point ( P\mathrm {1~dB}) are 11 and 7 dBm, respectively. The rejection level at 200-MHz offset frequency from the passband center frequency is better than 25 and 41 dB for 2- and 3-pole filters, respectively, across the entire tuning range. To the best of our knowledge, this planar bandpass filter exhibits the widest tuning range with a near-constant bandwidth. [ABSTRACT FROM PUBLISHER]

This paper presents a nonlinear Q-switching impedance (NLQSI) technique for picosecond pulse radiation in silicon. A prototype chip is designed with four NLQSI-based impulse generation channels, which can produce picosecond pulses with a reconfigurable amplitude. An on-chip impulse-coupling scheme combines the outputs from four channels and delivers the combined signal to an on-chip antenna. In addition, an asynchronous optical-sampling measurement system is used to characterize the radiated picosecond pulses in the time domain. The prototype chip can radiate 4-ps pulses with an SNR > 1 bandwidth of 161 GHz. Furthermore, pulse amplitude modulation is experimentally demonstrated. The prototype chip is fabricated in a 130-nm SiGe BiCMOS process technology with a die area of 1 mm2. [ABSTRACT FROM PUBLISHER]

This paper presents a comparison of existing and novel behavioral models targeted at the outphasing power amplifier (PA) architecture. A comprehensive comparison of ten modeling strategies is presented in the results. Novel techniques for outphasing PAs, such as vector switched and dual path time series, are also presented for the first time. Investigation of such techniques was driven by the analysis of outphasing operation at minimum output powers, demonstrating the generation of frequency-dependent amplitude and phase deviations, which can be difficult to characterize. The increased robustness was achieved at the cost of additional complexity; for practical implementation, time series coefficient reduction techniques were also evaluated. The results of all modeling approaches are experimentally validated for the wideband operation of an NXP 19-W GaN digital outphasing amplifier module. Considering computational complexity and accuracy for system-level modeling across all presented options, a subset of existing and new models is identified as best suited for modeling outphasing PAs. [ABSTRACT FROM PUBLISHER]

In this paper, an efficient free-positioning wireless power transfer (WPT) system for charging multiple devices is proposed. For the system, a planar transmitting (Tx) coil that consists of a spiral coil and concentric multiple parallel loops and switchable impedance matching networks (IMNs) at a transmitter are developed. Using the Tx coil, mutual inductance between the Tx coil and the receiving (Rx) spiral coils is made uniform in the effective charging area. The parallel loops are placed in the interior of the Tx coil, and the magnetic field is enhanced and controlled by adjusting the space in each parallel loop. For optimal design of the coil, an analysis method using an equivalent circuit is explained in detail. It is found that the current of one loop of a parallel loop is more than the input current and negative current flows on the other loop, while the total current of each parallel loop is constant. An array of parallel capacitors with a switch as the switchable IMN is used for the maximum power transfer efficiency corresponding to the number of devices. The reflection coefficients of the fabricated WPT system are under −10 dB at 6.78 MHz, regardless of the number of devices and positions. The WPT system has the maximum power transfer efficiencies of 93% for two devices and simultaneously transfers uniform power to up to four devices with high efficiency. [ABSTRACT FROM PUBLISHER]

Switched mode RF power amplifiers (PAs) under bitstream modulations, such as bandpass or envelope delta–sigma modulations (EDSMs), have received increasing attentions over the past years. Such amplifiers offer high power efficiencies under power back-off conditions with pulse train voltage waveforms yet maintain their linearity in amplification through digital coding and modulations. This paper presented an $X$ -band switched mode PA based on the pulsed load modulation (PLM) technique with multilevel EDSM to realize broadband efficient amplification of nonconstant-envelope signals. The complete theory of power efficiency for PLM under three-level EDSM is presented. The X$ -band PA is implemented with 0.25- \mu \text{m} discrete GaN transistors from Triquint. Both two-level and three-level EDSM techniques were tested and compared in regard to their quantization noise levels and power efficiencies. Under the three-level EDSM, the PA delivered 34.6-dBm output power for a WCDMA uplink signal with 100-MHz bandwidth and 5.3-dB peak-to-average power ratio at the carrier frequency of 9.2 GHz. The measured drain efficiency and the power-added efficiency with the modulation were 34.6% and 26.5%, respectively. The adjacent channel leakage power ratio at the output was measured to be 32.2/32.3 dBc at the 100-MHz offsets without using digital predistortion. [ABSTRACT FROM AUTHOR]

This paper presents the design and measurement of an inductive link for transferring energy to a fully integrated wireless power receiver. The power receiver design was focused on optimizing each factor that contributes to the link efficiency while its size was constrained to 1.5 mm $\times$ 1.5 mm in a conventional CMOS 180-nm process. On the power transmitter side, the primary inductor is printed on an FR4 board and its dimensions are selected so as to optimize its quality factor and the magnetic coupling factor. A strategy is proposed to experimentally determine the performance of the entire system. Using the proposed strategy, we measured a link efficiency of −25.4 dB at a frequency of 986 MHz, with a primary inductor of average diameter 22 mm and distance 15 mm from the receiver. Considering the characteristics of the receiver: monolithic implementation, chip area, link efficiency, and distance to the transmitter, the designed wireless power transfer system exhibits a better performance than state-of-the-art systems. [ABSTRACT FROM PUBLISHER]

This paper presents a design methodology to drastically improve the hot-switching reliability of contact-type radio frequency microelectromechanical system (RF-MEMS) switches. In the proposed design, sacrificial contacts are placed in parallel with low-resistance contacts to significantly reduce the electric field across the latter. The lower field strength drastically reduces the contact degradation associated with field-induced material transfer. Theoretical and numerical modeling shows that the proposed protection scheme introduces minimal, if any, impact on the RF performance of the switch. To realize the protection scheme, we introduce a novel mechanical design that allows the correct protection actuation sequence to be realized using a single actuator and bias electrode. As a demonstration, several 0–40-GHz RF-MEMS switches are fabricated using a robust copper sacrificial layer technique. Compared with unprotected switches, the protected switch design exhibits over 100 times improvement in the hot-switching lifetime. In particular, we demonstrate a 100–150 million cycle lifetime at 1-W hot switching and 50 million cycles at 2-W hot switching before catastrophic failure, measured in an open-air lab environment. Further optimization of the structural design and contact materials is likely to further increase the hot-switching lifetime. [ABSTRACT FROM PUBLISHER]

In this paper, a miniature switched beamformer module for 2.4-GHz applications is proposed. The proposed beamformer module is based on the integrated passive device technology, and it integrates a 4 \times 4 Butler matrix, a single-pole four-throw beam-selection switch, and a p-i-n diode-based transmit/receive (T/R) switch into a compact module size of only 4.9 \text {mm} \times 5~\text {mm} \times 0.9 mm. To achieve the compact module size, bridged-T coils are used to replace the transmission line sections in the 4 \times 4$ Butler matrix and the T/R switch. The measured insertion loss at the center frequency of 2.4 GHz is within 10.89 ± 1.13 dB for the receive path and 11.33 ± 0.69 dB for the transmit path. The measured phase error is less than 8.4° at 2.4 GHz. The proposed beamformer features low cost, compact size, and low profile. It can help enable the use of phased array technique in handheld mobile devices. [ABSTRACT FROM AUTHOR]

This paper presents the analysis of a novel high-pass filter/low-pass filter (HPF/LPF) switching concept. Since an HPF/LPF switching concept has a periodic structure, its equivalent circuit is almost the same as an LPF for the ON-state and is the same as an HPF for the OFF-state. The broadband isolation characteristics with low insertion loss can be achieved by designing its cutoff frequency. A three-stage single pole single throw InGaAs pseudomorphic high electron mobility transistor monolithic microwave integrated circuit switch based on the HPF/LPF switching concept is successfully demonstrated with an insertion loss of less than 1.6 dB and isolation of more than 82 dB below 6 GHz, with a size of 1.1 mm $\times \,\, 1.0$ mm. The RF performances are in good agreement with the theoretical calculations. The measured input power of 1-dB insertion loss compression, P1dB, and the measured third-order intercept point, IIP3, are 19 and 27.7 dBm, respectively, at 1.95 GHz. The measured ON-time is 5.5 ns without cable delay. The measured rise time is as fast as 1.4 ns. [ABSTRACT FROM AUTHOR]

A 2.4-GHz low-power low-noise direct-conversion receiver is demonstrated using parasitic vertical-NPN bipolar junction transistors (BJTs) in a standard 0.18-\mu\ m CMOS process. The current switching operation of a Gilbert mixer with finite transistor cutoff frequency (fT) is thoroughly analyzed and discussed in this paper. When the mixer operates near or higher than the transistor f T, the loss of the polyphase filter due to the capacitive loading of the mixer is a main issue. Thus, BJT devices with smaller base resistance and an inductive peaking technique with symmetric 3-D realization are employed in this paper to reduce local oscillator power by 4.5 dB. At 2.4 GHz, the demonstrated receiver has conversion gain of 51 dB and noise figure of 3.2 dB with 70-kHz 1/f noise corner, while the current consumption is 4.5 mA at a 1.8-V supply. [ABSTRACT FROM PUBLISHER]

This paper presents a study of the noise performance of a time-varying impedance matching technique. A mathematical model is developed for calculating the impulse response of the matching design that reconfigures itself in the real time between two subsystems. Based on this model, the signal-to-noise ratio (SNR) degradation of the matching network is defined and analyzed. Simulations of a typical matching design for RL sources show that the SNR degradation is generally lower than 1 dB for common pulse signals including single-cycle sinusoids and Gaussian pulses. Particularly, the time-varying matching design for a high-quality (Q>10) source can be optimized to have an impulse response that matches monocycle pulses very well, leading to a near-optimal SNR performance (less than 0.1-dB SNR degradation). The theoretical results are validated experimentally by an implementation of the matching technique for electrically small loop antennas. Lower than 1.5-dB SNR degradation is measured for most cases. The effect of switch noise is also investigated in this paper. [ABSTRACT FROM AUTHOR]

This paper presents a novel design procedure for the class-EM amplifier. The numerical design procedure is applied to the design of the class-EM amplifier, which achieves simple and accurate designs for high-order circuits. As a result, no tuning process is necessary in the circuit implementations. In this paper, two types of auxiliary circuits are considered, namely, the zero-voltage switching class-E amplifier and the zero-voltage switching class-E frequency doubler. The class-E auxiliary amplifier has a lower driving power and a higher output power capability than the class-E auxiliary frequency doubler. On the other hand, the class-E auxiliary frequency doubler has lower number of the non-zero-current switchings than the class-E auxiliary amplifier and no on-interval of the antiparallel diode of the MOSFET. The laboratory experimental results agreed quantitatively with the numerical predictions, which validate the effectiveness of the proposed design procedure. [ABSTRACT FROM AUTHOR]

A dual-band switchable harmonic receiver for downconverting the industrial-scientific-medical and local-multipoint-distribution-service bands at 24 and 31 GHz is proposed in this paper. The front end utilizes a new technique for band selection. Mathematical formulation, including the effect of mismatches, for the new switchable harmonic receiver is provided in this paper. In addition, new circuit techniques for the low-noise amplifier and millimeter-wave mixer implementations are presented. The receiver is implemented using 0.18-\mum BiCMOS technology with a total power consumption of 60 mW. Measurements show a band rejection higher than 43 dB, gain of 21 and 18 dB, NF lower than 8 and 9.5 dB, and third-order intercept point of -18 and -17 dBm for the 24- and 31-GHz frequency bands, respectively. [ABSTRACT FROM PUBLISHER]

This paper proposes a scalable and efficient frequency multiplication technique that synthesizes a multi-phase clock with finely adjustable output taps. It uses a pulse injection locked rotary traveling-wave oscillator (RTWO) with switched capacitors and complementary varactor pairs to achieve a 1.7–2-GHz tuning range and to implement the fine phase adjustment. The worst case phase-tuning resolution is 0.36°. The design is implemented in IBM’s 130-nm CMOS technology, and consumes a total power of 28.4 mW. Locked to a clean 679-MHz reference, it has a phase-noise performance of -\text 132 dBc/Hz at 100-kHz offset from 2.039 GHz. It achieves 39-fs integrated root mean square (rms) jitter from 1 kHz to 40-MHz offset, for a \text Jitter^2 \ast \text Power Figure of Merit (FOM) of -\text 251 dB . [ABSTRACT FROM AUTHOR]

This paper describes a newly developed Si/GaAs hybrid multiband power amplifier module (MB-PAM) that supports major quad wideband code division multiple access (WCDMA) bands (Bands 5, 8, 2, and 1) for handset applications. With four dies (two GaAs-HBT dies, one GaAs-HEMT die, and one CMOS die) and several surface-mount devices, the hybrid MB-PAM accommodates two amplifier chains and two single-pole double-throw HEMT band-select switches on a 5 mm\,\times\, 5.5 mm laminate, covering 824–915 and 1850–1980 MHz. Each amplifier chain has two switchable signal paths corresponding to dual (high and low) power modes [high-power mode (HPM) and low-power mode (LPM)] for saving battery current in practical handset use. One of the main features of this MB-PAM is the integration of driver stages, RF switches, and their bias control circuits on the CMOS die for pursuing cost reduction. Only the two output power stages are fabricated in a GaA-HBT process. Measurements conducted under the condition of a 3.4-V supply voltage and a WCDMA (Third Generation Partnership Project Release 99) modulated signal are as follows. Owing to optimized linear design and broadband output matching design, the hybrid MB-PAM achieves a power-added efficiency (PAE) as high as 39%–40% at 28 dBm of output power ( Pout) over 824–915 MHz in the HPM while maintaining a \pm \5-MHz-offset adjacent channel leakage power ratio (ACLR1) to less than -\39 dBc. In the LPM, PAE of 15% at a Pout of 17 dBm is obtained while ACLR1 of less than -\40 dBc is maintained. For 1850–1980 MHz, the MB-PAM delivers 35% of PAE with ACLR1 of less than -\40 dBc at 28 dBm of Pout in the HPM and 15% PAE at 17.5 dBm of Pout in the LPM. [ABSTRACT FROM PUBLISHER]

In this paper, two fully integrated digital power amplifiers (DPAs) intended for polar transmitters are proposed using a 40-nm CMOS technology, which achieve ultra wideband and high efficiency simultaneously. Firstly, the wideband Class-E power amplifier with nonideal characteristics is analyzed. Secondly, the design procedure of converting the nonideal Class-E model to a compact matching network is introduced for the on-chip implementation. Thirdly, the stacked-stepped-impedance transformer is utilized for the wideband output-matching network to improve the DPA power efficiency while tracking optimum load impedance. Finally, to enhance the saturated and back-off efficiency within a wideband, a novel feed-forward DPA architecture for a digital polar transmitter with multi-mode dynamic-matching (DM) network is firstly introduced and demonstrated. To verify the mechanism mentioned above, two DPAs are implemented and fabricated, which are the only reported wideband DPAs operating above 3 GHz with record fractional bandwidths, i.e., 92% and 100.8%, respectively. The proposed DPAs (i.e., DPA-I and DPA-II) exhibit peak output power of 22.2 and 22.3 dBm and peak drain efficiency of 46.2% and 47.4%, respectively, with a 1.2-V supply. In DM modes, the saturated and 6-dB back-off drain efficiency of DPA-II achieve maximum improvements of 7.5% and 5.7%, respectively. The core chip-sizes of the proposed DPAs (i.e., DPA-I and DPA-II) are 0.22 mm^2 and 0.24 mm^2, respectively. [ABSTRACT FROM PUBLISHER]

This paper proposes a smart wireless power transmission method, based on a two-step procedure, exploiting real-time beaming of time-modulated arrays. The sideband radiation phenomenon, which is usually a drawback of these radiating systems, is favorably used for intentional wireless power transfer (WPT): in a first step to precisely localize the tag to be powered and in the second one to perform directive WPT. The approach is first theoretically discussed, then the numerical procedure, which integrates full-wave analysis of the antenna array with nonlinear simulation of the modulated nonlinear feeding network, is used to validate the principle of operation and to include nonlinearities and electromagnetic couplings affecting the whole system performance. The procedure allows a flexible design of the time-modulated-array-based WPT system, taking into account the impact of different array elements layout and spacing on localization and power transmission performance. Experiment of the first step is carried out in a real indoor environment at 2.45 GHz: a TI MSP430 drives a Schottky-diode-based network to provide proper modulated RF excitations of the array elements. Measurements show that the system is able to select tags to be energized randomly distributed in a 100^\circ-scanning range. [ABSTRACT FROM PUBLISHER]

This paper presents a low switching-loss Dicke radiometer for W-band passive imaging systems. The equivalent switching loss introduced by the passive single-pole-double-throw (SPDT) switch in the conventional radiometer is significantly reduced by the proposed single-pole-double-throw distributed amplifier (SPDT-DA), which leads to radical improvement on the receiver’s noise performance. The Dicke radiometer consisting of a SPDT-DA, a four-stage low noise amplifier (LNA) and a power detector is fully integrated in a 0.13-\mu\ m SiGe BiCMOS chip. With the 0.93-dB equivalent switching loss at 91 GHz of the SPDT-DA, the total noise figure (NF) of 8.4 dB at 91 GHz is achieved by the SPDT-DA followed by the LNA. With a power consumption of 28.5 mW, the radiometer obtains an overall RF gain of 42 dB and a noise equivalent temperature difference (NETD) of 0.21 K with 30-ms integration time. The two-dimensional imaging experiment with object distance of 0.7 m is successfully carried out with the radiometer chip. [ABSTRACT FROM AUTHOR]

In this paper, we present a distributed positioning system for indoor environment based on a mesh of compact independent anchor nodes. Each node is built of low-cost off-the-shelf components and operates as specialized access points capable of standard connectivity at 2.45 GHz. The key technology for the localization strategy is the switched beam antenna (SBA), which enables a space division multiple access (SDMA) paradigm. The coordinated operation of SBA-equipped anchor nodes constitutes a legacy unmodified IEEE 802.11 network which can exploit the multiplexing mechanism. The latter is the driving force of the estimation strategy, with the positional information obtained as the result of a maximum likelihood algorithm driven by the comparison of a real-time received signal strength indicator (RSSI) with the predicted signal level distribution, which can be estimated and stored without the need of lengthy offline measurement. The signal level prediction is based on a simple propagation model which is effective because benefits of both the elementary antenna radiation beams directivity and the circular polarization operation, two strong aids for the mitigation of the multipath impairment. In turn, these feature make the estimation procedure tolerant to noisy power measurements, hence particularly suitable for cost-effective solutions based on RSSI. Experimental validations demonstrate the performance of a network composed of four anchors arranged in a 2.6\,\times\, 3.8 m^2 mesh in a 6\,\times\, 7 m^2 office room, and dealing with a single target node. The mean error inside the mesh area is 63 cm while the mean error in the entire room is 1.1 m. Focusing on the cumulative distribution of the error, the 90th percentile value is 1 m considering only the mesh and 1.9 m for the entire room. [ABSTRACT FROM PUBLISHER]

This paper presents the design and characterization of dc–dc converters operating at microwave frequencies. The converters are based on GaN transistor class-E power amplifiers (PAs) and rectifiers. Three topologies are presented, which are: 1) a PA and synchronous rectifier, requiring two RF inputs; 2) a PA and self-synchronous rectifier with a single RF input; and 3) a power oscillator with a self-synchronous rectifier with no required RF inputs. The synchronous 1.2-GHz class-\E^2 converter reaches a maximum efficiency of 72% at 4.6 W. By replacing the RF input at the rectifier gate with a specific termination, a self-synchronous circuit demonstrates 75% efficiency at 4.6 W, with a maximum output power of 13 W at 58% efficiency. In the third topology, the PA is replaced by a power oscillator by providing correct feedback for class-E operation, resulting in a circuit requiring no RF inputs. This oscillating self-synchronous dc–dc converter is demonstrated at 900 MHz with an efficiency of 79% at 28 V and 12.8-W output power. Self-synchronous class-E transistor rectifier operation is analyzed theoretically in the time domain and validated with harmonic-balance simulations using an improved nonlinear model for a GaN HEMT. The simplified theoretical analysis provides a useful starting point for high-efficiency self-synchronous power rectifier design, which can, in turn, be extended to high-efficiency oscillating power inverter design. [ABSTRACT FROM AUTHOR]

This paper describes analysis of the far-out spurious noise and a method to reduce this noise in an envelope-tracking power amplifier (ET PA). The ET PA delivers a higher efficiency and a better linearity than the stand-alone PA, simultaneously. However, the ET PA generates spectral regrowth at a far-out spurious emission domain. The noise sources are analyzed, and the noise effects on a RF PA are estimated using mathematical models of the RF PA and supply modulator. To reduce the noise, a wideband supply modulator is designed using 40-nm CMOS process for a high speed operation, and an additional capacitor is connected to the supply line of the PA. These noise reduction techniques significantly reduce the far-out spurious noise of the ET PA to a level similar to that of the stand-alone PA. For a 10-MHz bandwidth and 6.5-dB peak-to-average power ratio long term evolution signal, the ET PA delivers a power-added efficiency of 41.8%, a gain of 23.8 dB, and an evolved universal terrestrial radio access adjacent channel leakage ratio of -34.3~dBc at an average output power of 27 dBm and an operating frequency of 1.85 GHz. The noise power spectrum densities of the ET PA are -130.3/-133.7~dBm/Hz at 1.93/1.99 GHz, respectively, which is limited by our PA itself. [ABSTRACT FROM PUBLISHER]

Design and analysis of two high-speed high dynamic-range track-and-hold amplifiers are presented in this paper using 65- and 90-nm CMOS processes. To achieve remarkable circuit performance in the advanced CMOS regime, the cascode topology with an inductive peaking technique and the distributed topology are employed in the track-and-hold amplifiers. The circuit topology is investigated to obtain the design methodology of the CMOS high-speed high dynamic-range track-and-hold amplifier. The theoretical calculation is presented to completely verify the design concept. Moreover, the proposed CMOS track-and-hold amplifiers demonstrate wide bandwidth and good linearity. With a dc power consumption of 197 mW, the 65-nm CMOS track-and-hold amplifier features an input bandwidth of up to 7 GHz, a spurious-free dynamic range (SFDR) of 44.6 dB, and a total harmonic distortion (THD) of -\44.5 dB. With a dc power consumption of 216 mW, the 90-nm CMOS track-and-hold amplifier features an input bandwidth of 19 GHz, an SFDR of 47.5 dB, and a THD of -\44.5 dB. The proposed CMOS track-and-hold amplifiers are suitable for the high-resolution high-speed analog-to-digital converter with low dc supply voltage and power. [ABSTRACT FROM PUBLISHER]

This paper presents high power test results for high temperature superconductor (HTS) filters having six different configurations. The results demonstrate the possibility of realizing narrow band HTS filters that are capable of handling 30-50 W at 77 K. The paper also introduces a procedure for comparing the power handling capability of HTS filters with different RF characteristics. Issues related to thermal design of high power HTS filters are discussed in detail. [ABSTRACT FROM AUTHOR]

This paper presents an envelope tracking (ET) transmitter architecture based on the combination of a novel 3-bit (N = 3) supply modulator and digital predistortion (DPD). The proposed power converter is based on a direct digital-to-analog conversion architecture that implements the binary-coded sum of N isolated dc voltages, allowing the synthesis of an output waveform with L = 2^N voltage levels, with a binary distribution in the range \Delta V = VM - VO (maximum voltage VM, offset voltage Vo). This solution provides a better voltage resolution VS = \Delta V/(2^{N}-1) with respect to typical multilevel switched-sources topologies (VS = \Delta V/N). The improved voltage resolution enables the correction of the residual discretization error in the ET transmitter by means of DPD of the RF signal without the need of an auxiliary linear envelope amplifier. The proposed ET solution has been tested with an L-band 30-W lateral-diffused MOS RF high power amplifier (RF HPA) with 1.4- and 10-MHz long-term-evolution signals. In these conditions the converter demonstrated 92% and 83% efficiency, respectively, whereas the congregate efficiency of the transmitter are 38.3% and 23.9% at 5.5 and 1.9 W of average RF output power, respectively. These performances correspond to an improvement of 17.2 and 17.9 points for the power-added efficiency of the RF HPA and to 13.4 and 13 points of improvement for the efficiency of the entire transmitter with respect to fixed bias operation. [ABSTRACT FROM AUTHOR]

This paper discusses the design and implementation of a 94-GHz phased-array transceiver front-end in SiGe BiCMOS that is capable of receiving concurrently in both vertical (V) and horizontal (H) polarizations and time-duplexed transmission in either polarization. The compact front-end is implemented in \1.3 mm\times \ 1.45 mm of silicon area to ensure compatibility with a scalable phased-array tile approach with \lambda/2~(\sim \1.6 mm) spacing between elements. Each transceiver front-end includes variable transmitter (TX) and receiver (RX) gain and 360^\circ variable phase shift in TX and RX. Co-integration of the transmit-receive (T/R) switch with the power amplifier (PA) and low-noise amplifier (LNA) matching network minimizes switch impact on RX noise figure (NF). A varactor-based passive reflection-type phase shifter (RTPS) is shared between the TX and RX to reduce area. Analysis of loss mechanisms in on-chip RTPS leads to a novel RTPS load that minimizes RTPS loss while ensuring that the amplitude variation across phase shift is <\1 dB. In RX mode, the front-end achieves 30-dB RX gain, bandwidth of 15 GHz (84–99 GHz) with < 10-dB NF in the high-gain mode. In TX mode, the front-end achieves > 2-dBm saturated output power and > 0-dBm output-referred 1-dB compression point (OP1dB) in V and H polarizations (time-duplexed), 30-dB gain, and 8-GHz bandwidth (89–97 GHz). The 94-GHz phase shifters achieve full 360^\circ variable phase shift with 5-bit phase resolution (11.25^\circ resolution) and <3^\circ~\rms error and < 1-dB rms gain error at 94 GHz. The front-end consumes 160 mW in RX mode for dual-polarization concurrent reception/phase-shifting and 116 mW in TX mode for time-duplexed V and H output in the W-band. [ABSTRACT FROM PUBLISHER]

This paper presents the design of a fully integrated high-efficiency and high-power RF frontend for the IEEE 802.11p standard in GaN HEMT technology. An embedded transmitter/receiver (Tx/Rx) switching scheme and a dual-bias power amplifier linearization technique are used to improve Tx efficiency and linearity. An accurate physics-based nonlinear large-signal device model is developed and used for the design, providing insight into the impact of the behavioral nuances of the GaN HEMTs on RF circuit performance. The fully integrated RF frontend is fabricated in 0.25-\mu\m GaN-on-SiC technology and occupies only 2 mm \times 1.2 mm. The Tx branch achieves 48.5% drain efficiency at 33.9 dBm, Psat with 28-V supply. With orthogonal frequency-division multiplexing modulated signals, it achieves 30% average efficiency at 27.8-dBm output power while meeting the -25-dB error vector magnitude limit without predistortion. The Rx branch achieves +22-dBm output third-order intercept point with 3.7-dB noise figure at 12-V supply. The fully integrated high-efficiency and linear RF frontend designed with physics-based RF GaN compact models is demonstrated for the first time for future device-to-device applications. [ABSTRACT FROM AUTHOR]

Coupled electromagnetic resonances have various important applications in microwave engineering. Among them, the newly discovered electromagnetically induced transparency (EIT) has attracted much interest. In this paper, we explore the use of configurable electrically induced transparency to construct a microwave “diffractive medium” whose air-like optimally matched transparency and metal-like optimally reflective opacity can be conveniently switched by a binary dc voltage. Different from EITs based on closely coupled resonances, we use decoupled electrically induced resonances to achieve a low-loss transparency along with an optimal impedance matching with air. Satisfying the condition of a lossless perfectly matched layer, such transparency and opacity can be obtained in a wide range of incident angles. We validate our approach by experimentally demonstrating two electrically controlled steering antennas based on diffractive grating effect, both with thin planar apertures and binary digital control circuits. The proposed approach can be extended to higher frequencies, achieving configurable diffractive devices at millimeter-wave and terahertz frequencies. [ABSTRACT FROM PUBLISHER]

In this paper, a three-way reconfigurable power divider/combiner is proposed based on novel switch element with matching network (SEMN) and reconfigurable impedance transformer network (RITN). A good matching performance and a high isolation of the SEMN with one p-i-n diode can be obtained by the parasitic inductance and reverse capacitance of the p-i-n diode involved in matching circuits. With different parameters of one p-i-n diode under forward bias and reverse bias, the reconfigurable impedance matching can be obtained by the RITN with a simple structure. By using four RITNs and nine SEMNs, the three-way reconfigurable power divider/combiner can provide seven different states in the three-path mode, the two-path mode, and the single-path mode. For verification, a 5-GHz three-way reconfigurable power divider/combiner is designed and fabricated. In the three-path mode, measured insertion losses from port 1 to transmission ports (port 2, port 3, and port 4) are less than 0.74 dB and the isolations between transmission ports are higher than 32.1 dB. In the two-path mode with three states, the measured insertion losses are less than 0.93 dB; the isolations between transmission ports, transmission ports and isolation ports, and port 1 and isolation ports are higher than 27.5, 35.1, and 30.5 dB, respectively. In the single-path mode with three states, the measured insertion losses are less than 1.13 dB; the measured isolations between transmission ports and isolation ports are higher than 28.8 dB, and the isolations between port 1 and isolation ports are higher than 28.2 dB at the design frequency. [ABSTRACT FROM PUBLISHER]

The recently introduced Class-EF power amplifier (PA) has a peak switch voltage lower than that of the Class-E PA. However, the value of the transistor output capacitance at high frequencies is typically larger than the required Class-EF optimum shunt capacitance. Consequently, soft-switching operation that minimizes power dissipation during off-to-on transition cannot be achieved at high frequencies. Two new Class-EF PA variants with transmission-line load networks, namely, third-harmonic-peaking (THP) and fifth-harmonic-peaking (FHP) Class-EF PAs are proposed in this paper. These permit operation at higher frequencies at no expense to other PA figures of merit. Analytical expressions are derived in order to obtain circuit component values, which satisfy the required Class-EF impedances at fundamental frequency, all even harmonics, and the first few odd harmonics as well as simultaneously providing impedance matching to a 50-\Omega load. Furthermore, a novel open-circuit and shorted stub arrangement, which has substantial practical benefits, is proposed to replace the normal quarter-wave line connected at the transistor's drain. Using GaN HEMTs, two PA prototypes were built. Measured peak drain efficiency of 91% and output power of 39.5 dBm were obtained at 2.22 GHz for the THP Class-EF PA. The FHP Class-EF PA delivered output power of 41.9 dBm with 85% drain efficiency at 1.52 GHz. [ABSTRACT FROM AUTHOR]

This paper presents two different types of high-power gallium–nitride (GaN) phase shifters designed for X-band (8–12 GHz), but offering good performance over a much wider band. The first is a 22.5^\circ switched-filter phase shifter, which has much wider bandwidth than is typically found with this configuration, while maintaining low insertion loss (<2 dB), good return loss (>11.15 dB), and an amplitude imbalance of less than 1.03 dB across X-band. The 1-dB compression point was higher than laboratory equipment was able to measure (>38 dBm) and the phase shifter monolithic microwave integrated circuit exhibited an input-referred third-order intercept point (IIP3) of 46.2 dBm. The second phase shifter is a novel design, which promises wide bandwidth (in our case, limited by the single-pole double-throw switch we have also designed), but which achieves decent insertion loss (5 dB), good return loss (better than 11 dB), and very low phase variation (1^\circ) across X-band, also with 22.5^\circ phase shift. It offers a 1-dB compression point of 30.1 dBm and an IIP3 of 46.3 dBm. The components for a 45^\circ differential phase shift using the same structure were also fabricated and verified with measurements. The high-power phase shifters have been fabricated in a 0.5-\mu\ m GaN HEMT process and were designed using an accurate customized switch field-effect transistor model. [ABSTRACT FROM PUBLISHER]

In this paper, a dynamic stack-controlled CMOS FET RF power amplifier (PA) is developed to enhance the efficiency of the envelope tracking power amplifier (ET PA) system for low-voltage operation. The power cell used in the two-stage PA is a quadruple-stacked FET structure with dynamic stacking controller to reconfigure the power cell into the quasi-triple or quasi-double stacks according to the magnitude of the input envelope signal. The proposed power cell boosts the peak efficiency in the low VDD region by bypassing the stack entering the triode region and reoptimizing the load impedance so that all the FETs operate under the saturation and the optimum load conditions. A detailed analysis is presented to understand the gain and phase step discontinuities at the stack switching points, and the circuit techniques to equalize the gain and phase between the adjacent stack configurations are developed. The proposed two-stage stack-controlled PA is fabricated with a 0.32-\mu\ m silicon-on-insulator (SOI) CMOS process together with the envelope amplifier (EA). Full long-term evolution (LTE) characterization is performed using LTE signals with a peak-to-average power ratio (PAPR) of 6.7 dB and signal bandwidths (BW) of 10 and 20 MHz. With 10-MHz signals, dynamic stacking provides 3.5% power added efficiency (PAE) improvement over the static stack at 25.7 dBm, resulting in 47.5% PAE with 26.6-dB gain. A 20-MHz LTE test shows an overall PAE of 45.9% with an evolved universal terrestrial radio access (E-UTRA) adjacent channel leakage ratio (ACLR) of -33 dBc with memoryless digital predistortion. Even with the lower efficiency of the EA compared with the state-of-the-art results, the measured overall system efficiency with 3.4 V maximum voltage is comparable with those reported using GaAs HBT's with 5 V supplies, which clearly demonstrates the advantages of the proposed dynamic stack control. [ABSTRACT FROM AUTHOR]

This paper presents a reconfigurable dual Q- and W-band bidirectional amplifier and a V-band active circulator in a 45-nm CMOS silicon-on-insulator (SOI) technology. The circuits rely on reconfigurable feedback networks to manipulate the traveling wave along a transmission line. The dual Q- and W-band bidirectional amplifier operates at 40 and 81 GHz, with peak gain of more than 4.2 dB in all modes of operation. The V-band active circulator is reconfigurable to operate in four different modes of operation: clockwise, counter-clockwise, quasi-circulation, and as a thru between port 1 and port 2. The circulator is measured to have an insertion loss of 7.4 dB with isolation between any pair of isolated ports better than 18 dB from 62-75 GHz. The circuit technique proposed here can easily be adapted to operate at different millimeter-wave frequency bands. [ABSTRACT FROM AUTHOR]

With the aid of tri-operational mode synthesized transmission lines, an innovative heterogeneous integrated phased array having the functions of beam-switching and retrodirection in three individual bands is proposed and demonstrated. The key innovation is the array feeding network, capable of automatically reconfiguring its topology into three states without applying any active switch. In the low band, the feeding circuit, and hence, the entire system function as a beam-switching array using the Butler matrix for communication and positioning. In the mid and high bands, the integrated array rearranges its feeding network into pairs of isolated delay lines and becomes a Van Atta array and a phase-conjugating array, respectively, to re-radiate the signals to the direction of arrival. The core building blocks are the three-channel selector, tri-mode coupler, and diplexer, all realized by synthesized transmission lines with rigorous design formulae. The operational principle is first introduced, followed by the design and implementation of the key components. A phase compensation scheme is discussed to complete the tri-mode array design. This unique concept is experimentally verified using the radiation characteristics of the integrated array at the end of this paper. [ABSTRACT FROM AUTHOR]

This paper presents the first truly wireless 24-GHz round-trip time-of-flight local positioning frontend with an integrated CMOS transceiver. The transceiver in 130-nm CMOS technology features a novel receiver/transceiver switching concept, which reduces RF losses between the receiver/transmitter and antenna and drastically improves the transmit/receive isolation. The low-power RF transceiver chip was integrated with a digital signal-processing unit and mounted on a circuit board to form a system-level demonstrator of a secondary radar node incorporating synchronization and a distributed localization algorithm. The performance of the self-organizing localization network is evaluated in an indoor setup using comparisons with reference trajectories. Experimental results show a distance precision between the active nodes close to the theoretical optimum that can be achieved with the used signal parameters, as well as an absolute localization error in the centimeter range. [ABSTRACT FROM AUTHOR]

This paper presents a new symmetrical field-effect transistor (FET) model suitable for microwave switches. The model takes advantage of the inherent symmetry of typical switch devices, justifying a new small-signal model where all intrinsic model parameters can be mirrored between the positive and negative drain–source bias regions. This small-signal model is utilized in a new and simplified approach to large-signal modeling of these type of devices. It is shown that the proposed large-signal model only needs a single charge expression to model all intrinsic capacitances. For validation of the proposed model, small-signal measurements from 100 MHz to 50 GHz and large-signal measurements at 600 MHz and 16 GHz, are carried out on a GaAs pHEMT. Good agreement between the model and the measurements is observed under both small- and large-signal conditions with particularly accurate prediction of higher harmonic content. The reduced measurement requirements and complexity of the symmetrical model demonstrates its advantages. Further, supporting operation in the negative drain–source voltage region, the model is robust and applicable to a variety of circuits, e.g., switches, resistive mixers, oscillators, etc. [ABSTRACT FROM PUBLISHER]

In this paper, a surface acoustic wave (SAW)-less receiver (RX) front-end adopting switchable front-end architecture has been presented for second-generation/third-generation/fourth-generation cellular applications. Depending on the RX–transmitter (TX) frequency separation, a favorable down-mixing architecture is selected between a current-sampling mixer and a voltage-sampling mixer. The proposed switchable architecture meets the specification of an input-referred second-order intercept point (IIP2) for the SAW-less RX while minimizing the power consumption. The implemented RX front-end consists of a wideband capacitor cross-coupled common-gate low-noise amplifier, a 25% duty-cycle passive mixer with IIP2 calibration circuitry, a baseband transconductor, and a trans-impedance amplifier. Fabricated in a 65-nm CMOS process, the SAW-less RX front-end provides conversion gain of 42 dB, and achieves noise figure of below 3.3 dB, out-of-band input-referred third-order intercept point of -\2 dBm, and IIP2 of more than 56 dBm. It draws an average current of 14.8 mA from 1.2 V. The die area is 1.71 mm^2. [ABSTRACT FROM PUBLISHER]

This paper presents a wideband 2\times13-bit in-phase/quadrature-phase (I/Q) RF digital-to-analog converter-based all-digital modulator realized in 65-nm CMOS. The isolation between I and Q paths is guaranteed employing 25% duty-cycle differential quadrature clocks. With a 1.3-V supply and an on-chip power combiner, the digital I/Q transmitter provides more than 21-dBm RF output power within a frequency range of 1.36–2.51 GHz. The peak RF output power, overall system, and drain efficiencies of the modulator are 22.8 dBm, 34%, and 42%, respectively. The measured static noise floor is below -160 dBc/Hz. The digital I/Q RF modulator demonstrates an IQ image rejection and local oscillator leakage of -65 and -68 dBc, respectively. It could be linearized using either of the two digital predistortion (DPD) approaches: a memoryless polynomial or a lookup table. Its linearity is examined using single-carrier 4/16/64/256/1024 quadrature amplitude modulation (QAM), as well as multi-carrier 256-QAM orthogonal frequency-division multiplexing baseband signals while their related modulation bandwidth can be as high as 154 MHz. Employing DPD improves the third-order intermodulation product (IM3) by more than 25 dB, while the measured error vector magnitude for a “single-carrier 22-MHz 64-QAM” signal is better than -28 dB. [ABSTRACT FROM AUTHOR]

This paper presents the circuit techniques to achieve superior linearity and isolation for a single-pole six-throw transmit/receive (T/R) switch designed for GSM/W-CDMA dual-band operation at 0.85–0.9 and 1.8–1.9 GHz. Implemented in a 0.18-\mum thick-film silicon-on-insulator (SOI) CMOS process, the switch employs an LC-tuned asymmetric topology for the transmit (Tx) and receive (Rx) branch to handle the high-power GSM transmitter requirement. The proposed design also features a switchable double LC-tank acting as a variable impedance block to relax the tradeoff among linearity, insertion loss (IL), and isolation. Feed-forward capacitors, ac-floating bias techniques, and floating-body SOI devices are utilized to further improve the linearity. The measured P-0.1\ {dB}, IL and Tx–Rx isolation in the lower and upper band are 37.2–35.6 dBm, 0.43–0.75 dB, and 45–37 dB, respectively. The proposed T/R switch design in SOI CMOS is an important building block toward more compact and lower cost RF frond-end modules, which integrate the switch, antenna tuning module, and control logic on the same chip. [ABSTRACT FROM AUTHOR]

This paper presents the design and characterization of compact high-power RF microelectromechanical system single-pole single-throw (SPST) and single-pole four-throw (SP4T) metal-contact switches. The SPST design results in a contact force of 1.9–2.8 mN at 80–90 V distributed over eight contacts and using four independent quadrants for actuation. The SP4T is a derivative of the SPST and results in a contact force of 0.45–0.7 mN per switch at 80–90 V. S-parameter measurements show an up-state capacitance of 70 and 17 fF along with a down-state resistance of 1–2 and 2–4 \Omega using Au-to-Ru contacts for the SPST and SP4T switches, respectively. The switch pull-in and release voltages are 50 and 45 V, respectively, and the switching time is t on \sim \ 10~\mu\ s and t off \sim \ 2~\mu\ s. The SPST and SP4T are capable of handling 10 and 2 W up to 100 million cycles, and the SPST has been tested with 30 W of power up to 30 million cycles before failure (all cold switched). The application areas are in compact high-power applications such as wireless communication systems and base-stations. [ABSTRACT FROM AUTHOR]

This paper presents a novel concept of a millimeter-wave waveguide switch based on a microelectromechanical (MEMS)-reconfigurable surface with insertion loss and isolation very similar to high performance but bulky rotary waveguide switches, despite its thickness of only 30 \mu\m. A set of up to 1470 micromachined cantilevers arranged in vertical columns are actuated laterally by on-chip integrated MEMS comb-drive actuators, to switch between the transmissive state and the blocking state. In the blocking state, the surface is reconfigured so that the wave propagation is blocked by the cantilever columns short-circuiting the electrical field lines of the TE10 mode. A design study has been carried out identifying the performance impact of different design parameters. The RF measurements (60–70 GHz) of fabricated, fully functional prototype chips show that the devices have an isolation between 30 and 40 dB in the off state and an insertion loss between 0.4 and 1.1 dB in the on state, of which the waveguide-assembly setup alone contributes 0.3 dB. A device-level yield analysis was carried out, both by simulations and by creating artificial defects in the fabricated devices, revealing that a cantilever yield of 95% is sufficient for close-to-best performance. The actuation voltage of the active-opening/active-closing actuators is 40–44 V, depending on design, with high reproducibility of better than (\sigma=\ 0.0605 V). Lifetime measurements of the all-metal, monocrystalline-silicon core devices were carried out for 14 h, after which 4.3 million cycles were achieved without any indication of degradation. Furthermore, a MEMS-switchable waveguide iris based on the reconfigurable surface is presented. [ABSTRACT FROM AUTHOR]

This paper presents a gallium nitride (GaN)-based hybrid current-mode class-S (CMCS) power amplifier (PA) using a bandpass delta–sigma modulator (BPDSM) for a 955-MHz LTE signal. To enhance the drain efficiency of the CMCS PA, the chip-on-board (COB) technique, which can reduce the external parasitic components of the packaged transistor and allow fast switching operation at high frequencies by minimizing distortion of the pulse waveform, is adopted. Also, GaN Schottky barrier diodes are fabricated in-house to protect the switching transistor against the high negative voltage swing. The differential output filter and balun composed of lumped LC resonators are integrated at the back of the switching transistor to extract amplified LTE signal from the output rectangular waveform, and the fabricated CMCS PA is measured and analyzed at four different states of BPDSM according to the coding efficiency from different input power level to obtain higher power and efficiency. Finally, a cavity bandpass filter (BPF) is added to the output circuit for a more accurate reduction of the harmonics and out-of-band noise signals to enhance system efficiency. From the measured results for an 8.5-dB PAPR 3 G LTE 10-MHz input signal, the proposed CMCS PA has a maximum average output power of 37.61 and 30.78 dBm, and the resulting drain efficiencies of 33.3% and 38.6% with the drain voltage of 19 and 7 V, respectively. [ABSTRACT FROM AUTHOR]

In this paper, a new envelope amplifier (EA) scheme incorporating a linear regulator array is presented. The proposed EA achieves a higher efficiency over a wide envelope range utilizing multiple linear regulators. The linear regulators biased as multiple supply voltages are responsible for delivering a partial envelope current, ensuring high efficiency. A simulation revealed the superior performance efficiency of the proposed scheme in terms of the instantaneous envelope voltage compared with that of a conventional EA. Based on the simulation results, an envelope tracking (ET) amplifier consisting of the proposed EA was implemented using a commercially available 60-W gallium–nitride (GaN) device. The experimental results show that the implemented ET system has an overall efficiency of 47.8% and a gain of 14 dB at an average output power of 40.8 dBm. In this situation, the spectral performance is less than -\49.5 dBc using the optimum digital predisotortion functionality. [ABSTRACT FROM PUBLISHER]

Design techniques for a load-independent low-power low-phase-noise CMOS LC direct bulk-coupled quadrature voltage-controlled oscillator (DBC-QVCO) is presented in this paper. A capacitor tapping technique is used to lower the phase noise and achieve load-independent frequency of oscillation. Class-C operation is used to further reduce the phase noise and power consumption. Quadrature coupling is achieved using bulk coupling, leading to reduction in both power and area. The DBC-QVCO has been implemented in a standard 0.18-\mu\m BiCMOS process and occupies an area of 0.3 \mm^2. The implemented DBC-QVCO achieves a measured phase noise of -114.2~dBc/Hz at 1-MHz offset from the 6.26-GHz carrier while consuming only 3.2 mW from a 1-V power supply. The DBC-QVCO achieves a figure of merit (FOM) of -185.1 dBc/Hz and an FOM with area of -190.3 dBc/Hz, which are among the best compared with recently published QVCOs operating in a similar frequency range. [ABSTRACT FROM AUTHOR]

This paper describes the design and implementation of a package-integrated Chireix outphasing RF switch-mode power amplifier (PA). The optimum loading conditions, based on class E, and the Chireix compensation elements are provided to the active devices by a dedicated low-loss bondwire-based transformer power combiner that enables a very small form factor and low cost. The realized prototype achieved 70.6-W peak power with 73% peak drain efficiency at 2.3 GHz and 28 V, and up to 81% peak drain efficiency at 2.2 GHz and 20 V. When operated for maximum power at 28 V, it reached 53.5%/43.5% average drain/total efficiency for a 9.6-dB peak-to-average-power-ratio W-CDMA signal at 2.3 GHz with low ACLR1/2 levels ( -\49/-\56 dBc after memoryless digital predistortion). Moreover, from 2.1 to 2.4 GHz, the realized PA demonstrated more than 50% drain efficiency across >\260, >\160, and >\80 MHz at 6-, 8-, and 10-dB back-off, respectively. [ABSTRACT FROM PUBLISHER]

This paper presents a high-power high-efficiency wideband suboptimum Class-E RF power amplifier based on a packaged high-power GaN HEMT. It uses a simple double-reactance compensation and impedance transformation load network that includes device intrinsic capacitance, package parasitics, low-loss microstrip transmission lines, and lumped components. This load network makes the GaN HEMT operate in suboptimum Class-E from 900 to 1500 MHz (50% fractional bandwidth at 1200 MHz). The amplifier can operate both in continuous wave and pulsed modes over its full bandwidth without tuning. It delivers up to 180-W output power with up to 85% drain efficiency and PAE=81\%. To the best of the authors' knowledge, the amplifier proposed in this work outperforms commercial grade amplifiers that operate in the same frequency band with similar output power levels. Direct applications for this amplifier include mobile satellite communications transmitters, envelope elimination and restoration digital audio broadcasting transmitters, and power stages for primary and secondary RADAR transmitters. [ABSTRACT FROM PUBLISHER]