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In this paper, we describe a design of a mixed-signal circuit for an binary neuron (a.k.a perceptron, threshold logic gate) and a methodology for automatically embedding such cells in ASICs. The binary neuron, referred to as an FTL (flash threshold logic) uses floating gate or flash transistors whose threshold voltages serve as a proxy for the weights of the neuron. Algorithms for mapping the weights to the flash transistor threshold voltages are presented. The threshold voltages are determined to maximize both the robustness of the cell and its speed. The performance, power, and area of a single FTL cell are shown to be significantly smaller (79.4%), consume less power (61.6%), and operate faster (40.3%) compared to conventional CMOS logic equivalents. Also included are the architecture and the algorithms to program the flash devices of an FTL. The FTL cells are implemented as standard cells, and are designed to allow commercial synthesis and P&R tools to automatically use them in synthesis of ASICs. Substantial reductions in area and power without sacrificing performance are demonstrated on several ASIC benchmarks by the automatic embedding of FTL cells. The paper also demonstrates how FTL cells can be used for fixing timing errors after fabrication [ABSTRACT FROM AUTHOR]

Most memristor-based associative memory neural networks are focused on classical conditioning and ignored operant conditioning. In this paper, a memristor-based neural network of operant conditioning accorded with biological feature is designed. The designed circuit includes a voltage control module, an operant module and synapse modules. It realizes learning, forgetting, long-term memory, reinforcement and punishment functions based on variable synapse structure and double self-protection measure. Meanwhile, the four factors that affect operant conditioning such as contingency, immediacy, magnitude and deprivation are discussed and implemented. The simulation results in PSPICE show that the circuit can be used to simulate actual conditioned reflex and complicated applications. The memristor-based neural network circuit of operant conditioning provides more references for further development of neural networks. [ABSTRACT FROM AUTHOR]

This paper presents a low-power constant subthreshold transconductance reference circuit that produces a constant transconductance by subtracting the output currents of two independent transconductance references. By taking the difference between the output currents of the two independent transconductance references, process, voltage and temperature variations are reduced by minimizing the effects of channel length modulation and drain-induced barrier lowering without relying on feedback to regulate the drain voltage. The proposed reference, fabricated in TSMC’s 130 nm process and testing with off-chip temperature-insensitive resistors, can provide a constant transconductance over a temperature range of −30 to 120°C, and a supply voltage range of 0.5 to 1.7 V. The experimental result of the proposed transconductance reference shows an average variation of ±0.8% over temperature for the entire operating voltage range and an average variation of ±1.97% over voltage for the entire operating temperature range. Through the subtraction, the proposed circuit also shows less variation across process corners compared to the conventional constant transconductance reference. The proposed constant transconductance reference exhibits the highest power efficiency (transconductance over power consumption) amongst the reported constant transconductance references. At 0.5 V, the proposed transconductance reference produces a transconductance of 21.46 $\mu \text{S}$ , while consuming 1.95 $\mu \text{W}$. [ABSTRACT FROM AUTHOR]

In this paper it is proposed and explored the use of the Dickson charge pump (CP) to amplify time-variant signals. The study has been carried out through a theoretical analysis that provides an in-depth comprehension of the behavioral equations and the main design metrics commonly used to evaluate the performance of amplifiers. Starting from the analytical models, we show the conditions upon which the CP can be modeled with an equivalent small signal circuit and can amplify a signal. Then, assuming the CP working in the widest operative conditions, small-signal, large-signal and noise analysis are carried out. The results have been validated by extensive simulations and measurements on a proof of concept using a 130 nm CMOS technology. [ABSTRACT FROM AUTHOR]

This paper presents two high-efficiency charge pumps (CPs) by utilizing the gate voltage boosting technique (GVBT). Unlike traditional bulk-CMOS and all-NMOS CPs, an input bias voltage is independently applied to the gate terminal, and it improves the current driving capability without the need of large pumping capacitors or high-frequency clocks. Meanwhile, the GVBT decouples the state of transistors from the clocks connected to the pumping capacitor, and it can eliminate the reversion loss in both main and auxiliary circuits. Fabricated in a 0.18- $\mu \text{m}$ standard CMOS technology, the single-stage all-NMOS CP achieved a maximum output voltage of 6.589 V and a peak power efficiency of 80.08%. We also implemented the bulk-CMOS CP with GBVT for comparison, the single-stage all-NMOS CP achieved $\sim 1.24\times $ more output voltage than the bulk-CMOS CP under a load current of 1.5 mA. The voltage errors of the all-NMOS CP between the analytical and the measured results are less than 7%. [ABSTRACT FROM AUTHOR]

Back-bias control is a new degree of freedom brought by fully-depleted silicon-on-insulator (FDSOI) CMOS technologies, which can be used to control the oscillation frequency of voltage-controlled ring oscillators (VCROs). The resulting VCRO architecture is called a back-bias-controlled oscillator (BBCO). This paper compares it with the conventional current-starved ring oscillator (CSRO) topology in terms of power consumption and phase noise figure-of-merit (FoM), while taking practical design constraints of process-voltage-temperature (PVT) robustness and frequency tuning range into account. The proposed comprehensive analysis takes advantage of relevant and compact analytical models, as well as extensive pre-layout simulation results. The comparison is made at four different target oscillation frequencies, which are representative of frequency synthesis for WiFi/Bluetooth/LPWAN wireless communications and of clock generation for smartphone/Internet-of-Things processors: 300 MHz, 868 MHz, 2.45 GHz, and 5.18 GHz. In 28-nm FDSOI technology, the results demonstrate that BBCOs can intrinsically reach 1.69 to $4.63\times $ lower minimum power consumption and slightly better FoM values than CSROs. [ABSTRACT FROM AUTHOR]

This paper presents a high-precision bandgap voltage reference (BGR) with high-order temperature compensation. The compensation signal is generated by using both strong-inversion MOSFETs and Bipolar Junction transistors (BJTs), which cancels the high-order nonlinear term $T\ln (T)$ in the BJT base-emitter voltage (VBE), and thus a low temperature coefficient (TC) over a wide temperature range is achieved. The proposed BGR circuit is fabricated in a 0.18- $\mu \text{m}$ CMOS process with an active area of $0.256 m{m^{2}}$ and a max power consumption of 1.35 mW. A minimum TC of 0.706 ${\mathrm{ppm}}/{}^ \circ C$ from $- 25\,\,{}^ \circ C$ to 125 ${}^ \circ C$ is achieved after an 8-bit resistance trimming. The line sensitivity is 0.0146%/V operating from 3.2 V to 3.7 V. The BGR achieves a power supply rejection (PSR) of −63.4 dB and a noise spectrum density of $0.92 ~\mu \text{V}/\sqrt {Hz} $ at 10 Hz. [ABSTRACT FROM AUTHOR]

In this paper, the issue of open-switch faults of voltage source inverter (VSI) is studied, an adaptive fast voltage-based real-time open-switch fault location method is proposed. Firstly, for each switching period, the voltage deviation is calculated by the expected voltage and estimated actual voltage, they are obtained via the mixed logical dynamic model (MLDM) and measured currents, respectively. Then, the voltage deviation of each phase is employed as a fault variable. By this way, avoiding the use of additional hardware, and embedding easily in system. Furthermore, considering the impact of sampling error, parameter error, dead time, delay time, and transition time, the adaptive threshold is designed. Finally, simulations and experiments are executed to verify the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

This paper proposes a Differential-Input Body Bias Sense Amplifier (DIBBSA) with an auto-offset mitigation feature suitable for low-voltage SRAMs where the differential bitline signals are applied to the sources as well as to the body of the critical sensing transistors. We simulated and fabricated the proposed DIBBSA architecture with various operational modes in 65-nm CMOS technology to analyze body biasing’s effectiveness in mitigating the offset. The standard deviation of offset (σOS) was measured over 5120 SAs in 10 ICs. The iso-gate area reduction in σOS for the proposed DIBBSA-FL and DIBBSA-PD modes resulted in 68.1% and 61.9% compared to conventional Current Latch SA (CLSA) and 24.1% and 18.1% compared to Voltage Latch SA (VLSA) at 0.4 V supply and 25 °C, respectively. Carried out measurements on 512 SAs in an IC show the minimum required differential input voltage across the temperature range of 0 °C to 75 °C at 0.4 V is achieved to be 48% lower compared to CLSA and 28% lower compared to VLSA by both the DIBBSA-FL and DIBBSA-PD modes. [ABSTRACT FROM AUTHOR]

This article presents a fully dynamic latched comparator with a high-gain three-stage configuration and an extra parallel feed-forward path, able to achieve a delay of 26.8 ps and a data rate of 13.5 Gb/s with less than 10−12 BER for a 5 $\text{m}\text {V}_{\text {pp}}$ differential input ($\Delta V_{\textrm {I}}$) at 0.5 V common-mode ($V_{\textrm {CM}}$) and 1V supply ($V_{\textrm {DD}}$). Additionally, the reduced-stacking cascaded triple-latch arrangement enables a < 70ps delay down to 0.6 V $V_{\textrm {DD}}$. The comparator is analyzed and compared against two prior art circuits by means of derived delay and noise expressions, serving as design guidelines. The prototype comparator and its prior art are fabricated in 28 nm bulk CMOS, with delay, input-referred noise, energy/comparison, and area measurements highlighting the benefits and trade-offs of the proposed solution. [ABSTRACT FROM AUTHOR]

The failure probabilities of industrial SRAM cells fall below the ppm (10−6) range, disqualifying the computational-intensive Monte-Carlo simulations for efficient robustness assessment. Starting from a novel two-dimensional threshold voltage imbalance representation, we propose a new methodology for fast and accurate prediction of the subthreshold SRAM hold stability failure rate. The probability is derived in a closed form which involves the transistor threshold-voltage standard deviations and only requires the two quick DC extractions of the worst- and best-case static noise margins. We validate our approach on a Six-Transistor (6T) bitcell in 28 nm Fully Depleted Silicon-On-Insulator (FD-SOI) CMOS technology. Our method turns out to be especially insightful for comparative and sensitivity analyses, for instance to study the effect of supply voltage downscaling or temperature variations. Finally, we show that the achieved accuracy and the capability of estimating extremely low failure probabilities (down to 10−9), combined with the important gain in simulation and post-processing cost, makes our methodology attractive compared to other recent modelling works. [ABSTRACT FROM AUTHOR]

An odd-element half-wave-rectification superposition (OHS) technique is presented and verified for designing the high-multiplication factor frequency multipliers. The proposed OHS technique superposes N odd-element phase-shifted half-wave-rectification (HWR) fundamental signals ($f_{0}$) to extract the 2N-order harmonic (2N $f_{0}$) while canceling the fundamental ($f_{0}$) and the 2nd to (2N-1)th harmonics without extra filtering. Compared with the reported even-element half-wave-rectification superposition technique (EHS) technique, the proposed OHS technique can realize the same multiplication factor but requires only a half number of the input HWR signals. Thus, the proposed OHS technique can be applied to design the high-multiplication factor frequency multiplier that is difficult to be implemented using the reported EHS technique. To verify the validity of the proposed OHS technique, a differential $\times 6$ frequency multiplier with the input frequency range of 5-7GHz and output frequency range of 30–42 GHz was implemented in 65 nm CMOS process. The experimental results indicate that the implemented $\times 6$ frequency multiplier exhibits more than 23 dBc rejection to the fundamental and 2nd to 5th harmonics without the extra filter. The DC power consumption is 4.6 mW for the core circuit. [ABSTRACT FROM AUTHOR]

The millimeter-wave (mm-wave) single-pole double-throw (SPDT) switch designed in bulk CMOS technology has limited power-handling capability in terms of 1-dB compression point (P1dB) inherently. This is mainly due to the low threshold voltage of the switching transistors used for shunt-connected configuration. To solve this issue, an innovative approach is presented in this work, which utilizes a unique passive ring structure. It allows a relatively strong RF signal passing through the TX branch, while the switching transistors are turned on. Thus, the fundamental limitation for P1dB due to reduced threshold voltage is overcome. To prove the presented approach is feasible in practice, a 90-GHz asymmetrical SPDT switch is designed in a standard 55-nm bulk CMOS technology. The design has achieved an insertion loss of 3.2 dB and 3.6 dB in TX and RX mode, respectively. Moreover, more than 20 dB isolation is obtained in both modes. Because of using the proposed passive ring structure, a remarkable P1dB is achieved. No gain compression is observed at all, while a 19.5 dBm input power is injected into the TX branch of the designed SPDT switch. The die area of this design is only 0.26 mm2. [ABSTRACT FROM AUTHOR]

A 10.4-16-Gb/s reference-less and baud-rate clock and data recovery (CDR) circuit with a one-tap speculative decision feedback equalizer (DFE) is presented. The quarter-rate CDR circuit uses a pattern-based phase detector (PD) and the proposed FD. This wide-range FD is composed of a coarse FD and a fine FD (FFD) which share the same front-end comparators with the PD and the DFE. Thus, no extra comparators are required. In addition, by monitoring the drift direction of five samples on the five-bit data patterns, the FFD performs an error-free operation within a frequency error of 7.7%. Therefore, the CDR has a robust FD-to-PD transition. By using the proposed FD, this CDR circuit not only achieves a wide frequency capture range of 43%, but also has a short frequency settling time of $680~\mu \text{s}$. This CDR circuit is fabricated in 40-nm CMOS technology and occupies an active area of 0.1004 mm2. The total power of the receiver is 39.9mW at 16 Gb/s, and the calculated energy efficiency is 2.49pJ/b. [ABSTRACT FROM AUTHOR]

This article presents a highly-efficient radio frequency energy harvester that utilizes an extra matching network to produce a passively-amplified adaptive compensation voltage. The compensation voltage produced on the gate of the transistors reduces the transistors’ conduction loss by increasing the gate-source voltage when transistors are on and reduces the leakage current by producing a negative gate-source voltage when the transistors are off. This is the first work that produces an adaptive compensation voltage without using active components, resulting in a significantly higher conversion efficiency if passive components of high quality are utilized. The mathematical derivations show that the forward conduction loss and the leakage current of the transistors are minimized by utilizing the proposed technique, increasing the overall efficiency. The proposed rectifier is fabricated in a TSMC 130 nm standard CMOS process, and measurement results and simulation results are in good agreement. Measurement results show that the rectifier achieves the maximum efficiency of 61% and 63.4% for battery load of 1.2 V and 1.5 V, respectively, which is at least 20 % larger than the efficiency of the conventional Dickson’s rectifiers. [ABSTRACT FROM AUTHOR]