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In this work, impacts of the independent dual-gate (IDG) operation on performance and reliability of the polycrystalline-silicon (poly-Si) junctionless thin-film transistor (JL-TFT) with a nanosheet channel (~4 nm) are investigated. Compared to the single-gate (SG) operation, the JL-TFT with tied dual gate (DG) operation times maximum transconductance (${G}_{m\_{}{\text {max}}}$) improvement and 3.3 times driving current enhancement. The tied DG operation also exhibits better gate bias stress immunity than the SG operation although the tied DG stress causes more serious damages to the JL-TFT than the SG stress. As for the independent back gate (BG) voltage (${V}_{\text {BG}}$) operation mode, the ${V}_{\text {BG}}$ can provide a wide threshold voltage (${V}_{\text {TH}}$) tuning range ~2 V when the ${V}_{\text {BG}}$ is modulated from 0 to −4 V. The negative ${V}_{\text {BG}}$ bias stress would induce electron injection from the BG, resulting in positive ${V}_{\text {TH}}$ shift. Because the positive top gate voltage stress exhibits more serious electrical degradation than the negative ${V}_{\text {BG}}$ stress, using ${V}_{\text {BG}}$ to modulate the ${V}_{\text {TH}}$ of the JL-TFT will cause a slightly more serious reliability issue. The results show the feasibility of using independent ${V}_{\text {BG}}$ to adjust the ${V}_{\text {TH}}$ of the JL-TFTs to meet the multiple- ${V}_{\text {TH}}$ requirement of advanced integrated circuits. [ABSTRACT FROM AUTHOR]

In this work, the impacts of oxygen (O2) plasma treatment on the performance and negative bias temperature instability (NBTI) of tunnel thin-film transistors (T-TFTs) with polycrystalline-silicon channel material are studied. After O2 plasma treatment, the T-TFT exhibits that the minimum leakage current is suppressed from 134 to 7 pA and the subthreshold swing (SS) is decreased from 0.602 to 0.508 V/decade. In addition, the degradation of SS and threshold voltage ($V_{\text {TH}}$) of T-TFT with O2 plasma after NBTI stress for 1000 s are suppressed from 0.779 to 0.319 V/decade and 1.28 to −0.82 V, respectively. The degradation of on-state current is also improved significantly from −87% to −40% when the T-TFT is passivated by the O2 plasma. Moreover, the T-TFT with O2 plasma exhibits less stress voltage-dependent electrical degradation of NBTI than it without O2 plasma. When the stress voltage of NBTI increases, two-step $V_{\text {TH}}$ shift behavior of T-TFT with O2 plasma is observed due to the competition of hole trapping effect and SS degradation effect. Furthermore, the T-TFT with O2 plasma shows less electrical degradation quantity than it without O2 plasma when the temperature of NBTI is increased from 25 °C to 75 °C. [ABSTRACT FROM AUTHOR]

The impacts of ammonia gas (NH3) plasma treatment on the performance and positive gate bias stress (PGBS) of polycrystalline-silicon (poly-Si) junctionless thin-film transistor (JL-TFT) are studied. A −0.785-V threshold voltage ($V_{\mathrm {TH}}$) shift of JL-TFT due to the NH3 plasma treatment is observed, which is attributed to the fixed oxide charge effect of the plasma-induced interfacial layer (PIL). In addition, the transconductance of JL-TFT with the NH3 plasma treatment is enhanced by ~2.73 times due to the trap state passivation of grain boundaries in the poly-Si, and the ON-state current ($I_{\mathrm {ON}}$) is enhanced by ~2.91 times. In addition to the performance enhancement of JL-TFT by the plasma process, the $V_{\mathrm {TH}}$ shift of poly-Si JL-TFT under PGBS is suppressed from −0.240 to −0.063 V after the plasma treatment. It is attributed to the less degradation of insulator/channel interface due to the growth of PIL by the plasma process. Moreover, the $I_{\mathrm {ON}}$ degradation of JL-TFT after PGBS is also improved from −19% to −16% after the plasma treatment. As the carrier transport of JL-TFT is the bulk conduction rather than the surface conduction of conventional inversion-mode TFT, the degradation of insulator/channel interface would exhibit less impacts on the $I_{\mathrm {ON}}$. The improvement of performance and PGBS of JL-TFT by the NH3 plasma treatment would be beneficial to the application of 3-D integrated circuits. [ABSTRACT FROM AUTHOR]

Hot-carrier stress (HCS) characteristics of polycrystalline-silicon (poly-Si) tunnel field-effect thin-film transistors are investigated and compared with the conventional poly-Si thin-film transistors (TFTs). After HCS with VDS = 2VGS = 20 V for 1000 s, poly-Si TFT exhibits significant ON-state current (Ion) degradation ~85% and two-step subthreshold swing (SS) behavior due to the serious lattice damage between the pinch-off point and the drain. For the poly-Si tunnel field-effect transistor (TFET), less Ion degradation ~70% is observed. In addition, the stress drain voltage (VDS) effect of the HCS is also studied. When the stress VDS is increased from 10 to 15 V, the poly-Si TFETs exhibit more obvious stressed Ion degradation (~24.4%) than that of poly-Si TFTs (~6.5%). When the stress VDS is further increased from 15 to 20 V, the poly-Si TFETs exhibit less stressed Ion degradation (~62.4%) than that of poly-Si TFTs (~85%). Because the increase in the stress drain voltage is dropped in the pinch-off region of the poly-Si TFETs after the pinch-off phenomenon occurs, resulting in less impact on the stress field at the tunnel junction. When the channel length is decreased, the results show that the HCS effect of poly-Si TFETs is insensitive to the channel length, and the poly-Si TFTs show more serious electrical degradation and breakdown behavior with the scaling down of the channel length. The stronger HCS immunity of poly-Si TFETs would be an important advantage to replacing poly-Si TFTs for applications of 3-D integrated circuits. [ABSTRACT FROM AUTHOR]

Performance improvement of polycrystalline-silicon (poly-Si) tunnel field-effect transistors (TFETs) by the channel thickness reduction is proposed and compared with conventional poly-Si thin-film transistors (TFTs). The thickness reduction of poly-Si film would have smaller grain size and higher trap state density, resulting in the driving current degradation ~33% of conventional poly-Si TFTs due to the degradation of field-effect mobility. However, the poly-Si TFETs with thinner poly-Si channel film exhibit better subthreshold swing from 0.545 V/decade to 0.365 V/decade and ~70% improvement of driving current when the channel film thickness is decreased from 100-nm to 50-nm. It indicates the enhancement of gate-to-junction control ability has stronger impacts than the effect of trap state density generation on the interband tunneling current of the poly-Si TFETs. Consequently, it is an easy way to improve the performance of poly-Si TFETs and can be easily combined with other performance improvement techniques of poly-Si TFETs. [ABSTRACT FROM AUTHOR]

The drain lapping effect of tunneling FETs (TFETs) with polycrystalline-silicon (poly-Si) channel film is well investigated for the first time. The carrier transport mechanisms of poly-Si TFETs can be divided into several transport mechanisms due to the device structure of source to drain. The interband tunneling at source/channel junction, carrier drift in the channel region, and drain-to-gate underlap region are elemental carrier transport mechanisms of TFETs with single-crystalline channel material. The poly-Si channel has many grain boundary trap states among bandgap due to the grain boundary defects, resulting in strong recombination effect in the drain-to-gate underlap region of poly-Si TFETs. The recombination rate of the underlap region would be significantly enhanced with the increased temperature and lead to obvious ON-state current ( I \mathrm{ ON} ) degradation. Therefore, the I \mathrm{ ON} behavior of the drain lapping effect is sensitive to the temperature and underlap length. In addition, the poly-Si TFETs with drain-to-gate overlap structure exhibit less temperature dependence and drain-to-gate overlap length dependence of the I \mathrm{ ON} to exhibit stable electrical behavior. Consequently, the drain lapping structure of poly-Si TFETs would trade the suppression of ambipolar behavior of poly-Si TFETs by the drain-to-gate underlap structure off against the I \mathrm{ ON} instability of temperature and device dimension. [ABSTRACT FROM AUTHOR]

In this paper, tunnel field-effect transistor (TFETs) with polycrystalline-silicon (poly-Si) channel film has been demonstrated to exhibit better short-channel effects (SCEs) immunity than conventional poly-Si thin-film transistors. Oxygen (O2) plasma surface treatment before the deposition of gate dielectric can produce a plasma-induced interfacial layer, which can passivate the interface trap state density ~25%. In addition, the ON-state transconductance Gm is improved ~54% due to the decrease of tunneling distance of band-to-band tunneling. However, the Gm improvement of poly-Si TFETs is decreased with the scaling down of channel length due to the less trap state density in the small area of poly-Si channel film. Moreover, the O2 plasma surface treatment can also reduce the grain boundary trap state density of poly-Si channel film ~37%, which can reduce the trap-assisted tunneling current of poly-Si TFETs to suppress the length dependence of drain leakage current in the subthreshold region. Consequently, the O2 plasma surface treatment can not only improve the ON-state current and OFF-state leakage current of poly-Si TFETs, but also further improve the SCEs of poly-Si TFETs. [ABSTRACT FROM PUBLISHER]

In this paper, positive-bias temperature instability (PBTI) stress with different stress voltage at T = 125~^\circ \textC is executed on the high-performance polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with HfO2 gate dielectric and ammonia (NH3) plasma surface treatment. The NH3 plasma surface treatment on the poly-Si TFT with HfO2 gate dielectric can significantly decrease the threshold voltage ( V\mathrm{ TH} ) approximately −1.86 V, reduce the subthreshold slope (S.S.) approximately −88 mV/decade, enhance the transconductance ( Gm ) approximately 2.4\times , and driving current ( I_{\mathrm{ drv}}) approximately 2.34. In addition, the device degradation after PBTI stress with stress voltage V_{G} - V_{\mathrm{ TH}} = 7 V for 1000 s at T = 125~^\circ \textC can also be improved after the NH3 plasma surface treatment, such as the suppressing of V\mathrm TH shift from 2.063 to 0.617 V, S.S. degradation quantity from 0.284 V/decade to 0.172 V/decade, and I\mathrm{ drv} reduction from −77% to −44%. The improvement of the PBTI of poly-Si TFTs with NH3 plasma surface treatment is attributed to the suppression of oxide charge trapping effect and the degradation of interface state density ( N\mathrm{ it} ) and grain boundary trap state density ( N\mathrm{ GB} ). [ABSTRACT FROM AUTHOR]

In this paper, low-temperature polycrystalline silicon (poly-Si) tunnel thin-film transistors (tunnel-TFTs) are demonstrated to show excellent short-channel effects immunity due to their special current transport mechanism: inter-band tunneling. The ammonia (NH 3 ) plasma surface treatment before the deposition of gate dielectric can significantly reduce the grain boundary trap state densities (N GB ) of poly-Si channel film and the interface trap state densities (N it ) at the gate-oxide/poly-Si interface. About 27% reduction of N GB by NH 3 plasma surface treatment can reduce the minimum drain current ~ 0.51 × and improve the subthreshold slope due to the suppression of trap-assisted tunneling, which dominates the current transport in the subthreshold operation region. In addition, about 37% reduction of N it by NH 3 plasma surface treatment can significantly enhance the on-state current ~ 2.86 × due to the increase of band bending of poly-Si channel potential, which can decrease the tunneling distance to increase the electron tunneling probability. Consequently, the performance improvement of poly-Si tunnel-TFTs by the NH 3 plasma surface treatment would be helpful for the development of system-on-panel and three-dimension integrated circuits. [ABSTRACT FROM AUTHOR]

In this brief, the tunnel FETs (TFETs) with a polycrystalline-Si (poly-Si) channel have been demonstrated, and the performance of the poly-Si TFET shows a significant improvement by the reduction of interface trap states ( N\mathrm {{it}} ) near the conduction band edge. The ON-state current ( I\mathrm{\scriptscriptstyle ON} ) conduction mechanism, band-to-band tunneling, of poly-Si TFETs is strongly affected by the band bending of poly-Si channel. The N2 plasma surface treatment before the gate dielectric deposition can produce a plasma-induced interfacial layer to reduce N\mathrm {it} obviously, which greatly enhances the surface potential modulation by the gate and improves the I\mathrm{\scriptscriptstyle ON} value of poly-Si TFETs \sim 3.7\times . The OFF-state current ( I_{\mathrm { {min}}} ) attributed to the trap-assisted tunneling (TAT) can also be reduced by a factor of \sim 40 %, because of the passivation of grain boundary trap ( N\mathrm {trap} ) of the poly-Si channel film. Consequently, the ON/OFF current ratio is enhanced from 9.42\times 10^{5} to 6.13\times 10^6 . In addition, the subthreshold swing, $I_{{\mathrm{\scriptscriptstyle ON}}}$ , and I_{\mathrm { {min}}} of poly-Si TFET exhibit superior short-channel effect immunity, which shows good feasibility for implementing high packing density of poly-Si thin-film transistors, such as 3-D nonvolatile memory and pixel driving device. [ABSTRACT FROM AUTHOR]

In this paper, the positive and negative bias temperature instability (P/NBTI) of complementary metal–oxide–semiconductor (CMOS) low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO 2 gate dielectric are studied simultaneously. Significant threshold voltage shift Δ V TH , degradation of the subthreshold swing S.S. and transconductance G m are observed for both n-type LTPS-TFTs after PBTI stress and p-type LTPS-TFTs after NBTI stress. Moreover, the G m degradation rate with the stress time of p-type devices during NBTI shows significantly different behavior from the PBTI of n-type devices. The PBTI of n-type device shows a saturation behavior of the G m degradation with various stress bias and temperature. Conversely, the NBTI of p-type device shows an enhanced G m degradation rate with the increase of stress time and stress temperature. In addition, the threshold voltage shift |Δ V TH | of PBTI does not obey the traditional empirical power law model, but the NBTI obeys it with higher time exponent. Consequently, the NBTI of the p-type device shows worse driving current I drv degradation than the PBTI of the n-type device mainly due to the different G m degradation behavior. [ABSTRACT FROM AUTHOR]

In this paper, NH3 plasma directly applied to the surface of poly-Si channel is studied for the development of high-performance low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) with HfO2 high- \kappa gate dielectric. The reduction of threshold voltage from 1.52 to 0.62 V, the decrease of subthreshold swing from 227 to 151 mV/decade, and the enhancement of field effect mobility \mu _{\mathrm {FE}} from 31 to 65 cm ^{\mathrm {\mathbf {2}}}$ /Vs are observed after NH3 plasma surface treatment. It can be attributed to the NH3 plasma surface treatment enabling defect passivation and plasma-induced interfacial layer (PIL) growth. To decouple the impacts of defect passivation and PIL growth, the device without PIL is also fabricated. This paper demonstrates the important impacts of NH3 plasma surface treatment on the improvement of electrical characteristics of LTPS-TFTs. [ABSTRACT FROM PUBLISHER]

In this paper, the opposite impacts of N2O plasma surface treatment on the n- and p-channel low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO2 gate dielectric are investigated. Significant performance improvement of n-channel LTPS-TFT by N2O plasma surface treatment is observed, including threshold voltage reduction \Delta V\mathrm {\mathbf {TH}}\sim -0.57 V, 1.55× higher transconductance G\mathit {m} , and 1.82× higher driving current I{\rm{drv}} . However, p-channel LTPS-TFT shows serious performance degradation after N2O plasma surface treatment, including threshold voltage increase \Delta V\mathrm {\mathbf {TH}}~\sim -0.99 V, transconductance G\mathit {m} reduction, and driving current I\mathrm {\mathbf {drv}} degradation. The difference of the two mechanisms of N2O plasma surface treatment, namely, plasma induced interfacial layer (PIL) growth effect and trap passivation effect on poly-Si, is elaborated by a process of the PIL removal after the PIL growth. As a result, the trap passivation effect benefits both n- and p-channel LTPS-TFTs. The PIL growth effect shows the opposite impacts on the n- and p-channel LTPS-TFTs, that benefits n-channel LTPS-TFT and degrades p-channel LTPS-TFT seriously. Therefore, the negative impacts of N2O plasma surface treatment on the p-channel LTPS-TFTs can be eliminated by a PIL removal step in the process. These results would be critical for the applications of system-on-panel and 3-D integrated circuit. [ABSTRACT FROM PUBLISHER]

In this paper, the channel-film-thickness effect of low-temperature polycrystalline-Si thin-film transistors (LTPS-TFTs) is investigated. Greater channel film thickness can provide a higher field-effect mobility \muFE, rising from 14.33 to 22.33 \cm^2/\break\V\cdot \s, as the channel film thickness increases from 55 to 120 nm, due to grain-size effect. In addition, varying the channel film thickness of LTPS-TFTs results in different junction leakage current due to the source/drain (S/D) junction area effect. Moreover, the S/D series resistance also significantly increases when the channel film thickness is reduced from 120 to 35 nm, leading to poor field-effect mobility \muFE and driving current. Consequently, the optimum channel film thickness for active-matrix liquid-crystal displays may be identified. [ABSTRACT FROM AUTHOR]

Abstract: The nickel-nanocrystals (Ni-NCs)-embedded silicon nitride acting as a trapping layer has been successfully demonstrated to manipulate the charging and discharging of electrons in a thin film transistor (TFT) for non-volatile memory (NVM) applications. Regarding device performance, with and without Ni-NCs in the stack and under a programming/erasing condition of +/−18V for 1s, a better threshold voltage shift of 3.2V can be reached compared to a shift of 2.0V for a stack without Ni-NCs. The shift is an index representing the value required to differentiate “0” or “1” states during operation. In this case, the diameter range and number density of Ni-NCs are 5–13nm and 5.3×1011 cm− 2, respectively. [Copyright &y& Elsevier]

In this paper, the asymmetric driving current Idrv modification of CMOS low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO{2} gate dielectric is demonstrated by the interfacial layer (IL) engineering of HfO{2}/poly-Si interface. P-channel LTPS-TFT has much higher Idrv\sim 0.789~mA than the n-channel LTPS-TFT \sim0.274~mA under the same overdrive gate voltage. This asymmetric Idrv is due to the characteristics of field effect mobility \muFE that p-channel LTPS-TFT has much higher hole \muFE\sim 80.16~cm^{{2}}/Vs than the electron \muFE\sim 38.26~cm^{{2}}/V~s of n-channel LTPS-TFT. The modification of HfO{2}/poly-Si interface by O{2} plasma can enhance the electron \muFE\sim {34\%} and reduce the hole \muFE\sim{22.4\%}, resulting in balanced Idrv of CMOS LTPS-TFTs that n-channel device shows Idrv\sim 0.553~mA and p-channel device shows Idrv\sim 0.590~mA. In addition, the phonon scattering would also be improved by the IL growth and recovered to initial condition after IL removal. Consequently, the IL engineering of CMOS LTPS-TFTs with HfO{2} gate dielectric would be a good candidate for the application of system-on-panel or 3-D integrated circuits. [ABSTRACT FROM AUTHOR]

• P-type tunnel transistors with different gate capacitance are demonstrated. • Tunnel transistors with HfZrO2 gate dielectric is studied. • Tunnel transistors show stronger gate capacitance effect than general transistors. In this work, the polycrystalline-silicon (poly-Si) tunnel field-effect thin-film transistors (TFETs) with TiN/HfZrO 2 gate stack materials are demonstrated to exhibit low threshold voltage ~ –1.218 V, subthreshold swing (SS) ~ 0.311 V/decade and channel length insensitive transfer characteristics. Conventional carrier transport mechanism of poly-Si thin-film transistors (TFTs) is the thermionic emission with scattering effect, which is deduced as the drift-diffusion transport model with additional trap state induced energy barrier height, resulting in the stronger channel length dependence effect. For the poly-Si TFETs, the carrier transport mechanism is the interband tunneling, including band-to-band tunneling and trap-assisted tunneling, which is less affected by the channel length. The different carrier transport mechanisms of poly-Si TFETs and TFTs would lead to different gate dielectric thickness effect. When the thickness of gate dielectric HfZrO 2 is reduced from 18 to 10 nm to increase the gate capacitance density, the SS and on-state current of poly-Si TFETs exhibit much higher improvement than them of poly-Si TFTs. It indicates that the high gate capacitance density is a key parameter for the development of poly-Si TFETs to replace the conventional poly-Si TFTs in three-dimensional integrated circuit applications. [ABSTRACT FROM AUTHOR]

• Drain-to-gate lapping structure effect of poly-Si TFET is studied. • A series resistance effect in drain-to-gate lapping region is observed. • Temperature dependent I ON effect of poly-Si TFET is suppressed. • Suppression of temperature instability of poly-Si TFET is obtained. Trap-assisted tunneling (TAT) mechanism dominates the subthreshold leakage current and ambipolar transport behavior of tunnel field-effect transistor (TFET) with polycrystalline-silicon (poly-Si) channel. The unwanted ambipolar transport behavior of poly-Si TFET can be suppressed by the employment of gate-to-drain underlap structure to increase the tunneling distance near the drain side when the TFET is operated at the negative gate voltage. The gate-to-drain underlap length of TFET would also exhibit series resistance effect and strong temperature effect on the on-state current (I ON). The strong temperature dependent series resistance effect and bandgap narrowing effect cause the poly-Si TFET to exhibit temperature instability of the on-state current. In order to improve the temperature instability of the on-state current, the ammonia plasma treatment has been performed to passivate the defects and reduce the trap state density of poly-Si film. The trap state density reduction of poly-Si can improve the field-effect mobility of transport carrier and reduce the series resistance effect, resulting in the reduction of the temperature dependence of I ON. Consequently, the improved temperature dependent I ON of poly-Si TFET can be obtained, and it is useful for the development of poly-Si thin-film transistor and its applications in the high resolution display industry and three-dimensional integrated-circuit. [ABSTRACT FROM AUTHOR]