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Digital Signage can be quickly updated, greatly enhancing functionality compared to traditional paper signs. Worries about climate change, carbon footprint, energy shortages and light pollution means Signage should be low power with low light pollution. In response, E Ink has developed Kaleido reflective ePaper outdoor displays with good color performance. On a spectrum between paper signs and other forms of full color electronic display Kaleido is much closer to paper signs in power use and lighting impact. Operating temperature range is ‐15°C to 65°C, removing the need for expensive, power hungry heating and cooling. [ABSTRACT FROM AUTHOR]

A low-power, low-voltage universal multi-mode Gm-C filter using a 180 nm TSMC technology node is presented in this paper. The proposed filter employs only three transconductance operational amplifiers (OTAs) operating in the sub-threshold region with a supply voltage of 0.5 V, resulting in a power consumption of 32 nW. Moreover, without additional active elements, the proposed circuit can operate various functional modes, such as voltage, current, transconductance, and trans-resistance. The filter's frequency, centered at 462 Hz, and a compact and low-power solution showing only 93.5 µVrms input-referred noise make the proposed filter highly suitable for bio-signal processing. [ABSTRACT FROM AUTHOR]

Researchers are currently emphasizing the development of memory design based on memristors as a solution to the challenges posed by MOSFET-based designs. In this paper, a memristor-based ternary content addressable memory (MTCAM) has been designed and analyzed that is both high-speed and energy-efficient, while also occupying minimal area. The proposed MTCAM cell has five transistors and four memristors (referred to as 5T4M). It comprises two operational units: the main unit responsible for WRITE and SEARCH functions, composed of three transistors and two memristors, and the data recall unit, which is activated when data restoration is needed. This research work has been simulated in HSPICE with a 32-word array, each containing 144-digit MTCAM cells, using PTM 32 nm 0.9 V strained Si technology. The results indicate a search time of 204.6 ps and a search energy of 0.521 fJ/digit/search for worst-case mismatches, all achieved with a 1.2 V supply voltage. Furthermore, the implemented 32 × 144 MTCAM array provides a voltage margin of 331.38 mV. The 5T4M MTCAM design occupies an estimated area of 1.4904 μm2, which is notably compact compared to existing designs. [ABSTRACT FROM AUTHOR]

Edge computing enables prompt responses in IoT environments, such as the operation of autonomous vehicles and unmanned aerial vehicles. However, with the increase in sensor nodes, the computational burden on the computing node also increases. Specifically, data filtering and reduction at application nodes add to the energy burden for battery-operated devices. In this paper, we propose a preprocessing system at the application node that requires low power consumption for data transmission reduction. Based on our simulations, we identify the minimum data size needed to preserve the signal. We first design the preprocessing system using a hardware description language to evaluate its performance. Then, we implement the open-library-based MCU system, including the proposed preprocessing IP, to assess its operation and overhead. Our implementation of the preprocessing system reduces data transmission by 50% with acceptable information loss. Additionally, the area and power consumption after the logic synthesis of the preprocessing IP within the entire MCU system are evaluated at only 3.6% and 13.1%, respectively. By performing preprocessing using the MCU and proposed IP, nearly 74.4% power reduction is achieved compared to using the existing MCU core. [ABSTRACT FROM AUTHOR]

In this paper, a new structure for a 1-bit full adder is proposed based on dynamic logic methodology, which utilises pass transistors. The clocking operation falls into two phases. The clocking operation consists of a pre-discharged cycle, during which pseudo capacitors are reset to zero when the clock signal is high, and an evaluation cycle, during which the circuit outputs the adder function when the clock signal is low. The circuit uses a combination of 12 pass-transistors to better implement the full adder logic function with the maximum of a NMOS threshold voltage drop. Moreover, the circuit has no direct connection to the power-supply node and so this can possibly save the power dissipation. Our new adder outperforms other 1-bit full adder structures in terms of power-delay factor, according to simulation results. [ABSTRACT FROM AUTHOR]

The Internet of Things (IoT) and blockchain are emerging technologies that have attracted attention in many industries, including healthcare, automotive, and supply chain. IoT networks and devices are typically low-powered and susceptible to cyber intrusions. However, blockchains hold considerable potential for securing low-power IoT networks. Blockchain networks provide security features such as encryption, decentralisation, time stamps, and ledger functions. The integration of blockchain and IoT technologies may address many of the security concerns. However, integrating blockchain with IoT raises several issues, including the security vulnerabilities and anomalies of blockchain-based IoT networks. In this paper, we report on our experiments using our blockchain test bed to demonstrate that blockchains on IoT platforms are vulnerable to DDoS attacks, which can also potentially lead to device hardware failures. We show that a number of anomalies are visible during either a DDoS attack or IoT device failure. In particular, the temperature of IoT hardware devices can exceed 90 °C during a DDoS attack, which could lead to hardware failure and potential fire hazards. We also found that the Block Transaction Rate (BTR) and network block loss percentage can increase due to corrupted hardware, with the BTR dropping to nearly zero blocks/sec and a block loss percentage of over 50 percent for all evaluated blockchains, and as high as 81.3 percent in one case. Our experiments demonstrate that anomalous temperature, latency, bandwidth, BTR, and network block loss percentage can potentially be used to identify DDoS attacks. [ABSTRACT FROM AUTHOR]

In this paper, the impact of the inductive peaking bandwidth enhancement technique on the input-referred noise performance of a 10 Gbps optical receiver, which includes the CMOS Regulated Cascode (RGC) Transimpedance Amplifier (TIA) is investigated and analyzed. By examining the noise equations in this paper, a novel low-noise design methodology, is introduced. Additionally, through the implementation of the structured g m / I D approach and by selecting the suitable transistor dimensions, the power consumption as well as the noise values are reduced, while the values of the obtained gain and bandwidth are increased. To verify the performance of the designed TIA, the circuit is simulated in HSPICE using 90 nm CMOS technology parameters. The simulation results show the obtained gain value of 55.45 dBΩ, a bandwidth of 7.51 GHz and an input referenced noise value of 15.7 pA/√Hz at the 1.2 V power supply, while the circuit consumes 0.75 mW of power. [ABSTRACT FROM AUTHOR]

Brain-inspired flexible neuromorphic devices are of great significance for next-generation high-efficiency wearable sensing and computing systems. In this paper, we propose a flexible organic electrochemical transistor using poly[(bithiophene)-alternate-(2,5-di(2-octyldodecyl)- 3,6-di(thienyl)-pyrrolyl pyrrolidone)] (DPPT-TT) as the organic semiconductor and poly(methyl methacrylate) (PMMA)/LiClO4 solid-state electrolyte as the gate dielectric layer. Under gate voltage modulation, an electric double layer (EDL) forms between the dielectric layer and the channel, allowing the device to operate at low voltages. Furthermore, by leveraging the double layer effect and electrochemical doping within the device, we successfully mimic various synaptic behaviors, including excitatory post-synaptic currents (EPSC), paired-pulse facilitation (PPF), high-pass filtering characteristics, transitions from short-term plasticity (STP) to long-term plasticity (LTP), and demonstrate its image recognition and storage capabilities in a 3 × 3 array. Importantly, the device's electrical performance remains stable even after bending, achieving ultra-low-power consumption of 2.08 fJ per synaptic event at −0.001 V. This research may contribute to the development of ultra-low-power neuromorphic computing, biomimetic robotics, and artificial intelligence. [ABSTRACT FROM AUTHOR]

Bluetooth Low Energy Mesh (BLE Mesh) enables Bluetooth flexibility and coverage by introducing Low-Power Nodes (LPNs) and enhanced networking protocol. It is also a commonly used communication method in sensor networks. In BLE Mesh, LPNs are periodically woken to exchange messages in a stop-and-wait way, where the tradeoff between energy and efficiency is a hard problem. Related works have reduced the energy consumption of LPNs mainly in the direction of changing the bearer layer, improving time synchronization and broadcast channel utilization. These algorithms improve communication efficiency; however, they cause energy loss, especially for the LPNs. In this paper, we propose a constrained flooding algorithm based on time series prediction and lightweight GBN (Go-Back-N). On the one hand, the wake-up cycle of the LPNs is determined by the time series prediction of the surrounding load. On the other, LPNs exchange messages through lightweight GBN, which improves the window and ACK mechanisms. Simulation results validate the effectiveness of the Time series Prediction and LlightWeight GBN (TP-LW) algorithm in energy consumption and throughput. Compared with the original algorithm of BLE Mesh, when fewer packets are transmitted, the throughput is increased by 214.71%, and the energy consumption is reduced by 65.14%. [ABSTRACT FROM AUTHOR]

Although CNN shows high performance in the image recognition field, it has great disadvantages. They are to take a long time to perform machine learning due to a lack of system resources, and to consume a lot of power due to the great volume of computation. A convolution layer is a key element of convolutional neural network processing. This paper presents a convolution layer hardware using processing elements with a low-power multiplier. The low-power multiplier reduces the switching activity by increasing the exchange rate between the multiplier and multiplicand. The proposed convolution layer hardware was implemented on the Intel DE1-SoC FPGA Board using Verilog-HDL. The performance was verified by comparing the exchange rate with the existing multipliers when performing multiplications to process convolutional operations for the MNIST image database. [ABSTRACT FROM AUTHOR]

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In this paper, we present an analysis of an operational trans-conductance amplifier (OTA) with two positive feedback. The direct current (DC) transfer function is obtained by analyzing the OTA using the drain current in the weak inversion region. The analysis results were verified through comparison with SPICE simulations, and the characteristics of the DC transfer function analysis for the OTA design are well matched with the simulation results. The designed OTA dissipates a low power of 41.4 nW, and features the slew rate is improved by 436% compared to a conventional OTA without two positive feedback. Additionally, a DC gain and a unity-gain bandwidth is improved by 36 dB and 6.7 times, respectively. The OTAs are designed for the 0.18 µm complementary metal-oxide-semiconductor (CMOS) process. [ABSTRACT FROM AUTHOR]

This paper presents a shock detection device for packages in the supply chain. The primary purpose is to identify package damage during storage, delivery, and handling. Additionally, products are likely to be damaged if dropped from a certain height, which sometimes does not appear on the package. By continuously measuring package vibrations and detecting shocks in the supply chain, consumers can gain an insight into the state of the product upon delivery. This paper presents the Smart Sticker implementation for ultra-low-power shock detection in the supply chain. The overall energy consumption must be kept as low as possible while continuously sensing the presence of shock to ensure that the Smart Sticker's battery lasts as long as possible. The Smart Sticker functions in three modes to meet the established constraints: low-power, active, and data transfer mode. While detecting the shock, the low-power mode uses the least amount of energy needed. If the shock exceeds the threshold, the Smart Sticker enters active mode, stores the detected g force value in memory, and then switches back to low-power mode. Finally, employing Near Field Communication (NFC) and energy harvesting, the data transfer mode allows the consumer to read the recorded data. The results show that the Smart Sticker for shock detection performs according to set requirements and successfully monitors and detects shock for packages in the supply chain. [ABSTRACT FROM AUTHOR]

Modern processors often face challenges when handling instructions that overwhelm the branch target buffer (BTB), leading to front-end bottlenecks. As the BTB's capacity increases, its prediction module can become slower and power-hungry. In this paper, we introduce a straightforward yet highly effective two-level prediction mechanism to mitigate the escalating power consumption in the BTB structure, achieved by reducing the number of accesses. Our approach incorporates two main elements: M-BTB and V-BTB. M-BTB encompasses the first-level prediction mechanism and a fully associative BTB, while V-BTB houses the second-level prediction mechanism and a set-associative BTB. To implement our prediction mechanism, we optimize the traditional two-level BTB structure. The first level employs the skew mechanism, and the second level dissects the tag bits to create the Partial tag. These two levels of prediction mechanism correspond to the bank/way prediction for the two-level BTB structure. Our experimental results show that the first-stage prediction mechanism reduces M-BTB accesses by 75%, while the second-stage prediction mechanism ensures that over 98% of addresses require just zero or one way of the V-BTB to achieve a hit result. Our proposed approach achieves a remarkable 86–97% reduction in power consumption, with a minimal impact on performance and an increase in overall area efficiency. [ABSTRACT FROM AUTHOR]

This paper proposes a novel analog front end to filter edges in captured images. The proposed architecture employs the Sobel algorithm and uses a 3 × 3 kernel to process the input images. We used 180 nm Semi-Conductor Laboratory (SCL) CMOS fabrication technology for implementation with a power supply of 1.8 V. The proposed design employs six analog differential pairs in each horizontal and vertical gradient unit. The inputs to the differential pairs are the active signals fed from the 3 × 3 kernel using the Sobel weight masks. We connected the differential datum pairs in cascade to estimate the gradient index in horizontal/vertical direction using the net difference current between the output terminals. The horizontal and vertical gradient units, viz., G H and G V , respectively, are configured based on the polarity of weights in respective Sobel masks. The gradient (G) of the processing pixel (PP) is estimated using the net difference current in the combined circuitry employing G H and G V cells. The key advantages of the proposed design are very low area realization, high accuracy, and low power dissipation. The efficacy of the proposed edge filter analog front end is estimated through simulations and analysis with two sets of test signals in the processing window. [ABSTRACT FROM AUTHOR]

High‐transmission, high contrast ratio and low‐power‐consumption amplified intrinsic fringe field (AIFF) multi‐domain vertical alignment (MVA) LCD's are developed for microdisplay for augmented reality, portable smart phones, GPS, tablet, and LC TV display applications. The AIFF MVA design eliminates all protrusions and ITO slits in TFT and CF.substrates, resulting in high transmission and high yield. The no‐pretilt fabrication process is low cost, does not require PI rubbing and special photoalignment process, and uses standard IC, LC, and PI materials. AIFF MVA is the only LCD mode without edge disclinations. It is compatible with the RGBW square pixel designs for low power consumption LCD applications. [ABSTRACT FROM AUTHOR]

The constant growth of social media, unconventional web technologies, mobile applications, and Internet of Things (IoT) devices create challenges for cloud data systems in order to support huge datasets and very high request rates. NoSQL databases, such as Cassandra and HBase, and relational SQL databases with replication, such as Citus/PostgreSQL, have been used to increase horizontal scalability and high availability of data store systems. In this paper, we evaluated three distributed databases on a low-power low-cost cluster of commodity Single-Board Computers (SBC): relational Citus/PostgreSQL and NoSQL databases Cassandra and HBase. The cluster has 15 Raspberry Pi 3 nodes with Docker Swarm orchestration tool for service deployment and ingress load balancing over SBCs. We believe that a low-cost SBC cluster can support cloud serving goals such as scale-out, elasticity, and high availability. Experimental results clearly demonstrated that there is a trade-off between performance and replication, which provides availability and partition tolerance. Besides, both properties are essential in the context of distributed systems with low-power boards. Cassandra attained better results with its consistency levels specified by the client. Both Citus and HBase enable consistency but it penalizes performance as the number of replicas increases. [ABSTRACT FROM AUTHOR]

This paper presents a single-ended 11T sub-threshold SRAM (SE11T) based on 10-nm FinFET technology. The performance of the proposed design is evaluated and compared with those of other state-of-the-art SRAMs namely 6T, 8T, DIRP10T, ST2, PPN10T, and FC11T at VDD = 0.3 V. The proposed design improves read stability by 2.08X/1.31X/1.03X compared to 6T/ST2/PPN10T due to the read-decoupling technique. Furthermore, it improves writability by 1.42X/2.85X/1.35X/1.28X compared to 6T/DIRP10T/ST2/PPN10T owing to feedback-cutting scheme. The use of write bitline free structure make the proposed SRAM consumes at least 2.79X lower dynamic power. The static power is reduced in the proposed SRAM by at least 1.09X. The reduction is because of the stacking of the transistors, the long path from power VDD to ground, and eliminated leakage in read path. The proposed SRAM works reliably even when exposed to extreme process variations. The proposed bitcell occupies a 1.46X/1.19X higher area than that of 6T/8T. The proposed design improves most of the design metrics and can be an efficient candidate for portable applications with budgeted power. [ABSTRACT FROM AUTHOR]

IoT and wearable medical devices frequently require ultra-low power solutions that can support long spells of inactivity. This study presents a buck converter to control power stages using a novel pulse frequency modulation (PFM) system that reduces switching losses for low-power systems. The modulation of high and low-frequencies was demonstrated, where the high-frequencies exhibited better energy transformation between the inductor and capacitor, and the low-frequencies could be adjusted for different current loads, to reduce switching losses. This circuit is optimized for light load applications. Using voltage control oscillation (VCO), the frequency range of 0.5 MHz – 2.0 MHz can be adjusted to influence conversion efficiency for different loads. The design was simulated and then fabricated using TSMC 0.18um process. The core size was about 1500 × 1000um that includes power MOS. Measurements result an average conversion efficiency of 91% under a load of 0.1 mA – 10 mA. This chip is suitable for battery-based IoT systems, or wearable medical devices. [ABSTRACT FROM AUTHOR]

Digital Image Processing has dominated Digital Signal Processing at the cost of more memory, resources, and high computational power. In image processing, filtering transformations and other operations need complex multiplications, and the multiplier is one of the most resources consuming elements. Recently, mitigating the multiplier complexity in the digital signal processing (DSP) algorithms sigma-delta modulation based general purpose and adaptive DSP algorithms are developed in MATLAB and compared with its counterpart multibit algorithms for functionality and area-performance-power in FPGA. The contemporary multiplier algorithms are also optimized to overcome the multiplier complexity challenge as computation becomes simple and fast. This paper extends the reported work by investigating the sigma-delta modulation approaches for developing a computationally efficient low-power image processing algorithm. The proposed model is designed, developed, and simulated in MATLAB. The simulation results are analyzed using SNR, MSE, and Peak SNR. The simulation results show that the proposed system can better mitigate the noise effect, making it robust for noisy environment. [ABSTRACT FROM AUTHOR]

Purpose: Full adder cells are building blocks of arithmetic circuits and affect the performance of the entire digital system. The purpose of this study is to provide a low-power and high-performance full adder cell. Design/methodology/approach: Approximate computing is a novel paradigm that is used to design low-power and high-performance circuits. In this paper, a novel 1-bit approximate full adder cell is presented using the combination of complementary metal-oxide-semiconductor, transmission gate and pass transistor logic styles. Findings: Simulation results confirm the superiority of the proposed design in terms of power consumption and power–delay product (PDP) criteria compared to state-of-the-art circuits. Also, the proposed full adder cell is applied in an 8-bit ripple carry adder to accomplish image processing applications including image blending, motion detection and edge detection. The results confirm that the proposed cell has premier compromise and outperforms its counterparts. Originality/value: The proposed cell consists of only 11 transistors and decreases the switching activity remarkably. Therefore, it is a low-power and low-PDP cell. [ABSTRACT FROM AUTHOR]

An artificial intelligence of things (AIoT) chip is a critical hardware component in edge devices that supports data acquisition and processing in the artificial intelligence (AI) era. In this paper, we introduce the architecture and circuit techniques for AIoT systems as well as the design challenges associated with them. To address the design challenges, we describe our design approaches to improve energy efficiency from the standpoints of system architecture, AI computing, and data acquisition circuits. Meanwhile, we present our most recent research progress and state-of-the-art AIoT chip demonstrations at a prestigious conference. Our design techniques improve power and energy efficiency by orders of magnitude on corresponding state of the arts (SOTA), allowing for an advanced AIoT chip design. [ABSTRACT FROM AUTHOR]

Wireless Body Area Network (WBAN) is a wireless network of short-range communication protocols for remote healthcare monitoring with the possibility of giving freedom of human body movements. Sensor nodes (motes) are usually located under the skin, implanted deep in the body, or ingested, as in the rare case of smart pills for medical and non-medical usage. Since the necessary connections of wearable and implantable devices are wireless, and the components use low batteries, processing and transferring the critical data can deplete the nodes' power. In most cases, it is impossible to exchange or re-power batteries. Holter monitoring, loop recorders, and wireless capsule endoscopy are some of the WBAN's applications for saving and transferring medical data. Wireless capsule endoscopy is the application for image transmission in WBANs, and the image compression in common is a specific segment of capsule endoscopy. Since the better compression of images increases the frame rate and typically improves the diagnosis process, selecting the compression algorithm should be relevant. The considerable scope of this comprehensive study pays attention to the various biomedical data compression approaches in WBANs. This paper focuses on power-efficient schemes of remote healthcare networks. In this survey article, the energy-based biomedical data compression approaches of WBANs and remote healthcare networks are accurately classified based on lossy, lossless, and hybrid techniques; later, a comprehensive comparison of each specific method's power consumption is presented. [ABSTRACT FROM AUTHOR]

Currently, static circuit power is becoming a major concern, dominating the total power consumption due to the scaling down of CMOS technology. The smaller sizes drastically affect the leakage current, which integrated circuit designers attempt to overcome this issue. Hence, several methods and technologies have been proposed to prevail this phenomenon. One of these methods is using memory structures in logic designs. A Hybrid MTJ/CMOS circuit is one of these promising techniques to design low-power nonvolatile circuits with power gating ability and low overhead for reconfigurable possibilities. In this paper, we have proposed a fully nonvolatile, low-power Full-Adder based on MTJs that uses the spin transfer torque method assisted by the spin hall effect. Simulation results of these designs by HSPICE show that they can work fast with low-power consumption compared to other state-of-the-art nonvolatile full-adders. [ABSTRACT FROM AUTHOR]

This paper presents a CNFET (Carbon Nano-tube FET) based MT (Multi-Threshold)-SRAM (Static Random Access Memory) design based on the leakage reduction mechanism. A multi-threshold logic is employed for reducing the leakage current during read/write operations. Here, the multi-threshold technique is used to insert the high threshold sleep control to the low threshold circuit. The insertion is performed in a serial manner. The high threshold transistors are very useful for deriving the low sub-threshold current. Meanwhile, the low threshold transistors are promising for improving the circuit performance. The high-low threshold transistor pairs are used to change the channel length by modifying the oxide thickness of the transistors. The overall implementation of the Multi-threshold-based SRAM cells are implemented with the help of CNFET in-order to avoid the short channel effect, mobility degradation which is occurred while considering the channel length below 32 nm in CMOS (Complementary Metal Oxide Semiconductor) devices. The paper clearly represents the performance improvement of the proposed SRAM cells with above-mentioned technologies. [ABSTRACT FROM AUTHOR]

The survival rate for sudden cardiac arrest (SCA) is low, and patients with long-term risks of SCA are not adequately alerted. Understanding SCA's characteristics will be key to developing preventive strategies. Many lives could be saved if SCA's early onset could be detected or predicted. Monitoring heart signals continuously is essential for diagnosing sporadic cardiac dysfunction. An electrocardiogram (ECG) can be used to continuously monitor heart function without having to go to the hospital. A zeolite-based dry electrode can provide safe on-skin ECG acquisition while the subject is out-of-hospital and facilitate long-term monitoring. To the ECG signal, a low-power 1 μW read-out circuit was designed and implemented in our prior work. However, having long-term ECG monitoring outside the hospital, i.e., high battery life, and low power consumption while transmission and reception of ECG signal are crucial. This paper proposes a prototype with a 10-bit resolution ADC and nRF24L01 transceivers placed 5 m apart. The system uses the 2.4 GHz worldwide ISM frequency band with GFSK modulation to wirelessly transmit digitized ECG bits at 250 kbps data rate to a physician's computer (or similar) for continuous monitoring of ECG signals; the power consumption is only 11.2 mW and 4.62 mW during transmission and reception, respectively, with a low bit error rate of ≤0.1%. Additionally, a subject-wise cross-validated, three-fold, optimized convolutional neural network (CNN) model using the Physionet-SCA dataset was implemented on NVIDIA Jetson to identify the irregular heartbeats yielding an accuracy of 89% with a run time of 5.31 s. Normal beat classification has an F1 score of 0.94 and a ROC score of 0.886. Thus, this paper integrates the ECG acquisition and processing unit with low-power wireless transmission and CNN model to detect irregular heartbeats. [ABSTRACT FROM AUTHOR]

There has been much interest in replacing traditional information supports with more technological solutions in recent years. New technologies which allow paper-like perception with minimal power needs have emerged as low-power wireless scenarios. A priority for these new supports is to create the architecture for a scalable solution which maintains minimal power requirements. The retail industry demands a new information infrastructure that improves customer and employee satisfaction. In this work, authors propose an information provision architecture based on E-Paper and carry out an experiment where different smart labeling architectures based on Paper, E-Paper, LED liquid crystal display (LCD) and Dot-matrix LCD were tested in order to determine which is best suited for a real labeling environment. Enclosed in a research project called SMARKET, the authors pilot-tested the work in a real supermarket, having the opportunity to survey employees and customers about satisfaction and frustration with the use of the architectures proposed in this research work. [ABSTRACT FROM AUTHOR]

With the emerging of Internet of Things (IoT) industry, applications like smart power plugs, security ID tags, home automation and wearable electronic devices all make the demand for low-power WiFi chips impendency. In this paper, a low-power 2.4 GHz 802.11b/g/n WiFi system-on-chip (SoC) is designed and implemented with 40-nm CMOS process, with area of 8.1 mm2. The low-power SoC integrates 32-bit microcontroller, 802.11b/g/n WiFi baseband, 2.4 GHz RF transceiver, ample memory space, ADC, 6-channel PWM, flexible I/O interfaces, multi-stage power management module, etc. It has several sleep modes with extremely low leakage current as 0.8 mA/12 µA in light/deep sleep mode and 0.4 µA in shutdown mode to reduce the power consumption. High performance is demonstrated, including Pout (−28 dB/-30 dB EVM) of 20.1 dBm/19.1 dBm and RX sensitivity of −76 dBm/-74 dBm meanwhile the total current of 148.5 mA/146.5 mA (TX) for 54 Mbps OFDM/HT20 MCS7. [ABSTRACT FROM AUTHOR]

This paper presents static and dynamic theoretical analysis of a new Operational Transconductance Amplifier (OTA) dedicated to low-voltage and low-power applications. High linearity is obtained using signal attenuation for rail-to-rail operation. Design, layout and post-layout simulations have been carried-out with Cadence Virtuoso in a 0.18µm CMOS technology. Post-Layout Simulation (PLS) demonstrates proper operation down to ± 0.75 V supply voltage with a high open loop small-signal voltage gain of 58.26dB, a unity gain frequency of 18MHz and a total harmonic distortion of -66.55dB at 100 kHz for a peak-to-peak input voltage of 0.8V. Based on this circuit, two applications have been successfully demonstrated: on the one side, a 5th order Butterworth G mC filter and, on the other side, a voltage mode instrumentation amplifier. [ABSTRACT FROM AUTHOR]

Portable applications and battery-operated devices require highly reliable, stable, and low-power nanometer-sized embedded cache static random access memory (SRAM) cells. The conventional 6-transistor (6 T) SRAM cell and its variants suffer from malfunctioning during the read/write operations, and instability, and are vulnerable to the multi-bit soft-error rate at scaled technology node and low supply voltage (VDD). In this regard, this paper proposes an 12 T SRAM cell with reliable functioning and reduced multi-bit soft-errors appropriate for low-power portable applications. This cell performs single-end bitline decoupled read operation and write data-dependent feedback-cutting-aware differential write operation to improve the read static noise margin (RSNM) and write static noise margin (WSNM), respectively. The presence of stack transistors in the cell core and read path, and also high virtual ground (VGND) minimize the leakage power dissipation. The proposed cell is compared with other state-of-the-art SRAM cells at VDD = 0.7 V and under harsh process, voltage, and temperature (PVT) variations. It offers at least 1.18X higher RSNM, 1.27X higher WSNM, and 2.02X lower leakage power dissipation. It also shows the second-best read power and incurs a penalty in write power. This cell shows at least 1.17X, 1.32X, and 1.04X smaller spread in read delay, RSNM, and WSNM, respectively, when subjected to PVT variations. In addition, the proposed cell eliminates the write half-select disturbance by employing a separate gate to drive the access transistors and thus column-interleaving structure and error correction coding can be applied to reduce multiple-bit upset and increase soft-error immunity. The soft-error in the proposed cell is reduced by at least 1.37X in critical charge. Generally, the proposed cell offers the best overall performance among all the compared cells by showing the highest proposed figure of merit. [ABSTRACT FROM AUTHOR]

Variable energy constraints affect the implementations of neural networks on battery-operated embedded systems. This paper describes a learning algorithm for randomization-based neural networks with hard-limit activation functions. The approach adopts a novel cost function that balances accuracy and network complexity during training. From an energy-specific perspective, the new learning strategy allows to adjust, dynamically and in real time, the number of operations during the network's forward phase. The proposed learning scheme leads to efficient predictors supported by digital architectures. The resulting digital architecture can switch to approximate computing at run time, in compliance with the available energy budget. Experiments on 10 real-world prediction testbeds confirmed the effectiveness of the learning scheme. Additional tests on limited-resource devices supported the implementation efficiency of the overall design approach. [ABSTRACT FROM AUTHOR]

This paper presents a sub-microwatt sub-bandgap voltage and current reference that can generate proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) currents concurrently. The voltage reference is derived from the process-insensitive silicon bandgap voltage of a bipolar junction transistor, whereas the current reference is made by combining PTAT and CTAT currents. Line regulation is improved by incorporating cascode devices without an operational amplifier (opamp). Fabricated in a standard 0.18-µm CMOS process, the proposed bandgap reference occupies an active area of 0.4 mm2. The current and voltage reference ( I REF and V REF ) are measured as 170 mV and 21 nA, respectively, while the start-up settling response is measured as 20 ms at room temperature. The average temperature coefficient of I REF and V REF is 79.8 ppm/°C and 87.93 ppm/°C across the temperature range from − 40 to 120 °C, respectively. The power consumption is 134 nW at the minimum supply voltage of 1.2 V. The power supply ripple rejection of V REF is measured as − 10 dB at 100 kHz without any filtering capacitor, when the 1.6 V input line voltage is distorted by a 300-mVp-p ripple. The measured line sensitivity of the voltage and current reference is 0.142%/V and 0.757%/V, respectively. [ABSTRACT FROM AUTHOR]

This article presents the design of a low-power low noise amplifier (LNA) implemented in 45 nm silicon-on-insulator (SOI) technology using the g m / I D methodology. The Ka-band LNA achieves a very low power consumption of only 1.98 mW andis the first time the g m / I D approach is applied at such a high frequency. The circuit is suitable for Ka-band applications with a central frequency of 28 GHz, as the circuit is intended to operate in the n257 frequency band defined by the 3GPP 5G new radio (NR) specification. The proposed cascode LNA uses the g m / I D methodology in an RF/MW scenario to exploit the advantages of moderate inversion region operation. The circuit occupies a total area of 1.23 mm2 excluding pads and draws 1.98 mW from a DC supply of 0.9 V. Post-layout simulation results reveal a total gain of 11.4 dB, a noise figure (NF) of 3.8 dB, and an input return loss (IRL) better than 12 dB. Compared to conventional circuits, this design obtains a remarkable figure of merit (FoM) as the LNA reports a gain and NF in line with other approaches with very low power consumption. [ABSTRACT FROM AUTHOR]

Implantable neuromodulation devices have significantly advanced treatments for neurological disorders such as Parkinson's disease, epilepsy, and depression. Traditional open-loop devices like deep brain stimulation (DBS) and spinal cord stimulators (SCS) often lead to overstimulation and lack adaptive precision, raising safety and side-effect concerns. Next-generation closed-loop systems offer real-time monitoring and on-device diagnostics for responsive stimulation, presenting a significant advancement for treating a range of brain diseases. However, the high false alarm rates of current closed-loop technologies limit their efficacy and increase energy consumption due to unnecessary stimulations. In this study, we introduce an artificial intelligence-integrated circuit co-design that targets these issues and using an online demonstration system for closedloop seizure prediction to showcase its effectiveness. Firstly, two neural network models are obtained with neural-network search and quantization strategies. A binary neural network is optimized for minimal computation with high sensitivity and a convolutional neural network with a false alarm rate as low as 0.1/h for false alarm rejection. Then, a dedicated low-power processor is fabricated in 55 nm technology to implement the two models. With reconfigurable design and event-driven processing feature the resulting application-specific integrated circuit (ASIC) occupies only 5mm2 silicon area and the average power consumption is 142 µW. The proposed solution achieves a significant reduction in both false alarm rates and power consumption when benchmarked against state-of-the-art counterparts. [ABSTRACT FROM AUTHOR]

Multiplication is a fundamental arithmetic operation in electronic processing units such as microprocessors and digital signal processors as it plays an important role in various computational tasks and applications. There exist many designs of synchronous multipliers in the literature. However, in the domain of Input–Output Mode (IOM) asynchronous design, there is relatively less published research on multipliers. Some existing works have considered quasi-delay-insensitive (QDI) asynchronous implementations of multipliers. However, the QDI asynchronous design paradigm, in general, is not area- and speed-efficient. This article presents an efficient alternative implementation of IOM asynchronous multipliers based on the concept of monotonic Boolean networks. The array multiplier architecture has been considered for demonstrating the usefulness of our proposition. The building blocks of the multiplier, such as the partial product generator, half adder, and full adder, were implemented monotonically. The popular dual-rail encoding scheme was considered for encoding the multiplier inputs and outputs, and four-phase return-to-zero handshaking (RZH) and return-to-one handshaking (ROH) were separately considered for communication. Compared to the best of the existing QDI asynchronous array multipliers, the proposed monotonic asynchronous array multiplier achieves the following reductions in design metrics: (i) a 40.1% (44.3%) reduction in cycle time (which is the asynchronous equivalent of synchronous clock timing), a 37.7% (37.7%) reduction in area, and a 4% (4.5%) reduction in power for 4 × 4 multiplication corresponding to RZH (ROH), and (ii) a 58.1% (60.2%) reduction in cycle time, a 45.2% (45.2%) reduction in area, and a 10.3% (11%) reduction in power for 8 × 8 multiplication corresponding to RZH (ROH). The multipliers were implemented using a 28 nm CMOS process technology. [ABSTRACT FROM AUTHOR]

Implantable microelectrodes arrays are used to record electrical signals from surrounding neurons and have led to incredible improvements in modern neuroscience research. Digital signals resulting from conditioning and the analog-to-digital conversion of neural spikes captured by microelectrodes arrays have to be elaborated in a dedicated DSP core devoted to a real-time spike-sorting process for the classification phase based on the source neurons from which they were emitted. On-chip spike-sorting is also essential to achieve enough data reduction to allow for wireless transmission within the power constraints imposed on implantable devices. The design of such integrated circuits must meet stringent constraints related to ultra-low power density and the minimum silicon area, as well as several application requirements. The aim of this work is to present real-time hardware architecture able to perform all the spike-sorting tasks on chip while satisfying the aforementioned stringent requirements related to this type of application. The proposed solution has been coded in VHDL language and simulated in the Cadence Xcelium tool to verify the functional behavior of the digital processing chain. Then, a synthesis and place and route flow has been carried out to implement the proposed architecture in both a 130 nm and a FD-SOI 28 nm CMOS process, with a 200 MHz clock frequency target. Post-layout simulations in the Cadence Xcelium tool confirmed the proper operation up to a 200 MHz clock frequency. The area occupation and power consumption of the proposed detection and clustering module are 0.2659 mm2/ch, 7.16 μW/ch, 0.0168 mm2/ch, and 0.47 μW/ch for the 130 nm and 28 nm implementation, respectively. [ABSTRACT FROM AUTHOR]

This paper proposes a modified Schmitt-trigger (ST)-based single-ended 11 T (MST11T) SRAM cell. The proposed cell is best suited to ultra-low voltage applications. Two ST-based cross-coupled inverters comprise the storage cell of the proposed MST11T bit cell. In comparison with conventional inverters, ST-based inverters have sharp voltage transfer characteristics. As a result, the proposed bit cell's stability performance increases. The proposed SRAM cell's leakage power consumption is reduced because of the use of stacked N-type transistors. For the read operation of the proposed bit cell, the read decoupled technique is used. As a result, the read static noise margin (RSNM) has greatly improved. The proposed bit cell's write static noise margin (WSNM) is increased by adopting feedback-cutting methodology. The performance of the proposed bit cell is compared with that of conventional 6 T, conventional 8 T, Schmitt-trigger 10 T (known as ST2), modified PMOS-PMOS-NMOS-based cell core 10 T (MPPN10T), feedback-cutting 11 T (FC11T), Schmitt-trigger 11 T (ST11), and Schmitt-trigger 12 T (ST12T) cells. According to the simulation results, the proposed MST11T SRAM cell has RSNM of 2.42, 1.18, 1.71, 1.30, and 1.80 times higher when compared to 6 T, FC11T, ST2, MPPN10T, and ST12T, respectively. The WSNM of the proposed bit cell has been increased by 1.56, 2.44, 1.28, 1.71, 1.35, 1.52, and 1.02 times, respectively, over 6 T, 8 T, ST2, MPPN10T, FC11T, ST11T, and ST12T. Furthermore, the suggested cell has a read delay that is 1.32, 1.79, and 1.53 times lower than ST11T, FC11T, and ST12T, respectively. The proposed bit cell has a write delay that is 1.14 and 1.63 times lower than FC11T and ST11T, respectively. The proposed MST11T bit-cell consumes 3.74, 1.56, 4.59, 5.38, and 4.83 times less leakage power than the 8 T, ST2, MPPN10T, FC11T, and ST12 bit-cells, respectively. When compared to 8 T/ST2/MPPN10T/ST12T at 0.2 V supply voltage, the enhanced facts incur a 4.87/3.79/3.78/1.97 penalty in write delay. The figure of merit (FOM) is derived as a result of this extensive access to the revolutionary SRAM cell performance, i.e., offering greater values at a 0.2 V DC supply voltage. In addition, the paper examines the impact of manufacturing process and temperature changes on MST11T cell enactment, as well as the circuit robustness using HSPICE with 7-nm FinFET technology. [ABSTRACT FROM AUTHOR]

In this paper, we analyze the performances of an Enhanced Static Segment Multiplier (ESSM) when the inputs have both uniform and non-uniform distribution. The enhanced segmentation divides the multiplicands into a lower, a middle, and an upper segment. While the middle segment is placed at the center of the inputs in other implementations, we seek the optimal position able to minimize the approximation error. To this aim, two design parameters are exploited: m, defining the size and the accuracy of the multiplier, and q, defining the position of the middle segment for further accuracy tuning. A hardware implementation is proposed for our generalized ESSM (gESSM), and an analytical model is described, able to find m and q which minimize the mean square approximation error. With uniform inputs, the error slightly improves by increasing q, whereas a large error decrease is observed by properly choosing q when the inputs are half-normal (with a NoEB up to 18.5 bits for a 16-bit multiplier). Implementation results in 28 nm CMOS technology are also satisfactory, with area and power reductions up to 71% and 83%. We report image and audio processing applications, showing that gESSM is a suitable candidate in applications with non-uniform inputs. [ABSTRACT FROM AUTHOR]

A low-noise and -power readout integrated circuit (IC) for two-electrode electrocardiogram (ECG) recording is developed in this study using a common-mode charge pump (CMCP) for a robust 20-VPP common-mode interference (CMI). Two-electrode ECG recording offers more comfort than three-electrode ECG recording. Contrasting to the three-electrode ECG recording, the two-electrode ECG recording is affected by CMI during measurements; the intervention of a large CMI will distort the ECG signal measurement. To achieve robustness for the CMI, the proposed ECG readout IC adopts CMCP—it uses switched capacitors that store and subtract CMI by control logic. In this paper, a window comparator structure is applied to CMCP to obtain a signal with less distortion. The window voltage ranges were set between the input common-mode ranges in which IA can operate. Therefore, a signal with less distortion was obtained by stopping the operation of CMCP between the window voltage ranges. It also reduced additional current consumption. To achieve this, the proposed circuit is implemented using a chopper stabilization technique. The chopper implemented in the amplifier can reduce low-frequency noise components, such as 1/f noise, and it comprises a CMCP, current feedback instrumentation amplifier, QRS peak detector, relaxation oscillator, voltage reference, timing generator, and serial peripheral interface on a single chip. The proposed circuit was designed using a standard 0.18 μm CMOS process with an active area of 0.54 mm2. The proposed CMCP achieves a CMI robustness of 20 VPP at 60 Hz. The measured input-referred noise level was 119 nV/√Hz at 1 Hz, and the power consumption was 23.83 μW with a 1.8 V power supply. [ABSTRACT FROM AUTHOR]

This paper presents the first implementation of a spiking neural network (SNN) for the extraction of cepstral coefficients in structural health monitoring (SHM) applications and demonstrates the possibilities of neuromorphic computing in this field. In this regard, we show that spiking neural networks can be effectively used to extract cepstral coefficients as features of vibration signals of structures in their operational conditions. We demonstrate that the neural cepstral coefficients extracted by the network can be successfully used for anomaly detection. To address the power efficiency of sensor nodes, related to both processing and transmission, affecting the applicability of the proposed approach, we implement the algorithm on specialised neuromorphic hardware (Intel ® Loihi architecture) and benchmark the results using numerical and experimental data of degradation in the form of stiffness change of a single degree of freedom system excited by Gaussian white noise. The work is expected to open a new direction of SHM applications towards non-Von Neumann computing through a neuromorphic approach. [ABSTRACT FROM AUTHOR]

This paper proposes a new discrete cosine transform (DCT) processor. The micro-rotation section of the architecture is based on a shared-resource improved coordinate rotation digital computer (CORDIC) unit, in an enhanced scalable DCT engine. To reduce the resources, and utilization area all micro-rotation operations have implemented as one united block in overlapped form. Using one processing element, the memory-based architecture has reduced the power consumption. Inputs and outputs of the processor are in-order which can be taken into account as an advantage for the proposed design. The processor has a low-complexity and distributed controller. Furthermore, due to the shared-resource implementation of CORDIC-II unit, by reduction of adding, shifting operations both in size, and number, the processor has high capabilities in short word lengths in comparison with state-of-the-art DCT processors. Compared to existing prominent DCT processors, the proposed processor achieves better results with limited hardware resources. [ABSTRACT FROM AUTHOR]

As the interest in the 4th industrial revolution and metaverse increases, metaverse with multi edge structure is proposed and noted. Metaverse is a structure that can create digital doctor-like system through a large amount of image processing and data transmission in a multi edge system. Since metaverse application requires calculating performance, which can reconstruct 3-D space, edge hardware’s insufficient calculating performance has been a problem. To provide streamable AI software in runtime, image processing, and data transmission, which is edge’s loads, needs to be lightweight. Also lightweight at the edge leads to power consumption reduction of the entire metaverse application system. In this paper, we propose collaborative edge-cloud image processing with remote image processing method and Region of Interest (ROI) to overcome edge’s power performance and build streamable and runtime executable AI software. The proposed structure was implemented using a PC and an embedded board, and the reduction of time, power, and network communications were verified. [ABSTRACT FROM AUTHOR]

A close correlation between CO2 concentration and aerosol enables the wide utilization of CO2 concentration as a good representation of Severe Acute Respiratory Syndrome-Coronavirus-2 infection airborne transmission. On the other side, many indoor air-quality monitoring devices have been developed for indoor monitoring applications. However, most of them are multiparameter air-quality sensor systems and tend to consume relatively high power, are relatively large devices, and are fairly expensive; therefore, they not meet the requirement for indoor monitoring applications. This paper presents a smart wireless sensor node that can measure and monitor CO2 concentration levels. The node was designed to meet the requirements of indoor air-quality monitoring applications by considering several factors, such as compact size, low cost, and low power, as well as providing real-time, continuous, reliable, and remote measurement. Furthermore, the commercial off-the-shelf and low-power consumption components are chosen to fit with the low-cost development and reduce energy consumption. Moreover, a low-power algorithm and cloud-based data logger also were applied to minimize the total power consumption. This power strategy was applied as a preliminary development toward an autonomous sensor node. The node has a compact size and consumes low energy for one cycle of CO2 measurement, accompanied by high accuracy with very low measurement error. The experiment result revealed the node could measure and monitor in real-time continuous, reliable, and remote CO2 concentration levels in indoor and outdoor environments. A user interface visualizes CO2 concentration graphically and numerically using the Adafruit platform for easy accessibility over the Internet of Things. The developed node is very promising and suitable for indoor CO2 monitoring applications with the acquired data that could be utilized as an indicator to minimize the risk of indoor Severe Acute Respiratory Syndrome-Coronavirus-2 airborne transmission. [ABSTRACT FROM AUTHOR]

Static random-access memories (SRAMs), which are the most ubiquitous in modern system-on-chips, suffer from high power dissipation and poor stability in advanced complementary metal–oxide–semiconductor (CMOS) technology due to continuous learning, which leads to increased short-channel effects (SCEs), thereby, leading to use of new nano-devices. The fin-shaped field-effect transistor (FinFET) with lots of impressive attributes like mitigated SCEs is an efficient replacement for CMOS to overcome the aforementioned concerns. In this regard, this paper aims to explore a novel single-bitline 9-transistor (SB9T) SRAM with bit-interleaving capability appropriate for low-power near-threshold operation in 7-nm FinFET technology. The relative performance of the proposed SB9T is estimated by comparing it with other seven contemporary SRAMs such as conventional 6 T, write–read enhanced 8T (WRE8T), transmission gate read decoupled 9T (TGRD9T), one-sided Schmitt-trigger 9T (ST9T), data-independent read port 10T (DIRP10T), PMOS-PMOS-NMOS-based cell core 10T (PPN10T), and feedback-cutting 11 T (FC11T) at a near-threshold supply voltage of 0.5 V. Simulation results inferred that the SB9T offers 1.77 × /1.36 × and 2.35 × /13.13 × /1.30 × improvement in read stability and writability compared to WRE8T/ST9T and 6 T/DIRP10T/PPN10T, respectively. Furthermore, it consumes the best dynamic read power, which is at least 1.50 × , the third-best dynamic write power, and the second-best static power. The proposed SB9T SRAM offers 2.89 × /2.37 × improvement in dynamic write power/static power, at the expense of 1.742 × area overhead, compared to 6 T. [ABSTRACT FROM AUTHOR]

This paper presents a PAM and PWM combined Mini‐LED pixel circuit based on oxide TFTs. In the PAM part, a constant current (1mA) allows Mini‐LEDs work at peak efficiency and reduce power consumption. A source follower structure compensates for ΔVTH and VSS IR rise, which has only one TFT on current path, so that the pixel circuit works at low voltage. In the PWM part, a diode connected structure compensates for ΔVTH. Simulation results show that the current error rate is less than 0.81% when ΔVTH of PAM part is within ±3 V. When VSS rises less than 3 V, the current error rate is less than 7.22%. When ΔVTH of PWM part is +3 V, emission time variation is reduced by 99.29% compared with the circuit without compensation. The supply‐voltage can be reduced from 19.7 V to 15 V thanks to the proposed Mini‐LED pixel circuit. [ABSTRACT FROM AUTHOR]

This paper investigates the use of approximate fixed-width and static segment multipliers in the design of Delayed Least Mean Square (DLMS) adaptive filters based on the sign–magnitude representation for the error signal. The fixed-width approximation discards part of the partial product matrix and introduces a compensation function for minimizing the approximation error, whereas the static segmented multipliers reduce the bit-width of the multiplicands at runtime. The use of sign–magnitude representation for the error signal reduces the switching activity in the filter learning section, minimizing power dissipation. Simulation results reveal that, by properly sizing the two approaches, a steady state mean square error practically unchanged with respect to the exact DLMS can be achieved. The hardware syntheses in a 28 nm CMOS technology reveal that the static segmented multipliers perform better in the learning section of the filter and are the most efficient approach to reduce area occupation, while the fixed-width multipliers offer the best performances in the finite impulse response section and provide the lowest power dissipation. The investigated adaptive filters overcome the state-of-the-art, exhibiting an area and power reduction with respect to the standard implementation up to −18.0% and −64.1%, respectively, while preserving the learning capabilities. [ABSTRACT FROM AUTHOR]

One of the most significant agricultural tasks in beekeeping involves continually observing the conditions inside and outside the beehive. This is mainly performed for the early detection of some harmful events. There have been many studies on how to detect and prevent such occurrences by performing periodic interventions or, when the frequency of such actions is hard to enforce, by using sensory systems that record the temperature, humidity, and weight of the beehive. Nevertheless, such methods are inaccurate, and their delivered outcomes usually diverge from the actual event or false trigger and introduce more effort and damage. In this paper, the authors propose a new low-cost, low-power system called Bee Sound Detector (BeeSD). BeeSD is a low-cost, embedded solution for beehive quality control. It incorporates the sensors mentioned above as well as real-time sound monitoring. With the combination of temperature, humidity, and sound sensors, the BeeSD can spot Colony Collapse Disorder events due to famine and extreme weather events, queen loss, and swarming. Furthermore, as a system, the BeeSD uses cloud logging and an appropriate mobile phone application to push notifications of extreme measurements to the farmers. Based on achieved performance indicators, the authors present their BeeSD IoT device and system operation, focusing on its advantages of low-cost, low-power, and easy-to-install characteristics. [ABSTRACT FROM AUTHOR]

This paper presents a robust low‐power 10T SRAM cell (RLP10T) with a novel read/write assist mechanism, improving both read static noise margin (RSNM) and write static noise margin (WSNM) simultaneously. To assess its relative strength, we compared the proposed cell with recently published SRAM cells such as WRE8T, 10T‐P1, HFBS10T, WALP11T, and SE11T in 16‐nm CMOS technology node. The RLP10T cell shows 3.55/1.07 times higher/lower RSNM compared to the WRE8T/WALP11T cell and offers at least 1.10 times higher WSNM. Due to the presence of three series‐connected transistors in its read path, which includes a strong pull‐down transistor, the proposed design shows 1.23 times shorter read delay (TRA) than that of 10T‐P1/HFBS10T cell. The proposed cell incurs a penalty of high write delay (TWA) due to its long write path. However, it exhibits the fourth (second)‐best read (write) power, attributed to its single‐ended structure and lower read (write) frequency. It also dissipates acceptable leakage power due to its single‐bitline structure and the presence of stacked transistors in its read path and pull‐down path of one of the inverters in the cell core. Subjected to the severe process, voltage, and temperature variations, the RLP10T cell offers at least 1.31/1.09/1.03 times lower variability in RSNM/WSNM/TRA at VDD = 0.7 V, at the cost of 1.22 times area overhead compared to the WRE8T cell. [ABSTRACT FROM AUTHOR]

This paper investigates a novel highly stable and robust single-ended 10T SRAM cell appropriate for low-power portable applications. The cell core of the proposed design is a combination of a normal inverter with a stacked NMOS transistor and a Schmitt-trigger (ST) inverter with a double-length pull-up transistor. This improves hold stability and leakage power dissipation. The read and write operations of the proposed cell are performed with the aid of separated paths and bitlines, lowering power consumption. The strong cell core and decoupled read path eliminate the read-disturbance issue in the proposed cell, resulting in read static noise margin (RSNM) enhancement. Furthermore, the feedback-cutting write-assist technique used in the proposed design mitigates the writing '1' issue; consequently, write static noise margin (WSNM)/write margin (WM) improves. To prove the superiority of the proposed SRAM cell in various performance metrics, it is compared with state-of-the-art SRAM cells, introduced as 6T, TG9T, 10T-P1, and SB11T, using HSPICE and 16-nm CMOS technology node taking into consideration the impact of the severe process, voltage, and temperature (PVT) variations. Obtained results at VDD = 0.7 V show that the proposed design offers the highest HSNM/RSNM/WSNM (or WM). The read/write delay of the proposed cell is 3.92X/2.37X higher than that of the 6T SRAM cell due to its single-ended reading/writing structure. However, in terms of power consumption, the proposed cell exhibits 1.64X/1.54X lower than that of 6T SRAM cell. Though the proposed cell occupies a 1.24X higher area compared with the 6T SRAM cell due to its higher count of transistor, it shows the highest proposed figure of merit among all the studied SRAM cells, which is 26.90X higher than that of 6T SRAM cell. [ABSTRACT FROM AUTHOR]