Search

Chemical reaction networks can be utilised as basic components for nucleic acid feedback control systems' design for Synthetic Biology application. DNA hybridisation and programmed strand-displacement reactions are effective primitives for implementation. However, the experimental validation and scale-up of nucleic acid control systems are still considerably falling behind their theoretical designs. To aid with the progress heading into experimental implementations, we provide here chemical reaction networks that represent two fundamental classes of linear controllers: integral and static negative state feedback. We reduced the complexity of the networks by finding designs with fewer reactions and chemical species, to take account of the limits of current experimental capabilities and mitigate issues pertaining to crosstalk and leakage, along with toehold sequence design. The supplied control circuits are quintessential candidates for the first experimental validations of nucleic acid controllers, since they have a number of parameters, species, and reactions small enough for viable experimentation with current technical capabilities, but still represent challenging feedback control systems. They are also well suited to further theoretical analysis to verify results on the stability, performance, and robustness of this important new class of control systems. [ABSTRACT FROM AUTHOR]

In order to achieve the full potential of the Internet-of-Things, connectivity between devices should be ubiquitous and efficient. Wireless mesh networks are a critical component to achieve this ubiquitous connectivity for a wide range of services, and are composed of terminal devices (i.e., nodes), such as sensors of various types, and wall powered gateway devices, which provide further internet connectivity (e.g., via Wi-Fi). When considering large indoor areas, such as hospitals or industrial scenarios, the mesh must cover a large area, which introduces concerns regarding range and the number of gateways needed and respective wall cabling infrastructure, including data and power. Solutions for mesh networks implemented over different wireless protocols exist, like the recent Bluetooth Low Energy (BLE) 5.1. While BLE provides lower power consumption, some wall-power infrastructure may still be required. Alternatively, if some nodes are battery powered, concerns such as lifetime and packet delivery are introduced. We evaluate a scenario where the intermediate nodes of the mesh are battery powered, using a BLE relay of our own design, which acts as a range extender by forwarding packets from end-nodes to gateways. We present the relay’s design and experimentally determine the packet forwarding efficiency for several scenarios and configurations. In the best case, up to 35% of the packets transmitted by 11 end-nodes can be forwarded to a gateway by a single relay under continuous operation. A battery lifetime of 1 year can be achieved with a relay duty cycle of 20%. [ABSTRACT FROM AUTHOR]

As applications move to the edge, efficiency in computing power and power/energy consumption is required. Heterogeneous computing promises to meet these requirements through application-specific hardware accelerators. Runtime adaptivity might be of paramount importance to realize the potential of hardware specialization, but further study is required on workload retargeting and offloading to reconfigurable hardware. This article presents our framework for the exploration of both offloading and hardware generation techniques. The framework is currently able to process instruction sequences from MicroBlaze, ARMv8, and riscv32imaf binaries, and to represent them as Control and Dataflow Graphs for transformation to implementations of hardware modules. We illustrate the framework's capabilities for identifying binary sequences for hardware translation with a set of 13 benchmarks. [ABSTRACT FROM AUTHOR]

The breakdown of Dennard scaling has resulted in a decade-long stall of the maximum operating clock frequencies of processors. To mitigate this issue, computing shifted to multi-core devices. This introduced the need for programming flows and tools that facilitate the expression of workload parallelism at high abstraction levels. However, not all workloads are easily parallelizable, and the minor improvements to processor cores have not significantly increased single-threaded performance. Simultaneously, Instruction Level Parallelism in applications is considerably underexplored. This article reviews notable approaches that focus on exploiting this potential parallelism via automatic generation of specialized hardware from binary code. Although research on this topic spans over more than 20 years, automatic acceleration of software via translation to hardware has gained new importance with the recent trend toward reconfigurable heterogeneous platforms. We characterize this kind of binary acceleration approach and the accelerator architectures on which it relies. We summarize notable state-of-the-art approaches individually and present a taxonomy and comparison. Performance gains from 2.6× to 5.6× are reported, mostly considering bare-metal embedded applications, along with power consumption reductions between 1.3× and 3.9×. We believe the methodologies and results achievable by automatic hardware generation approaches are promising in the context of emergent reconfigurable devices. [ABSTRACT FROM AUTHOR]

Summary: This paper presents an automatic procedure for the design and optimization of switched‐capacitor (SC) filters, including the automatic sizing of transistors in the amplifiers and switches. The optimization procedure is based on genetic algorithms (GAs) where the circuit's fitness is first computed using equations describing the filter's transfer function and then using transient simulations. These equations are obtained using a fast numerical methodology that takes into consideration the electrical behavior of all components in the circuit. The poles and zeros of the SC filter's transfer function are computed using a system of differential equations, obtained from the inspection of the circuit. This system describes the filter's behavior for all switch combinations, including the non‐ideal effects of the transistors in the switches and amplifiers. Due to the low computational effort and accuracy of this methodology, it is possible to use a large population in the GA. After finding a solution through equations, the more computationally intensive SPICE transient simulations are used to fine‐tune the solution, with a much smaller population in the GA. Taking advantage of the equations' low computational load and accuracy, process, voltage, temperature (PVT) corners and mismatch errors optimizations are also performed, allowing the chromosomes fitness to be calculated taking into consideration multiple cases, thus resulting in a low sensitivity design. [ABSTRACT FROM AUTHOR]

Summary: This paper presents an overview of design techniques to reduce the capacitance spread of SC notch filters. Three of these techniques are used in the design of a 50‐Hz notch filter, intended for an internet of things (IoT) water management sensor node. In this application, due to the high sampling frequency required by the acquisition channel's ADC, the filter's Fs/fp ratio becomes excessively large, resulting in a capacitance spread of 3225.8, if a conventional SC implementation is used. Using charge division networks, with up to seven share/reset cycles, the filter's capacitance spread is reduced by a factor 12.9 and the total capacitance by 5.9, and a total power dissipation of approximately 262 μW, for a supply voltage of 0.9 V. Using capacitive T‐cell networks, the filter's capacitance spread is reduced by a factor 40.5 and the total capacitance by 14.2. Using partial charge transfer networks, the filter's capacitance spread is improved by a factor 41.6, and the total capacitance by 10.0. The filter's total power consumption, using the last two techniques, is approximately 11 μW. [ABSTRACT FROM AUTHOR]

This brief presents an analog front-end (AFE) specially developed for a water conductivity measurement system for water network management applications. Water conductivity is one of the best ways to detect a problem with the water in the network. In order to trigger an alarm it is only required to detect a 10% variation, which allows to simplify the system design. The proposed sensor uses four platinum micro-machined electrodes, where a 6 kHz signal is applied to the outer electrodes and a voltage signal is read in the inner ones. A programmable switched-capacitor (SC) bandpass filter is included in the analog-to-digital (A/D) channel to attenuate the interference from the 50 Hz power network, that shares the same environment with the water network, and to allow using a square wave signal to drive the sensor, thus simplifying the overall system. The resulting sine wave is digitized using a passive continuous-time (CT) 2nd order $\Delta\Sigma$ modulator. The output bitstream is decimated, using a sinc filter, and the RMS value of the voltage is calculated. The A/D acquisition channel was implemented in a 130 nm CMOS technology, using a supply voltage of 0.9 V and a clock frequency of 1 MHz (SC amplifier and SC bandpass filter) and 4 MHz ($\Delta \Sigma $ modulator). Measurement results show a SNDR of 44.4 dB for an input signal of 6 kHz and an amplitude of −41 dBV. The channel dissipates 386 $\mu \text{W}$ and occupies an area of 0.27 mm2. [ABSTRACT FROM AUTHOR]

The use of specialized accelerator circuits is a feasible solution to address performance and energy issues in embedded systems. This paper extends a previous field-programmable gate array-based approach that automatically generates pipelined customized loop accelerators (CLAs) from runtime instruction traces. Despite efficient acceleration, the approach suffered from high area and resource requirements when offloading a large number of kernels from the target application. This paper addresses this by enhancing the CLA with dynamic partial reconfiguration (DPR) support. Each kernel to accelerate is implemented as a variant of a reconfigurable area of the CLA which hosts all functional units and configuration memory. Evaluation of the proposed system is performed on a Virtex-7 device. We show, for a set of 21 kernels, that when comparing two CLAs capable of accelerating the same subset of kernels, the one which benefits from DPR can be up to $4.3\times $ smaller. Resorting to DPR allows for the implementation of CLAs which support numerous kernels without a significant decrease in operating frequency and does not affect the initiation intervals at which kernels are scheduled. Finally, the area required by a CLA instance can be further reduced by increasing the IIs of the scheduled kernels. [ABSTRACT FROM AUTHOR]

In recent years, switched capacitor (SC) DC–DC converters have been gaining interest as an attractive solution for implementing power management solutions in small scale low power systems, such as Internet of Things remote sensor nodes. Since switch capacitor circuits can be fully integrated in bulk CMOS technology, the number of external components is reduced, thus decreasing both the production costs and the volume of the system. This brief presents a power management unit using a multi-ratio SC DC–DC converter, and its controlling circuits, designed in a 130 nm bulk CMOS technology occupying an area of 0.138 mm2. It provides a constant supply voltage of 0.9 V for a maximum output power of 1 mW, from an input supercapacitor voltage ranging from 1.2 to 2.3 V. The measured results show a conversion efficiency peak of 80.4%. [ABSTRACT FROM AUTHOR]

This brief presents a programmable second-order bandpass switched-capacitor filter implemented for an Internet-of-Things water management sensor node. The filter circuit, which is based on the Sallen-Key topology, is implemented using a low-gain amplifier (<2), avoiding designing high-gain high-bandwidth opamps, which can be difficult to design in advanced CMOS technologies, due to the reduction of the supply voltage and of the intrinsic gain of the transistors. Without the high gain, the circuit becomes sensitive to the effects of parasitic capacitances, which have to be minimized and compensated during the design process. The filter circuit was designed and fabricated in a 130-nm CMOS technology, using a supply voltage of only 0.9 V, to reduce the power dissipation, and a clock frequency of 1 MHz. Measurement results show that the filter’s central frequency can be tuned between 3.9 kHz and 7.1 kHz, the gain between −6.4 dB and 12.6 dB, and the quality factor between 0.9 and 6.9. In the default digital control code of the capacitor banks, the circuit has an IM3 of −66.5 dB. The total power consumption is 257 ${\boldsymbol \mu }\text{W}$. [ABSTRACT FROM AUTHOR]

The two projects presented in this paper can be used either as two separate assignments in two different semesters or as a final assignment for undergraduate students of electrical engineering. They have two main objectives: first, to teach basic electronic circuit design concepts and, second, to motivate the students to learn more about analog circuit design. The two projects are: 1) the design of an audio power amplifier, and 2) the design of an amplitude-modulated optical link with a pulsed light-emitting diode (LED) at the emitter and a photodiode and a transimpedance amplifier at the receiver. An audio signal is used to modulate the oscillator that drives the LED, and the receiver demodulates this signal to produce an audio signal (music, for example) that can be sent to a loudspeaker. The intent of this optical communication system was to allow students to design and build various electronic circuits that have an overall objective and a clear practical application. Students are motivated by using this system to transmit, receive, and listen to their own music. [ABSTRACT FROM PUBLISHER]

Many embedded applications process large amounts of data using regular computational kernels, amenable to acceleration by specialized hardware coprocessors. To reduce the significant design effort, the dedicated hardware may be automatically generated, usually starting from the application’s source or binary code. This paper presents a moduloscheduled loop accelerator capable of executing multiple loops and a supporting toolchain. A generation/scheduling procedure, which fully relies on MicroBlaze instruction traces, produces accelerator instances, customized in terms of functional units and interconnections. The accelerators support integer and single-precision floating-point arithmetic, and exploit instruction-level parallelism, loop pipelining, and memory access parallelism via two read/write ports. A complete implementation of the proposed architecture is evaluated in a Virtex-7 device. Augmenting a MicroBlaze processor with a tailored accelerator achieves a geometric mean speedup, over software-only execution, of 6.61 $\times $ for 13 floating-point kernels from the Livermore Loops set, and of 4.08 $\times $ for 11 integer kernels from Texas Instruments’ IMGLIB. The proposed customized accelerators are compared with ALU-based ones. The average specialized accelerator requires only 0.47 $\times $ the number of field-programmable gate array slices of an accelerator with four ALUs. A geometric mean speedup of 1.78 $\times $ over a four-issue very long instruction word (without floating-point support) was obtained for the integer kernels. [ABSTRACT FROM AUTHOR]

An energy-harvesting system requires an energy-storing device to store the energy retrieved from the surrounding environment. Rechargeable batteries are commonly used to store this energy; however, because of the limited number of charge/discharge cycles, they need to be periodically replaced. A supercapacitor, which has, ideally, a limitless number of charge/discharge cycles, avoids this problem. In this case, it is required for the power management unit to produce a constant output voltage as the supercapacitor discharges. This paper presents a system with a multiratio switched capacitor DC-DC converter, in a 130-nm technology, with a maximum output power of 2 mW, a maximum efficiency of 79.63% and a maximum output ripple, in the steady state, of 23 mV for an input voltage range of 2.3-0.87 V. The proposed converter has four operation states, to maximize its efficiency, that correspond to the conversion ratios of 1/2, 2/3, 1/1 and 3/2. Its clock frequency is automatically adjusted to produce a stable output voltage of 1 V. These features are implemented through two distinct controller circuits that use two asynchronous time machines to dynamically adjust the clock frequency and to select the active state of the converter. All the theoretical expressions as well as the behaviour of the whole system were verified by using electrical simulations. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]