Search

Enabling extreme ultraviolet lithography (EUVL) as a viable and efficient sub-10 nm patterning tool requires addressing the critical issue of reducing line edge roughness (LER). Stochastic effects from random and local variability in photon distribution and photochemical reactions have been considered the primary cause of LER. However, polymer chain conformation has recently attracted attention as an additional factor influencing LER, necessitating detailed computational studies with explicit chain representation and photon distribution to overcome the existing approach based on continuum models and random variables. We developed a coarse-grained molecular simulation model for an EUV patterning process to investigate the effect of chain conformation variation and stochastic effects via photon shot noise and acid diffusion on the roughness of the pattern. Our molecular simulation demonstrated that final LER is most sensitive to the variation in photon distributions, while material distributions and acid diffusion rate also impact LER; thus, the intrinsic limit of LER is expected even at extremely suppressed stochastic effects. Furthermore, we proposed and tested a novel approach to improve the roughness by controlling the initial polymer chain orientation.

Line-edge-roughness (LER) is one of undesirable process-induced random variation sources. LER is mostly occurred in the process of photo-lithography and etching, and it provokes random variation in performance of transistors such as metal oxide semiconductor field effect transistor (MOSFET), fin-shaped field effect transistor (FinFET), and gate-all-around field effect transistor (GAAFET). LER was analyzed/characterized with technology computer-aided design (TCAD), but it is fundamentally very time consuming. To tackle this issue, machine learning (ML)-based method is proposed in this work. LER parameters (i.e., amplitude, and correlation length X, Y) are provided as inputs. Then, artificial neural network (ANN) predicts 7-parameters [i.e., off-state leakage current (Ioff), saturation drain current (Idsat), linear drain current (Idlin), low drain current (Idlo), high drain current (Idhi), saturation threshold voltage (Vtsat), and linear threshold voltage (Vtlin)] which are usually used to evaluate the performance of FinFET. First, how datasets for training process of ANN were generated is explained. Next, the evaluation method for probabilistic problem is introduced. Finally, the architecture of ANN, training process and our new proposition is presented. It turned out that the prediction results (i.e., non-Gaussian distribution of device performance metrics) obtained from the ANN were very similar to that from TCAD in the respect of both qualitative and quantitative comparison.

The line-edge roughness (LER) is a critical issue that significantly impacts the critical dimension (CD) because the LER does not scale with the feature size. Hence, the LER influences the device performance with 7-nm and 5-nm patterns. In this study, LER impact on the performance of the fin-field-effect-transistors (FinFETs) are investigated using a compact device method. The fin-width roughness (FWR) is based on the stochastic fluctuation such as the LER and the line-width roughness (LWR) in the lithography process. The calculated results of the FWRs and the gate lengths L = 7-nm and 5-nm are addressed with the cases of electric potentials with the y-direction along the gate length, electric potentials with the x-direction along the fin width, and the absolute drain currents with the gate lengths L = 7-nm or 5-nm due to gate voltages. According to the gate length, the impact of the FWR patterns on the performance of fin-field-effect-transistors (FinFETs) can find regular fluctuations.

The challenges of patterning next-generation integrated circuits have driven the semiconductor industry to look outside of traditional lithographic methods in order to continue cost-effective size ...

ML (Machine Learning)-based artificial neural network (ANN) model is proposed to estimate the LER (line edge roughness)-induced performance variation in Fin-shaped Field Effect Transistor (FinFET). For a given LER features such as rms amplitude(Δ), correlation length along x-direction (AX), and correlation length along y-direction (AY), the metrics for device performance such as on-state drive current, off-state leakage current, threshold voltage, and subthreshold swing can be computing-efficiently estimated with the ANN model.

We investigate, for the first time, the effect of line-edge roughness (LER)-induced variability for dual-metal gate (DMG) Fin field-effect transistors (FinFETs) using a computer-aided-design simulation. The Gaussian autocorrelation function is utilized for generating the LER sequence. From the standard deviations of subthreshold swing (SS), threshold voltage (VTH), and transconductance (gm), the simulation results indicate that the LER-induced electrostatic integrity variability is related to the ratio of control gate to total gate lengths. The variability caused by LER degrades with respect to the length of control gate near the source. Our work fills a gap in the study of LER-induced variability for DMG FinFETs, and suggests that the length of the control gate near the source should be greater than or equal to the screen gate near the drain in the entire gate.

Nanosheet field-effect transistors (NSFETs) have emerged as a novel device replacement for sub-7nm CMOS technology nodes. However, due to smaller fin thickness (Tfin = 5nm), NSFETs are more vulnerable to the process-induced variations. Among various types of process-induced variations, Line edge roughness (LER) is becoming a significant concern for multi-gate field-effect transistors (MugFETs) with smaller feature sizes. In this article, we have reported and compared the impact of LER on the electrical characteristics of NSFETs and nanowire field-effect transistors (NWFETs) for the sub-7nm technology node. We have generated a 3-D LER profile using 2-D Auto Covariance Function (ACVF) that considers two degrees of freedom for a realistic roughness analysis at advanced CMOS technology nodes. For a complete study of 3-D LER effect in NSFET, we have considered roughness along the nanosheet's sidewalls as well as top and bottom surfaces. We have shown using 3D TCAD simulations that the sidewall roughness in NSFETs contributes to a negligible mismatch in threshold voltage and ON current. The mismatch performance of NSFET is compared with that of the NWFET for sub-7nm technology node. NSFET appears to be more immune to mismatch in ON current than NWFETs considered in this work. On the other hand, as compared with NSFET, owing to its superior gate all-around control, the NWFET achieves lower mismatch in drain induced barrier lowering (DIBL) and subthreshold slope (SS) in presence of LER. In addition to this, FETs with different channel doping modes such as inversion (IM) and Junction less (JL) mode have been compared for their matching performance against 3-D LER. It can be concluded from the results that IM FETs are more immune to 3-D LER as compared to JL FETs.

Guest Editors Alan Brodie and Martha I. Sanchez introduce the JM3 Special Section on Masks and Lithography in the Era of Multi-beam Mask Writers.

Extreme ultraviolet lithography (EUV) materials and processes are constantly evolving and maturing, making sub-30 nm pitch single-exposure yield feasible. Characterization methodologies for stochastic variations are well-documented at this stage, with most employing critical dimension scanning electron microscopy (CDSEM) and a form of defect inspection to quantify line edge roughness (LER), local critical dimension uniformity and patterning failures. In this paper, the link between LER and stochastic defectivity is explored at a deeper level, as we probe the possibility of nucleating stochastic failures with programmed LER structures at 30 nm pitch using CDSEM, optical inspection and electrical yield data. First, we characterize LER post-develop and post-etch using unbiased LER measurements. Second, we study the defectivity and optical characteristics of the programmed LER pattern post hard mask open using optical inspection. Specifically, we measure the optical noise induced by programmed LER, the inspection performance in terms of defect capture and nuisance rate, and the predictive capability of optical inspection through a comparison of defectivity with electrical yield data.

As the industry continues to push the limits of integrated circuit fabrication, reliance on EUV lithography has increased. Additionally, it has become clear that new techniques and methods are needed to mitigate pattern defectivity and roughness at Litho and Etch together with eliminating film-related defects. These approaches require further improvements to the process chemicals and the lithography process equipment to achieve finer patterns. In particular improvements in the coater/developer hardware and process are required to enable the use of a wide variety of chemicals as well as compatibility with existing systems. This paper reviews the ongoing progress in coater/developer processes that are required to enable EUV patterning sub-30nm line and space by using MOR (Metal Oxide Resist).

In this study, the impact of the negative capacitance (NC) effect on process-induced variations, such as work function variation (WFV), random dopant fluctuation (RDF), and line edge roughness (LER), was investigated and compared to those of the baseline junctionless nanowire FET (JL-NWFET) in both linear (Vds = 0.05 V) and saturation (Vds = 0.5 V) modes. Sentaurus TCAD and MATLAB were used for the simulation of the baseline JL-NWFET and negative capacitance JL-NWFET (NC-JL-NWFET). Owing to the NC effect, the NC-JL-NWFET showed less variation in terms of device performance, such as σ[Vt], σ[SS], σ[Ion/Ioff], σ[Vt]/µ[Vt], σ[SS]/µ[SS], and σ[Ion/Ioff]/µ[Ion/Ioff], and enhanced device performance, which implies that the NC effect can successfully control the variation-induced degradation.

In roll-to-roll digital maskless lithography (R2R DML) equipment, it is difficult to achieve high quality, owing to surface deformation that affects the pattern position. To address this issue, we simulated the patterning results of R2R DML to analyze the relationship between positional errors and pattern quality. Errors perpendicular to the pattern direction exhibited a 1.3–2 times greater effect on the linewidth and line edge roughness compared to those parallel to this direction. We confirmed that positioning errors could lead to defects in which the photoresists were not fully exposed. Finally, through simulations, we found that the effect of positional errors could be reduced by controlling the array spot separation length.

Two earlier publications showed that mask defectivity contributes to the stochastics of the EUVL-printed image on wafer. The present contribution gives more insights into the methodology and resist models used therein. In addition, an extended study of two types of mask roughness is presented, comprising mask absorber line-edge roughness and rippling of the multilayer mirror on the mask. For both, it is shown that contributions to stochastics are larger than expected purely from normalized intensity log-slope considerations. As a second topic, printability of local defects is readdressed at smaller pitches and more state-of-the-art illumination settings, in preparation to a genuine study of mask defectivity contribution to wafer printing stochastics at high-NA EUV lithography. First results for one-dimensional mask patterns indicate an influence of the anamorphic characteristic of high-NA imaging, showing a different behavior for vertical and horizontal orientations.

Nanosheet gate-all-around (GAA) field-effect transistor (NSFET) is a potential replacement for the FinFET at advanced technology nodes owing to better control of short-channel effects and higher drive current. Due to the increased complexity of the GAA stacked structure, new forms of process variability come into the picture, which are dominant over the conventional process variability such as metal gate granularity (MGG) and line edge roughness (LER) for FinFETs. In this article, we show one such process variability called as metal thickness variation (MTV). MTV causes WF mymargin variations on the gates of the GAA sheet transistor and results in a significant ${V}_{T}$ variability. The impact of MTV is studied using an analytical framework. We studied three variants of NSFETs and reported variability in terms of key device design parameters such as intersheet spacing and metal thicknesses. The results presented here help in designing the process flow for a type of NSFET to minimize the ${V}_{T}$ variability.

Standard samples with programmed micro-defects were fabricated for evaluating the defect detection capability of the next generation of pattern inspection tools. A 1.5-nm protrusion programmed defect and a 4-nm-wide (

Quantitative analysis of line edge roughness (LER) is very important for understanding the root causes of LER and thereby improving the pattern quality in near-field lithography (NFL), because LER has become the main limiter of critical dimension (CD) control as the feature size of nanostructures is scaled down. To address this challenge, the photoresist point-spread function of NFL with a contact plasmonic ridge nanoaperture can be employed to account for the physical and chemical effects involved in the LER-generation mechanism. Our theoretical and experimental results show that the sources of LER in NFL mainly come from the aerial image, material chemistry, and process. Importantly, the complicated decay characteristics of surface plasmon waves are demonstrated to be the main optical contributor. Because the evanescent mode of surface plasmon polaritons (SPPs) and quasi-spherical waves (QSWs) decay in the lateral direction, they can induce a small image log-slope and low photoresist contrast, leading to a large LER. We introduce an analytical model and demonstrate the relationship between LER and CD to estimate the pattern quality in NFL. We expect that these results can provide alternative approaches to further improve pattern uniformity and resolution, which can lead to advanced nanopatterning results in NFL.

Although several years delayed than its initial plan, extreme UV lithography (EUVL) with 13.5nm wavelength has been finally implemented into high volume manufacture (HVM) of mainstream semiconductor industry since 2018. With the delivery and installation of ASML EUV scanners in those giant Fab players like Samsung, TSMC and Intel, EUV lithography is becoming a sort of industry standard exposure metrology for those critical layers of advanced technology nodes beyond 7nm. Although ASML NXE EUVL scanner is the only commercialized EUV exposure system available on the market, its development is the concentration of all essence from worldwide industrial and academic collaboration. It is becoming more and more important not only for fab runners but also for main stream fabless design houses to understand and participate the progress of EUVL. In this review, working principles, module structures and technical challenges have been briefly discussed regarding each EUV subsystem, including light source, reflection mirrors and system, reticle module as well as photoresist development. EUV specific issues of light intensity, defectivity within reflection system, line edge roughness (LER) and mask 3D effects have been focused respectively and promising solutions have been summarized as well.

Variability of semiconductor devices is seriously limiting their performance at nanoscale. The impact of variability can be accurately and effectively predicted by computer-aided simulations in order to aid future device designs. Quantum corrected (QC) drift-diffusion (DD) simulations are usually employed to estimate the variability of state-of-the-art non-planar devices but require meticulous calibration. More accurate simulation methods, such as QC Monte Carlo (MC), are considered time consuming and elaborate. Therefore, we predict TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability on a 10-nm gate length gate-all-around Si nanowire FET and perform a rigorous comparison of the QC DD and MC results. In case of the MGG, we have found that the QC DD predicted variability can have a difference of up to 20% in comparison with the QC MC predicted one. In case of the LER, we demonstrate that the QC DD can overestimate the QC MC simulation produced variability by a significant error of up to 56%. This error between the simulation methods will vary with the root mean square (RMS) height and maximum source/drain $n$ -type doping. Our results indicate that the aforementioned QC DD simulation technique yields inaccurate results for the ON-current variability This work was supported in part by the Spanish Government under Project TIN2013-41129-P and Project TIN2016-76373-P, in part by Xunta de Galicia and FEDER funds under Grant GRC 2014/008, in part by the Consellería de Cultura, Educación e Ordenación Universitaria (accreditation 2016-2019), under Grant ED431G/08, and in part by the Centro de Supercomputación de Galicia (CESGA) for the computer resources provided. The work of G. Indalecio was supported by the Programa de Axudas á Etapa Posdoutoral da Xunta de Galicia under Grant 2017/077. The work of N. Seoane was supported by the RyC program of the Spanish Ministerio de Ciencia, Innovación y Universidades under Grant RYC-2017-23312 SI

Direct Self-Assembly (DSA) is expected to be applied to patterns below 20 nm, and many applications have been proposed along with several lithography techniques. The advantage of DSA is that the molecular weight of the polymer can control the pattern size and achieve a fixed pattern pitch. On the other hand, the DSA process faces the technical challenges of pattern defects, line edge roughness (LER), and pattern transfer to the underlying layer. Tokyo Electron has reported the results of these improvements in the past SPIE. This report introduces each optimization method and shows you the next steps.

Directed self-assembly (DSA) is one of the candidates for next generation lithography. Over the past years, many papers and presentation have been reported regarding DSA, and Tokyo Electron Limited (TEL is a registered trademark or a trademark of Tokyo Electron Limited in Japan and /or other countries.) also has presented the evaluation results and the advantages of each1-10. Polystyrene-b-polymethyl methacrylate (PS-b-PMMA) has been used in many report because the polymerization technology is established and it is easy to form vertical patterns. In addition, the chemical epitaxy flow for PS-b-PMMA has established well to improve defectivity, line edge roughness and line width roughness. On the other hand, it is difficult to achieve less than 24nm pitch pattern by PS-b-PMMA because of the low chi parameter. In this paper, the combination process of DSA and SADP (self-aligned double pattern) is proposed for further small pitch pattern by PS-b- PMMA and latest results are reported.

The authors present latent image characterization in photoresists by means of extreme ultraviolet (EUV) spectroscopic reflectometry. The optical constants of photoresists before and after exposure are measured in the EUV spectral range. Latent images are investigated in the form of periodic line gratings. The investigation is performed by the analysis of spectroscopic reflectance curves in the wavelength range from 5 nm to 20 nm at grazing incidence angles. Through an analysis of the reflectance curves based on rigorous electromagnetic modeling, a characterization of parameters of interest of the latent image is evaluated. This includes the latent image profile, surface topography and stochastic-related parameters such as line edge roughness.

In this study, we developed a methodology to evaluate scanning electron microscopy (SEM)-based line edge roughness (LER) metrology. In particular, we used a metrological tilting atomic force microscopy (tilting-mAFM) as LER reference metrology. We analyzed the height-height correlation function (HHCF) of SEM line-edge profiles combining averaging and unbiased correction methods. The direct comparison of our method with tilting-mAFM enabled a precise evaluation of the SEM-based LER metrology. We demonstrated that a combination of unbiased HHCF and averaging methods with appropriate condition enabled relatively precise measurement of three roughness parameters. We observed that, for precise roughness evaluation, reducing noise in the line-edge profiles is important before performing the HHCF analysis and unbiased correction.

This paper extends the 2019 findings, that local defects on an EUV mask are trigger points for stochastic failures on the printed wafer, to a simulation study of non-local mask deficiencies. These relate to shortcomings of a larger area nature where the reticle deviates from an ideal reticle or fails specification. These include aspects such as global CD error, absorber slope, contamination effects, line edge roughness, and multilayer roughness. The presented results suggest that mask specifications may need refinement, specifically for roughness type deficiencies, in order to help mitigate the mask contribution in the stochastics of wafer printing by EUV lithography.

In this work, the fluctuations of the electrical characteristics including ON -current, OFF -current, subthreshold swing and threshold voltage, due to line edge roughness (LER) for double-gate charge-plasma junctionless transistor (CPJLT) and side-wall charge-plasma junctionless transistor (S-CPJLT) are explored. Results shows that S-CPJLT has less fluctuations in ON -current while maintaining similar performance of other electrical characteristics. Besides, S-CPJLT has larger ON-current, smaller OFF-current on average. This work indicates that S-CPJLT has greater potential in electronic device development.

The aim of this contribution is to study the effect of roughness on the propagation constant in interconnect structures. For this purpose, a stochastic framework is constructed around a full-wave electromagnetic field solver. To reduce the number of repeated calls to the full-wave simulator, two sparse stochastic techniques have been implemented and tested. A balance between calculation time and accuracy is sought for and found, which is demonstrated for a rough rectangular waveguide.

We investigated the contribution ratio of process fidelity and beam accuracy in patterning with the multi-beam mask writing system. A beam pitch-related line edge profile may occur, which impacts on line edge roughness (LER) in the multi-beam writing system. The printability of beam image into the final etched pattern depends on the mask process, therefore, we need to understand quantitatively the printability of beam placement errors on LER with the actual mask process. We examined how the patterning characteristics are modified in each step of the mask process. The printability of beam placement errors largely depend on the period of errors, rather than the amplitude of errors. These results can optimize the writing strategy in multi-beam mask writing.

The different typical noise components observed in SEMs are important aspects to image quality and thus performance, yet models for adding realistic noise to model-generated images is an area where improvement of SEM simulation is important for addressing critical IC industry applications. Understanding how realistic factors affect the achieved noise distribution is important to achieve realistic noise characteristic fidelity in simulated images with respect to experimental images. Achieving realistic noise is important to enable simulations to help address many industry issues, such as minimizing line edge roughness measurement uncertainty. In this work, JMONSEL will be used to simulate various test structures with many repeats to observe how the noise distribution changes spatially, which will allow us to understand the noise dependencies on material and local geometry, which should give insight into the possible need for more detailed attention to how noise is applied to analytically-generated images.

Background: Line-edge roughness (LER) is often measured from top-down critical dimension scanning electron microscope (CD-SEM) images. The true three-dimensional roughness profile of the sidewall is typically ignored in such analyses. Aim: We study the response of a CD-SEM to sidewall roughness (SWR) by simulation. Approach: We generate random rough lines and spaces, where the SWR is modeled by a known power spectral density. We then obtain corresponding CD-SEM images using a Monte Carlo electron scattering simulator. We find the measured LER from these images and compare it to the known input roughness. Results: For isolated lines, the SEM measures the outermost extrusion of the rough sidewall. The result is that the measured LER is up to a factor of 2 less than the true on-wafer roughness. The effect can be modeled by making a top-down projection of the rough edge. Our model for isolated lines works fairly well for a dense grating of lines and spaces as long as the trench width exceeds the line height. Conclusions: In order to obtain and compare accurate LER values, the projection effect of SWR needs to be taken into account.

Line-edge roughness (LER) is often measured from top-down critical dimension scanning electron microscope (CD-SEM) images. The true three-dimensional roughness profile of the sidewall is typically ignored in such analyses. We study the response of a CD-SEM to sidewall roughness (SWR) by simulation. We generate random rough lines and spaces, where the SWR is modelled by a known power spectral density. We then obtain corresponding CD-SEM images using a Monte Carlo electron scattering simulator. We find the measured LER from these images, and compare it to the known input roughness. We find that, for isolated lines, the SEM measures the outermost extrusion of the rough sidewall. The result is that the measured LER is up to a factor 2 less than the true on-wafer roughness. The effect can be accurately modelled by making a top-down projection of the rough edge. Our model for isolated lines works fairly well for a dense grating of lines and spaces, as long as the trench width exceeds the line height.

The manufacturing of semiconductor devices using extreme ultraviolet (EUV) lithography started in 2019. A high numerical aperture tool under development is capable of resolving 8 nm line-and-space optical images and will extend the application of EUV lithography. However, resist materials have not been yet applicable to the production with 8 nm resolution. In this study, the relationships among the half-pitch of line-and-space patterns (resolution), chemical gradient [an indicator of line edge roughness (LER)], and sensitivity were investigated in the sub-10 nm half-pitch region for chemically amplified EUV resists. The chemical gradient was simulated on the basis of their sensitization and reaction mechanisms. The relationship was formulated as a function of total sensitizer concentration (the sum of photoacid generator and photodecomposable quencher concentrations) and the thermalization distance of secondary electrons. The effect of thermalized electrons was well incorporated into the trade-off relationships between resolution, LER, and sensitivity. (147/150)

Pitch uncertainty and line edge roughness are among the critical quality attributes of a pitch standard and normally the analyses of these two parameters are separate. The analysis of self-traceable Cr atom lithography nano-gratings shows a positive relevance and sensitivity between LER and evaluated standard deviation of pitch. Therefore, LER can be used as an aided pre-evaluation parameter for the pitch calculation method, such as the gravity center method or the zero-crossing points method. The optimization of the nano-grating evaluation method helps to obtain the accurate pitch value with fewer measurements and provide a comprehensive characterization of pitch standards.

In this paper, we investigated the effects of the correlation length of line edge roughness (LER) on the variability of 14-nm inversion mode (IM) and junctionless (JL) FinFETs by technology-computer-aided-design simulation. We examined the effects of the correlation length of gate LER (GLER) and of fin LER (FLER) on the device variability separately. The simulation results show that, for the 14-nm IM FinFET, both the GLER-induced and FLER-induced device variations will decrease as the correlation length of LER increases. Therefore, increasing the correlation length of LER is also an effective way to reduce the LER-induced device variations besides decreasing the rms amplitude (σ) of LER. In addition, as far as LER is concerned, GLER is the major source for device variations when devices operate in the subthreshold region and FLER is the major source for device variations when devices are in the ON state. However, for the 14-nm JL FinFET with the same fin geometry as the IM FinFET, the FLER-induced...

We examine the impact of line-edge roughness (LER) on the variability in the on-current and saturation threshold voltage of ultrascaled FinFET devices via quantum-mechanical transport simulation. We obtain a realistic model of LER by decomposing the LER into short- $\lambda $ and long- $\lambda $ fluctuations, and we consider their separate influences on device performance. We show that the long- $\lambda $ fluctuations lead to greater device variability than the short- $\lambda $ fluctuations, and we explain the difference between the two cases via the influence of fluctuating quantum confinement arising from the LER. Finally, we consider devices in which the long- $\lambda $ fluctuations of the two fin edges are correlated and demonstrate that this correlation significantly improves the variability. Thus, we show the continued need for fabrication technology either to reduce the amplitude of the long- $\lambda $ fluctuations or to ensure the long- $\lambda $ fluctuations between the sidewalls of ultrascaled FinFET devices are correlated.

In aggressively scaled devices, the FinFET technology has become more prone to line edge roughness (LER) induced threshold voltage variability. As a result, nano scale FinFET structures face the problem of intrinsic statistical fluctuations in the threshold voltage. This paper describes the all LER induced variability of threshold voltage for 14 nm underlap FinFET using 3-D numerical simulations. It is concluded that percentage threshold voltage ( V TH ) fluctuations referenced with respect to rectangular FinFET can go up to 8.76%. This work has also investigated the impact of other sources of variability such as random dopant fluctuation, work function variation and oxide thickness variation on threshold voltage.

As the physical sizes of devices have been scaled down, the negative impact of process-induced random variation on device performance has increased; therefore, there is an urgent demand for advanced simulation methods for variation. In this paper, a 3-D quasi-atomistic simulation methodology for line edge roughness (LER) in nonplanar devices, such as FinFETs and gate-all-around (GAA) FETs, is proposed. In addition, a simple gate oxide layer model is proposed to analyze the impact of LER on device performance while excluding the impact of oxide thickness variation. To verify the importance of the quasi-atomistic 3-D LER model and to compare the LER-induced performance variation in a FinFET to that in a GAA FET, the case studies using the 3-D quasi-atomistic LER model for FinFETs and GAA FETs are performed.

Mueller matrix ellipsometry (MME) is applied to characterize lithographic patterns with natural line edge roughness (LER). A computationally efficient approach based on effective medium approximation is proposed to model the effects of LER in MME measurements. We present both the theoretical and experimental results on lithographic patterns with realistic LER which demonstrate that MME in combination with the proposed effective modeling method is capable of quantifying LER amplitudes. Quantitative comparisons between the MME and scanning electron microscopy measured results also reveal the strong potential of this technique for in-line nondestructive line roughness monitoring.