Search

In this work, we evaluate the importance of the postmetallization annealing (PMA) temperature on the performance of HfxZr1−xO2-based ferroelectric tunnel junctions (FTJs). Our results indicate a significant difference in tunneling electroresistance (TER) ratio and endurance, depending on the PMA temperature despite negligible variations in remanent polarization. We conclude that the minimization of conductive oxide defect states is central to achieve high performance. Through carefully optimized PMA conditions, we demonstrate FTJs with a TER = 3 and low mean cycle-to-cycle variation of < 1.5% combined with at least 16 separable conductance states providing a 4-bit resolution analog FTJ.

Ferroelectric memories based on hafnium oxide are an attractive alternative to conventional memory technologies due to their scalability and energy efficiency. However, there are still many open questions regarding the optimal material stack and processing conditions for reliable device performance. Here, we report on the impact of the sputtering process conditions of the commonly used TiN top electrode on the ferroelectric properties of Hf1–xZrxO2. By manipulating the deposition pressure and chemistry, we control the preferential orientation of the TiN grains between (111) and (002). We observe that (111) textured TiN is superior to (002) texturing for achieving high remanent polarization (Pr). Furthermore, we find that additional nitrogen supply during TiN deposition leads to >5× greater endurance, possibly by limiting the scavenging of oxygen from the Hf1–xZrxO2film. These results help explain the large Prvariation reported in the literature for Hf1–xZrxO2/TiN and highlights the necessity of tuning the top electrode of the ferroelectric stack for successful device implementation.

InSb has the smallest bandgap and highest electron mobility among III‐V semiconductors and is widely used for photodetectors and high‐frequency electronic applications. Integration of InSb directly on Si would drastically reduce the fabrication cost and enable new applications, however, it is very challenging due to its 19% lattice mismatch with Si. Herein, the integration of single‐crystalline InSb microstructures on insulator‐covered Si through rapid melt growth (RMG) is reported and specifically provides details on the fabrication process. The importance of achieving high‐quality conformal capping layers at low thermal budget to contain the InSb melt is assessed when the sample is annealed. The importance of ensuring a pristine Si seed area to achieve single‐crystalline InSb is illustrated and demonstrated here for the first time. Herein, the integration of single‐crystalline InSb microstructures on insulator‐covered Si through rapid melt growth (RMG) and the details of the fabrication process are reported. This article is focued on the importance of having a high‐quality conformal capping layer and pristine Si/InSb interface required for achieving single‐crystalline InSb.