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In this paper, we presents the effect of higher back plane doping on analog figure of merit of fully depleted-silicon on insulator (FD-SOI) MOSFETs at RF frequencies. Procedure for DC and RF parameter extraction at RF frequencies has been discussed. Surface potential based Industry standard BSIM-IMG model for FD-SOI MOSFETs with enhanced gate parasitic network is used for validation of extracted DC and RF parameters such as gate resistance, gate parasitic capacitance, output conductance, transconductance.

An accurate physics-based lumped-circuit model, representing the nonquasi-static effect and the distributed polygate electrode resistance in bulk MOSFET is proposed. In our approach, an improved physical equivalent circuit capturing NQS effect is developed by using pole-zero compensation technique. The new model takes into account the inherent delay in the response of channel charges to the applied voltage. The proposed model is implemented in BSIM6 MOSFET model, and it is validated with Y-parameter data obtained from technology computer-aided design device simulations. The proposed model is in very good agreement with the device data up to 50/t, which ensures that it is suitable for most RF applications over any other computationally complex compact models.

In this paper, we present a novel physics based model for front and back gate coupling in UTBB (Ultra Thin body with Buried oxide) Fully Depleted Silicon On Insulator (FD-SOI) Transistors, which is then used in deriving the front and back gate surface potentials. To the best of our knowledge this is the first time a physical coupling model is being presented. The methodology discussed in this work is valid for any transistor irrespective of the geometry. The model shows accurate match with the exact numerical solution.

In this paper we have proposed new physics based analytical models for transport and flicker noise in field effect transistors (FETs) working in the quasi-ballistic regime. The model is capable of accurately predicting the device current and low frequency flicker noise power spectral density for all drain and gate biases and includes short channel effects. It takes length scaling into account and can be used for the full range of devices starting from complete drift-diffusive to completely ballistic. This is the first time an analytical model of flicker noise for quasi-ballistic devices is being presented. The model is generic and can be used for any device geometry and construction. The model has been verified with experimental data from literature.

In this paper, we demonstrate using extensive TCAD simulations that low frequency noise behavior is significantly different in presence of halo implants. The study of the noise behavior is extended to source side halo, drain side halo, symmetric halos and uniformly doped devices for different doping and length of the halo regions. Our study shows that source side halo region is responsible for the anomalous noise behavior in saturation. Such noise behavior can be accurately modeled with the presented SPICE model over wide range of biases and geometries. This study physically explains the trends observed in low frequency noise measurement in advanced CMOS technologies.

Negative capacitance based transistors are being considered as competent candidates in the low power regime due to their excellent switching characteristics. In this work we use a physics based compact model for negative capacitance (NC) FinFETs to study device-circuit interactions focusing on the delay and energy dissipation aspects of NC-FinFET based CMOS circuits. Our modeling approach involves coupling of the Landau-Devonshire model of ferroelectric materials with the standard BSIM-CMG model of FinFET. State of the art 22 nm technology node n- and p-FinFETs are chosen as the internal MOSFETs. We investigate the impact of scaling the ferroelectric thickness and variation of ferroelectric properties, namely the remnant polarization and coercive electric field on the energy-delay tradeoffs in a 17-stage ring oscillator circuit.

A quantum mechanical model of charge centroid is presented for III-V FETs. The model takes into account the finite potential barrier at the semiconductor/insulator interface and also the non-linearity of the potential profile. The model takes two energy subbands into account to calculate the centroid shift and has been validated against TCAD simulations.

Tunnel FETs (TFETs) with steep switching slope have emerged as an attractive device for energy-efficient circuit implementations. In this work, we explore Spiking Neural Network (SNN) based on Tunnel FETs. Neuron and binary image edge detection circuits implemented using 22 nm predictive technology-based bulk MOSFET models and 20 nm Verilog-A-based table model GaSb-InAs heterojunction TFETs are studied. TFET-based implementation is seen to provide better performance at lower power consumption regime, while the MOSFET-based edge detection circuit produces superior performance at higher power regime.

In this paper, we aim to present an overview of a surface-potential (SP) based model named “Advanced Spice Model for High Electron Mobility Transistor” (ASM-HEMT) for AlGaN/GaN HEMTs. This model is presently under consideration in the phase-III of industry standardization by the Compact Model Coalition (CMC). SP of GaN HEMT is obtained by solving Schrodinger and Poisson equations in the triangular potential well considering the first two energy subbands. The core drain current model and a intrinsic charge model are derived using the developed SP model. Various real device effects like: velocity saturation, drain-induced barrier lowering (DIBL), self-heating, field dependent mobility, non-linear access region resistances etc. are included in the core drain current model to represent real GaN HEMTs. Field-plate (FP) model is incorporated to predict accurate current and capacitance trends observed in the high power GaN HEMTs with source and gate connected field-plates. Along with the gate current model, non-linear trapping effects are also included in the model to capture larghe-signal high-frequency device behavior. This model is extensively validated with the experimental data of both high power and high frequency GaN HEMTs.

Amongst different two-dimensional semiconductor materials, silicene is fast emerging as a promising candidate for use as the channel material in field effect transistors. In this work, we first perform ab-initio calculations within density functional theory to obtain the band structure of mono- and multi-layered hydrogenated silicene, commonly known as silicane, in different stacking configurations. We then investigate the ultimate device performance of silicane FETs in the ballistic limit using the semiclassical “top of the barrier” transport model for different number of layers.