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Abstract: A new open-loop high-speed CMOS sample-and-hold is presented. Based on new method for further reduction of voltage-dependent charge injection, a new CMOS sample-and-hold was designed. Simulation results confirm the effectiveness of this method. Over 10dB improvement in signal-to-noise ratio, compared to the signal-to-noise ratio of conventional bottom plate sampling S/Hs was achieved with this method. A comparison between newly designed S/H and the bottom-plate sampling S/H is presented. [Copyright &y& Elsevier]

Abstract: A new high-speed successive approximation analog-to-digital converter (ADC) architecture is presented. Two-bits extraction in each clock cycle is the key idea to double the conversion speed. Generating reference levels for three comparators with only two digital-to-analog converter (DACs), is another novelty of the new architecture. The proposed DAC structure allows a substantial reduction in overall control logic complexity. A 10-bit 40Ms/S successive approximation ADC was designed based on the proposed architecture in CMOS technology. The simulation results show that the proposed architecture introduces 7% reduction in power consumption over conventional architecture. Furthermore, chip area for the new ADC is 40% less than what otherwise would be needed by an ADC using conventional architecture. [Copyright &y& Elsevier]

Abstract: A novel single-stage second-order structure for Gm-C filters is presented. It allows ample reduction in hardware and thus power consumption. Moreover, due to exploiting otherwise parasitic poles, the structure allows much higher bandwidth than in conventional designs, be achieved. To verify effectiveness of new concept, and based on the new approach to implement second-order stages, a third-order and a fifth-order continuous-time low-pass filters were implemented. The filters fabricated in a CMOS process, achieved more than 430MHz, bandwidth and less than THD for a 400m 100MHz input signal. All these accomplished with a factor of about four reduction in hardware and power. The bandwidth, output voltage swing, and dynamic range are far larger than those of any other CMOS low-pass filters thus far reported, which have bandwidth higher than 100MHz. [Copyright &y& Elsevier]

Abstract: In this paper a new CMOS current-mode four-quadrant analog multiplier and divider circuit based on squarer circuit is proposed. The dual translinear loop is the basic building block in realization scheme. Supply voltage is 3.3V. The major advantages of this multiplier are high speed, low power, high linearity and less dc offset error. The circuit is designed and simulated using HSPICE simulator by level 49 parameters (BSIM3v3) in standard CMOS technology. The simulation results of analog multiplier demonstrate a linearity error of 1.1%, a THD of 0.97% in 1MHz, a bandwidth of 41.8MHz and a maximum power consumption of 0.34mW. [Copyright &y& Elsevier]

Abstract: In this paper, an equalizer chip for digital communication channel is presented. The proposed system can equalize the CAT5e UTP cable from 20 to 400m with a 30MHz bandwidth. A novel structure has been used to realize GM-C filter. It uses only one GM-cell stage in contrast of conventional structures. This technique leads to improvement excess-phase, area and power consumption. An intelligent fuzzy controller tunes this filter. It changes the filter parameters based on reference eye pattern to achieve the best tuning for the filter. Layout of all circuits has been done in standard CMOS process. Total power consumption, area and power supply are 29.3mW, and 3.3V. [Copyright &y& Elsevier]