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As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.

Conventional scaling of planar CMOS devices has reached a practical electrostatic design limit at roughly 25nm gate lengths, corresponding to the 20nm node. The double-gate transistor has long been known to offer the potential to extend electrostatic scaling and in the last dozen years, workers around the world, in academia and industry, have applied a vertical fin-like embodiment of the double-gate FET, most popularly referred to as the 'FinFET,' to tackle the challenges of process, device, and product design, and accomplish the introduction of double-gate FETs into main-stream manufacturing. A view of these challenges and their solution leads to a projection that this FinFET structure will prove scalable to at least the atomic limit of CMOS scaling.

Nanoelectronics will have to face major challenges in the next decades in order to proceed with increasing progress and reduced variability. New progress laws combined to the scaling down of CMOS based technology will emerge to enable new paths to Functional Diversification. New materials and disruptive architectures, Heterogeneous Integration, introducing 3D schemes at the Front End and Back End levels, will be introduced to make it possible.

The superior transport properties of III-V materials makes them attractive choices to enable improved performance at low power. This paper examines the module targets and challenges for III-V materials to be successfully integrated for high performance/low power logic at or beyond the 11 nm technology node. A VLSI compatible, self-aligned, III-V on 200mm Si MOSFET process flow is presented using an industry standard toolset. Statistically significant data shows that III-V devices can be processed on a Si line with controlled contamination, good uniformity and yield. The Lg = 500 nm device has a drive current of 471 µA/µm (Vgs = Vds = 1V) and intrinsic transconductance of 1005 µS/um.

Fully depleted SOI (FDSOI) is a viable option for continued CMOS scaling. In this paper, we overview key challenges for designing and manufacturing extremely thin SOI (ETSOI) devices and provide solutions to each challenge. We demonstrate successful fabrication of ETSOI devices with physical gate length down to 25nm and SOI channel thickness down to 3.5nm. Our highly scaled ETSOI devices exhibit excellent electrostatics and respectable performances. We further discuss unique opportunities enabled by ETSOI for reducing CMOS process complexity and therefore reducing process cost, which in turn at least partially offsets the higher cost of SOI substrates. The unique advantages of ETSOI in conjunction with the presented solutions to challenges render ETSOI a strong candidate for scaling planar CMOS to 22-nm node and beyond.

As the planar CMOS transistor devices scaling down, a lot of original process have to be optimized, developed or changed to meet the evolutional requirement, and the new process elements were continuously implemented into the manufacture. The STI-liner is one of the processes from the STI module, which comes after the trench etch and before the trench gap-fill, to provide an excellent interface and good adhesion between the silicon and the oxide. While the device scaling down, some device issues, such as, the incident of dislocations which impacted on the device leakage current, the dopant segregation which result in the threshold voltage variation and impact the inverse narrow width effect (INWE) and the gate oxide integrity (GOI), etc, are associated with the STI module and can be improved by the STI-liner process. The STI liner process is evolved from the furnace oxidation, the dry RTO, the nitrided oxide liner to the ISSG.

Aggressive CMOS scaling and device performance enhancement is pursued thgrough the use of advanced dielectric and substrate materials. High-k dielectric materials are the key to both dramatically reduce the standby leakage current (and thus power consumption) and to enable the use of high mobility substrates. Critical for device performance and reliability are both the interface quality and bulk defect control. The most important question for high-k materials is always: "How many defects can we allow in these materials and how these are going to influence the performance observed and the reliability?" This paper addresses these issues by looking at both the current understanding of defects in advanced materials for performance and reliability.

The advent of high-k/metal gates into production for CMOS gate stacks has marked the onset of MOSFET scaling that has clearly become reliant on new materials and / or new device architecture. Additionally, new approaches to form ultra-shallow junctions with high active-dopant concentrations and low schottky barrier height silicides with novel materials to reduce contact resistance have been reported by many groups and will continue to facilitate MOSFET scaling with increasing performance. It is becoming clear that Si (as the channel) may not be able to provide for the high performance combined with low power technologies that would be needed in future. Over several years, there has been a lot of research on high mobility channels: group IV for pMOSFETs and III-V for NMOSFETs. However, there appears to be little consensus on a) the choice of high mobility channels for P and N channel MOSFETs, b) its potential compared to short channel strained-Si, and 3) potential technology node for insertion. In this work, trends, challenges and opportunities related to several of the aforementioned modules (gate stack, junctions, contacts, and high mobility Ge based channels) will be briefly presented and discussed.

High-k/metal gate stacks are a promising and viable approach for CMOS scaling. The high permittivity of the dielectric used can reduce the leakage current while preserving the low equivalent oxide (EOT) thickness needed for the future step of technologies. The recent advances are very encouraging, but reliability aspects, in particular TDDB characteristics, are much less developed. In this paper we investigate the issue of progressive dielectric breakdown, a debated aspect (1-3), which is critical for evaluation of the device lifetime.

We review the impact of oxide-semiconductor interface chemistry and precursor choice on the quality of novel field-effect transistor gate dielectrics grown by atomic layer deposition (ALD). Focus is on hafnium- and aluminum-based high-permittivity ('high-k') gate dielectrics on silicon and on high carrier mobility (germanium, gallium arsenide) channels. We shed light on the ways processing parameters (choice of materials; surface preparation; high-k dielectric deposition process) determine stack structure (continuity of the high-k layer; interfacial oxide thickness; detrimental channel-dielectric interactions) and hence electrical quality. Trends are rationalized based on thermodynamic properties of the semiconductors, dielectrics, and metal-organic precursors involved. This may serve as a basic guideline for ALD precursor selection.

The development of CMOS technology is always driven by system needs. Traditionally, these needs have been met quite satisfactorily by simply reducing the physical size of the transistors as guided by the MOSFET scaling theory and increasing the chip-level integration density as anticipated from Moore's Law. Now that CMOS has reached some of its key scaling limits, continued progress has to come from innovations beyond the traditional development paths, again guided by anticipating and addressing system designers' concerns and needs. To make real progress, we need to understand where CMOS scaling has run into limits and where the new barriers are. In this talk, we examine the factors limiting the scaling of CMOS as well as the opportunities for extending current CMOS technology to continue satisfying the needs of system designers.