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Hybrid embedded testbench acceleration (HETA), a new approach to reduce communication overhead in hardware accelerators, speeds up simulation of chip prototypes by avoiding the communication between hardware and software. Experimental results on an industry design show that the proposed HETA approach is about 10 times faster than a commercial hardware accelerator and with only 0.57% hardware overhead.

Functional verification of complex SoC designs is a challenging task, which fortunately is increasingly supported by automation. This article proposes a verification component for IEEE Std 1500, to be plugged into a commercial verification tool suite.

This article surveys recent advances in hybrid approaches for functional verification. These approaches combine multiple verification techniques so that they complement one another, resulting in superior verification effectiveness.

It's usually necessary to apply formal verification on very small modules or else be content with bounded proofs on realistically large modules. But there is no denying that despite its capacity problems, formal verification has its strengths and utility and is a complementary technique to simulation. Used judiciously, simulation and formal techniques can complement each other's strengths, thereby balancing their respective weaknesses. There are different ways to combine these two techniques. In this article, we present two case studies of the application of one such technique: the hybrid verification of a serial protocol. We chose this example because of serial protocols' added complexity compared to parallel protocols. Both case studies involve the same serial protocol (I2C) but demonstrate different aspects of its verification. Selection of the same protocol in both case studies also demonstrates the tremendous value of reuse in formal verification.

For functional verification, software simulation provides full controllability and observability, whereas hardware emulation offers speed. This article describes a new platform that leverages the advantages of both. This platform implements an efficient scheme to record the internal behavior of an FPGA emulator and replay the relevant segment of a simulation in a software environment for debugging. Experimental results show an order-of-magnitude savings in debugging time compared to a software-only simulation approach.

This hybrid dynamic simulation scheme implements part of the simulator in software running on a processor and maps the rest onto a programmable hardware accelerator. An algorithm for hardware synthesis of behavioral testbenches enables better partitions, resulting in lower communication costs between the two components. TPartition improves the performance of hardware accelerated simulation without a designer's remodeling effort and without losing compatibility with the original testbench.

Functional verification is widely recognized as the bottleneck of the hardware design cycle. With the ever-growing demand for greater performance and faster time to market, coupled with the exponential growth in hardware size, verification has become increasingly difficult. Although formal methods such as model checking and theorem proving have resulted in noticeable progress, these approaches apply only to the verification of relatively small design blocks or to very focused verification goals. Current industry practice is to use separate, automatic, random stimuli generators for processor- and multiprocessor-level verification. The generated stimuli, usually in the form of test programs, trigger architecture and microarchitecture events defined by a verification plan. MAC-based algorithms are well suited for the test program generation domain because they postpone heuristic decisions until after consideration of all architectural and testing-knowledge constraints. Geneysys-Pro is currently the main test generation tool for functional verification of IBM processors, including several complex processors. We've found that the new language considerably reduces the effort needed to define and maintain knowledge specific to an implementation and verification plan.

Multimedia application design exploration should begin at the system level, to meet low-power and minimum-area requirements. Existing validation techniques mainly concentrate on lower abstraction levels. This system-level methodology combines formal verification of loop-oriented transformations with correctness verification of arithmetic constructs and related control flows. A videoconferencing-decoder example illustrates the methodology's efficiency.

CAD tool designers have given priority to providing features that will let circuit and logic designers use this custom-memory formal verification and analysis tool without a steep learning curve. This article discusses a few fundamental design decisions behind the successful deployment of a second-generation formal custom-memory equivalence-checking tool, Versys2, in the PowerPC design flows. The Versys2 symbolic simulator was developed at Motorola for verifying equivalence between register-transfer-level (RTL) designs and custom transistor circuit schematics.

The author explores applying formal Boolean equivalence verification to the RTL design flow, and introduces an effective equivalence-checking usage model that ensures optimal benefits in an RTL static sign-off methodology.

Software simulation remains the primary means of functional validation for hardware designs. Coverage metrics ensure optimal use of simulation resources, measure the completeness of validation, and direct simulations toward unexplored areas of the design. This article surveys the literature, and discusses the experiences of verification practitioners, regarding coverage metrics.

Research on practical design verification techniques has long been impeded by the lack of published, detailed error data. We have systematically collected design error data over the last few years from a number of academic microprocessor design projects. We analyzed this data and report on the lessons learned in the collection effort.

Extracting controlling finite-state machines can significantly reduce state space and thereby speed functional verification. The controller extraction algorithm uses an approach that frees it from restrictions on HDL code writing style.

Integrating packaging trade-off analysis with functional verification and architectural design results in a complete virtual prototyping solution far optimizing complex electronic systems. The authors discuss the role of packaging costs in system design and present examples highlighting packaging design trade-offs.

The e language forms the basis of an extensive set of tools and methodologies, collectively known as verification process automation, and almost all major electronics companies worldwide use it. This paper discusses IEEE design automation standards project and shows that how the value of technology can be enhanced by the standardization process.

Verification is currently the hot topic in EDA. The move to deep-submicron feature sizes in the latest IC designs has caused a paradigm shift, moving the emphasis from design to verification. Designers must create ICs with upwards of 50 million equivalent gates and still meet cost and time-to-market constraints. To do this, they are limiting new logic to a minimum and relying heavily on the reuse of existing functional blocks and embedded memory to create the required chip functionality. This trend puts even more pressure on the already difficult problem of verifying these massive chips. To cope with these increased demands, chip designers, and therefore the EDA industry, have moved to using specialized languages and tools that improve the efficiency of the verification process. Previously, verification involved writing a testbench in a hardware description language (HDL) such as Verilog (IEEE-1364) or VHDL (IEEE-1076). By using the same language for design and verification, the processes tend to be a continuum rather than distinct parts. This is a simple mechanism seemingly not requiring additional training, but it has serious shortcomings when applied to very complex problems. Large projects tend to use specialized languages and, in many cases, separate teams of verification engineers working independently from the design team. Two verification languages emerged in the mid-1990s: Verisity's e and System Science's Vera. These two languages have followed two very different paths.

During the late 1980s, there was a widespread belief that engineering workstations, widely distributed through development organizations and connected through local area networks, would become the dominant, if not the only, platform for EDA tools and electronic design. Despite early skepticism, logic synthesis began making serious inroads into the design process in the late 1980s and has now entered the mainstream. The EDA industry also focused on behavioral-level design and synthesis as a future possibility. Despite some notable efforts to develop such tools and methodologies, it is still in the research phase. Functional verification, on the other hand, has continued to rise to higher levels of design abstraction with the availability of higher-level languages and verification tools and despite the enduring controversies surrounding the standardization of these languages.

This is a review of A Practical Introduction to PSL (Springer, 2006) by Cindy Eisner and Dana Fisman. It is an excellent manual for engineers. The author explains why, seven years after the IEEE standardization, the absence of a textbook on PSL for the general academic community might be restraining the future development of hardware verification in industrial system designs.

This is a review of Embedded System Design: Modeling, Synthesis and Verification (by Daniel D. Gajski, Samar Abdi, Andreas Gerstlauer, and Gunar Schirner). The book introduces readers to embedded-systems design methodologies and tools, both those in use and those yet to come. It summaries the pioneering work of Daniel Gajski and colleagues in system-level design and shows both progress made and yet to be made in the field.

This is a review of Creating Assertion-Based IP (by Harry D. Foster and Adam C. Krolnik)—a tutorial on creating assertion-based verification IP for real designs, applicable to various classes of design blocks found in today's systems. This book uses the specific syntax of System-Verilog Assertions (SVA) and the verification environment of the Advanced Verification Methodology (AVM). However, the same principles apply to other assertion specification languages and within the context of other verification environments. Perhaps most importantly, this book teaches a way of thinking about creating and using assertion-based verification IP.

Hybrid techniques are effective for exploring interesting corner cases, coverage holes, invariant variations, and so forth, in the general area of directed functional validation. However, despite the emergence of several effective hybrid validation techniques, several questions still remain. The five articles in this special issue help explain some of the different facets of this area.

A review of the book, "Verification Methodology Manual for SystemVerilog," by Janick Bergeron et al.

The combination of SystemVerilog, SystemC, and the property specification language (PSL) promises a powerful and flexible foundation for design. Together, these standards address clear needs for emerging software-rich designs; critical capabilities for these standards include advanced verification features such as solvers and constrained random testing. This combination of standards brings powerful assertion capabilities that, with PSL, provide a bridge to formal verification and the ability to apply assertions across multiple design languages.

The design automation conference is the premier forum for members of the electronic design industry to exchange information on products, methodologies, and processes. Its attendees include more than 15,000 developers, designers, researchers, managers, and engineers from leading electronics companies and universities around the world. With more than 50 exhibitors, DAC offers a robust technical program covering the electronics industry's hottest trends.

Functional verification remains a major bottleneck of the design process. One approach to combating this bottleneck is to combine multiple, complementary techniques. This issue examines recent progress in this direction. The issue also includes two Perspectives articles: an extended summary of a report on system-in-package technology by the FSA SiP subcommittee, and a discussion on challenges and new requirements for effective validation of future system chips. Finally, this issue includes an article on memory built-in self-repair (BISR) and a roundtable on the future of multiprocessor SoC.

VLSI has fundamentally changed the relationship of the design automation tool developer and the product designer. IBM's design and verification subsystem responds to that change.