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An ultrahigh-speed 8 bit multiplexer (MUX) has been developed for future-generation optical-fiber communication systems having a data rate of 20 Gb/s. This IC was fabricated using a 0.5 /spl mu/m WN/sub x//W-gate GaAs MESFET process based on optical lithography, ion implantation, and furnace annealing for good reproducibility and high throughput. The WN/sub x//W bilayer gate has a low sheet resistance, improving the circuit high frequency performance. To attain 20 GHz operation, advanced circuit techniques for the source-coupled FET logic (SCFL) were introduced. A cross coupled source-follower (CCSF) was developed mainly for the highest speed buffers to enhance the bandwidth. The first-stage T-type flip-flop was designed with optimization techniques and operated up to 21.1 GHz. >

An 8-b slice GaAs bus logic LSI (BL) has been developed for a high-speed interconnection network in a multiple-instruction multiple-data stream (MIMD) parallel processing system. The BL has been designed using a novel standard-cell approach called the building-cell methodology, which leads to a high integrated density of 25000 devices in a 7*7-mm/sup 2/ chip. The BL consists of 3376 logic gates and a 76-b dual-port register file (RF), which has as a new function a multi-address read/write operation for efficient data transfer. The BL was fabricated by a 0.8- mu m WN/sub x/ gate LDD (lightly doped drain) MESFET process, and fully functionally tested with an average yield of 20%. A 10-ns cycle time operation was achieved with a power dissipation of 5.5 W. This result reveals that a network with 256 GaAs BLs and 64 processor units can realize a maximum data transfer rate of 2.56 Gbyte/s. >

An ultrahigh-speed 8-b multiplexer (MUX) and demultiplexer (DMUX) chip set has been developed for the synchronous optical network (SONET) next-generation optical-fiber communication systems, which will require data bit rates of about 10 Gb/s. These ICs were designed using three novel concepts: a tree-type architecture giving reliable operation, a dynamic divider with a wide operating range, and a 50- Omega on-chip transmission line with high-speed pulse propagation. They were fabricated using a 0.5- mu m WN/sub x/-gate GaAs MESFET process. The DMUX and MUX operated at up to 10.4 and 11.4 GHz, respectively, both with an adequate phase margin of more than 230 degrees . >

A 2K-gate DCFL GaAs gate array has been successfully fabricated with a WN gate self-alignment GaAs MESFET process. Chip size was 4.59 mm/spl times/4.73 mm. A basic cell, consisting of one DFET and three EFETs, can be programmed as an inverter or a two or three-INPUT NOR gate by personalizing with first- and second-level interconnection and via hole masks. The I/O buffer was implemented with a large DCFL push-pull circuit. The unloaded propagation delay time was 42 ps/gate at a power dissipation of 0.5 mW/gate. The increases in delay time due to various loading capacitance were 11-ps/fan-in. 16-ps/fan-out, 59-ps/1-mm interconnection and 0.95 ps/crossover (area: 2 /spl mu/m/spl times/3 /spl mu/m). An 8/spl times/8-bit parallel multiplier was fabricated on this gate-array chip. A multiplication time of 8.5 ns was achieved at a power dissipation of about 400 mW including I/O buffers.