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This paper presents a 1.5-GS/s 6-bit single-channel loop-unrolled successive approximation register (SAR) analog-to-digital converter (ADC) using speculative capacitive DAC (CDAC) switching control technique. The proposed SAR ADC achieves a high sampling rate by eliminating additional delays in typical loop-unrolled SAR ADCs related to settling time constraints in their CDACs. Specifically, the CDACs are duplicated and controlled in speculative ways so that the CDAC outputs passage to their next values before completing the regeneration operation of comparators, thereby improving timing constraints for successive approximations. The switching power overhead from the CDAC speculation is mitigated by introducing an energy-efficient CDAC control technique that produces desired voltage transients with minimal power overheads. The prototype of the proposed SAR ADC is fabricated in a 28-nm CMOS technology and occupies an active area of 0.0038-mm2. The design consumes 5.8 mW from a 1.2-V supply. The ADC achieves 1.5-GS/s sampling frequency with a 31-dB SNDR at a low input frequency and a 28.6 dB at the Nyquist frequency without applying any offset calibration techniques, achieving the highest sampling frequency among the 6-bit single-channel loop-unrolled SAR ADCs reported. [ABSTRACT FROM AUTHOR]

This paper presents a 7-bit digital to phase converter (DPC) for high speed clock and data recovery (CDR) applications which is capable of generating multi-phase clocks at 7-GHz frequency. Fabricated in a standard 65-nm CMOS technology, the design introduces a modified phase interpolator (PI) and a quadrature phase corrector (QPC) to reduce the effect of the circuit imperfections on the DPC’s resolution and linearity. Employing a 14-GHz quadrature reference clock, the DPC achieves DNL/INL of 0.7/6 LSB respectively while consuming 40.5 mW power from 1.05 V supply. [ABSTRACT FROM AUTHOR]

Computing systems working in harsh environment is prone to suffer from radiation-induced soft errors; for example, Single Event Upsets (SEUs) and Single Event Transients (SETs) are the major reliability issue for circuits fabricated with nanoscale technology nodes. In this paper, we proposed a low-cost SET and SEU error tolerant flip-flop (SETU-TOFF). Based on the traditional flip-flop, two high-level sensitive redundant latches are added to latch the input data at different times, and a voter is designed for the correct output. It removes the timing overhead of temporal redundancy from the critical path of the systems. Comparing with the existing designs presented in literatures, SETU-TOFF has comprehensive fault tolerant capability with lower overheads; moreover, it doesn’t increase significant latency of the flip-flops. We use the SETU-TOFF cells to protect a pipeline of an OpenRISC microprocessor. Fault injection simulations show that SETU-TOFF can achieve 100% protection for the pipeline with negligible performance loss; additionally, it can detect and correct errors in real time without extra system control logic and clocks for errors recovery. [ABSTRACT FROM AUTHOR]

In the Mesochronous Pipeline (MP), the clock period is the maximal of differences between the maximum/minimum delays of all stages. This value is less than the maximum delay between the memory elements, so MP is operating faster than the conventional pipeline (CP). To take full advantages of MP, in this paper, Automated Mesochronous Pipeline Scheduler (AMPS) for high performance digital circuits, is proposed which provides all allowed partitioning options generated by register allocation procedures obtained with varying maximum delay differences of stages. This allows a designer to select from design space produced by AMPS based on the desired specification. Unlike the traditional MP, AMPS utilizes automated scripts to extract the timing characteristics of the synchronizers and gates. This enables a designer to explore trade-offs between latency, power, and frequency. To evaluate our toolset, an 8-bit Carry Increment Adder (CIA), a 4-bit Binary-Coded Decimal (BCD) adder, a 4-bit ALU, and a set of circuits from ISCAS85 and ISCAS89 benchmarks are considered. All circuit level simulations are performed in the 65nm CMOS standard technology node. AMPS improves the frequency for its best solutions about 127.94% (on average) in comparison to the conventional pipeline scheme. [ABSTRACT FROM AUTHOR]

This paper investigates the metastability of true single-phase clock (TSPC) D flip flops (DFFs) and its impact on the resolution of Vernier time-to-digital converters (TDCs). The mechanisms of the metastability of TSPC DFFs are investigated and the analytical expressions of setup time and hold time are obtained. A shunt capacitor technique capable of reducing setup time and hold time to zero with no power and delay penalty is proposed. The impact of PVT (process, voltage, temperature) on the effectiveness of the proposed technique is quantified using simulation. Vernier TDCs, both right-shifting and left-shifting, with untuned and tuned DFFs are designed in TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM3V3 device models. Simulation results demonstrate TDCs with tuned DFFs enjoy zero conversion error while the right-shifting and left-shifting TDCs with untuned DFFs have 1-bit and 5-bit conversion errors or 11% and 56% error rates, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a low power injection-locked oscillator (ILO)-type clock and data recovery (CDR) in 40 nm CMOS. An efficient “phase reset” scheme is proposed to periodically realign the clock phase to the rising edge of data. The frequency information is extracted by comparing the rising edge of the data and the clock after aligning the phase using a bang-bang phase detector (BBPD). Additionally, a low power injection-locked two-stage ring digitally controlled oscillator (ILDCO) is employed to provide four-phase quadrature clock and significantly reduce the power consumption. Based on the proposed architecture, the fabricated CDR consumes only 5.8 mW from a 0.9 V supply, while being able to extract the clock signal from 6.15 to 10.9 Gb/s input data with a measured jitter tolerance (JTOL) of 0.15 UIpp at the highest frequency, indicating that the CDR meets the OC-192 mask. Furthermore, the proposed CDR demonstrates a substantial improvement in the power efficiency of 0.58 pJ/bit. [ABSTRACT FROM AUTHOR]

Superconducting digital electronics, especially Single Flux Quantum (SFQ), has emerged as a promising beyond-CMOS technology with Josephson junctions (JJ) as the active device. It has the potential to meet the booming demands of lower power consumption and higher operation speeds in the electronics industry and future exascale supercomputing systems. Despite these promises, scaling SFQ circuits remains a serious challenge that motivates the support of multiple SFQ clock domains. Towards this end, this paper analyzes the impact of setup time violations and metastability in SFQ circuits comparing the derived analytical models to their CMOS counterparts. It also proposes new techniques to reduce the average latency in metastability-tolerant SFQ synchronizers, and evaluates their effects on the layout and critical margin of the design. It further extends the proposed model to estimate the Mean Time Between Failure (MTBF) of flip-flop-based synchronizers and shows that their MTBF with the current feature sizes is unaffected by noise, similar to CMOS. Finally, it curve fits this model to simulations using the state-of-the-art SFQ5ee process and shows that a two-flop SFQ synchronizer with a clock frequency of 25 GHz has an estimated MTBF of ~106 years. [ABSTRACT FROM AUTHOR]

This paper presents an analytical method for the performance evaluation of the correlation-based impulse radio (IR) receivers, which detect the data based on synchronizing the received signal with a locally generated template pulse. In this paper, a phase interpolation technique is employed to preserve synchronization accuracy with low power consumption. The analytical method computes the spectral density of jitter at the phase interpolator output, resulting from both flicker and thermal noise components. The analysis considers the aliasing phenomenon due to the sampling of the noise to predict the induced jitter accurately. Bit error rate (BER) of the receiver is also statistically estimated in terms of the induced jitter on the template pulse, the noise effect of the receiver chain, and the template signal level. The proposed estimation procedure is validated by comparing its results with transient noise simulations. It is shown that increasing the template signal range in the correlator and improving the linearity of the phase interpolation transfer curve, at a given power consumption, enhances the receiver sensitivity by 2 and 3.5 dB, respectively. The BER estimation results also reveal that the effect of the template signal jitter on the sensitivity of the correlation-based IR receivers becomes dominant with the increasing input signal level. [ABSTRACT FROM AUTHOR]

Manufacturing process variations and transistor’s aging effects are two major concerns for reliable design of nano-scale digital circuits. Correct functionality of flip-flops (FFs), as one of the most important elements in digital circuits, plays a key role in reliability of modern circuit designs. In this paper, a timing reliability improvement technique is proposed for master-slave FFs considering the impacts of process variations and aging effects. In this technique, the internal circuitry of the FF is restructured in order to improve the reliability by reducing the stress time (i.e. the time of being ON) of the transistors which are stacked in the feedback loop. Using Monte-Carlo based HSPICE simulations, the efficacy of the restructuring-based reliability improvement technique is shown considering various experimental conditions (i.e. different process variation ratios and lifetime values). The experimental results show that, the lifetime reliability of Master-Slave FFs improved by 22% in expense of 3% area overhead, 8% propagation delay absolute change, and 6% absolute power change in the presence of 20% variation ratio and 9 years of operation time. [ABSTRACT FROM AUTHOR]

This paper presents a compact and low-power time-domain CMOS temperature sensor intended for Internet of Things. To eliminate the off-chip reference clock that is commonly needed for time-domain CMOS temperature sensors, a precise on-chip reference clock is designed to measure the temperature-dependent delay generated by an inverter chain with even stages. In the reference clock circuit, a relaxation oscillator showing discharging phases with negative temperature coefficient (TC) is designed, which are compensated by 2 identical inverter-chains with positive-TC delay, resulting in a reference clock with nearly temperature-independent pulse width and period. In addition, a $2^{{\text {nd}}}$ -order hybrid time-voltage delta-sigma ($\Delta \Sigma $) modulator with feedforward path is proposed to quantize the temperature-dependent delay of the main inverter chain, achieving 100-mK resolution only in about 25-ms conversion time. Fabricated in 0.18- $\mu \text{m}$ CMOS, measurement results show that the best (worst)-case temperature accuracy of the clock’s reference time is ±0.015% (±0.055%) and the temperature sensor achieves a maximum inaccuracy of +0.66/−0.73 °C from −20 °C to −80 °C. The prototype occupies 0.45-mm2 chip area and consumes 1.99- $\mu \text{W}$ from a 1.8-V supply at room temperature. [ABSTRACT FROM AUTHOR]

This paper presents an NMOS digital low-dropout regulator (LDO) with fast transient response and ultra-low quiescent current, to provide a tunable power supply for near-threshold voltage computing circuits in internet-of-things (IoT) devices. An LDO with an NMOS power transistor can enjoy the intrinsic fast transient response of the source-follower-like power stage, contributing to the proportional (P) part of the control loop. A shift-register-based digital control serves as an excellent candidate for the integral (I) part of the control loop. In addition, we propose a NAND-gate-based high-pass analog path (NAP) as the derivative (D) part of the loop, making the whole control scheme a complete PID control, therefore, achieving a fast transient response. We fabricated two versions of the prototype chip, one with a 35 pF on-chip load capacitor and a fast-transient on-chip load, and the other with no load capacitor, in 28-nm CMOS. The proposed NMOS digital LDO with NAP can handle the load transient of 160 mA/ns with 810-nA quiescent current, achieving 117-mV voltage undershoot. With the proposed techniques, we can achieve nearly two orders of better FoM when comparing it to the state-of-the-art works. [ABSTRACT FROM AUTHOR]

The use of digital pulse-width modulators (DPWMs) as controllers for dc–dc converters is becoming more and more popular, due to the lower sensitivity to process variations, programmability, and easiness to translate complex control algorithm in digital architecture. DPWMs require high resolution to avoid limit cycling. Moreover, especially in high-frequency switching power converters, the reduction of the electromagnetic interference (EMI) is of primary importance. A novel DPWM circuit is proposed in this paper. The circuit uses only standard cells, easing portability to new technological nodes. The DPWM includes a coarse delay stage, based on an enhanced counter-based architecture, which is able to modulate both the frequency and duty cycle. As a result, the proposed DPWM supports spread-spectrum modulation, with arbitrary modulation law, to reduce the EMI. The DPWM also includes a fine delay stage that employs digitally controlled NAND-based delay lines with excellent linearity and resolution. A measurement unit is used to compensate at run time, the process, voltage, and temperature variations. The circuit has been fabricated in low-cost UMC 130-nm CMOS technology and is fit in a 44-pin package. The chip can generate spread-spectrum pulse-width waveforms up to 10 MHz. Measurement of the conducted EMI in buck dc–dc converter is reported in this paper. [ABSTRACT FROM AUTHOR]

This paper presents a novel technique for single slope analog to digital converter (SSADC) to suppress the row-wise noise in CMOS image sensor. A sample switch is used in the current-steering DAC to reduce the noise introduced by bias circuits, which will deteriorate the characteristic of uniformity in the row direction. The sample switch can fix the voltage which biases the current source in the current-steering DAC when generating a ramp to avoid the ramp fluctuation in the time domain. The digital correlated double sampling is used to reduce the non-uniformity in column-level ADCs. The CMOS image sensor prototype is fabricated in 110nm 1P3M process. The 10-bit SSADC achieves DNL of −0.20 / +0.15 LSB and INL of −1.35 / +0.91 LSB at a sampling frequency of 29.2 KHz. It is proved that the row-wise noise is reduced from $764~\mu {\mathrm {V}}_{\text {rms}}$ to 163 $\mu {\mathrm {V}}_{\text {rms}}$ at a frame rate of 228 fps using the proposed sample switch structure. The prototype photos taken by the sensor show that the row-wise noise is reduced under the low-illumination circumstance effectively. [ABSTRACT FROM AUTHOR]

In this paper, a hybrid architecture of digital pulse width modulator (DPWM) with high resolution is proposed. Furthermore, to enhance linearity performance, the critical path is optimized by a novel synchronous phase-shifted circuit. A carry chain-based delay line is also utilized to improve time resolution. A 14-bit DPWM with the proposed architecture is implemented and tested by Altera Cyclone IV FPGA. The experiment results show that the DPWM achieves high linearity, where $R^{2}$ maintains over 0.9994. Besides, the output duty cycle covers a wide range from 0.9429% to 99.2% and the time resolution is about 41.3ps. [ABSTRACT FROM AUTHOR]

This paper proposes an ultra-compact 4 to 10-Gb/s 5-tap current-mode transmitter to realize the sub 1-UI fractional de-emphasis (DE) using a hybrid delay line, which is alternatively controlled by the voltage bias and clock. It exhibits the scalability between the clocked 0.5-UI and 1-UI DEs and data rate. The sub-1-UI DE provides wide tunability of the data amplitude and delay to compensate different channel losses between the $1^{st}$ and $2^{nd}$ Nyquist frequencies while effectively compensating the high-frequency portion of the pseudo-random binary sequence (PRBS) spectrum for data jitter improvement. Additional techniques are a two-step current-summing scheme, namely, two-step DE in the data path, and active inductors in both the data and clock paths to enhance the internal bandwidth without the need for passive inductors. In addition, we present an analytical model for predicting data-dependent jitter (DDJ) based on a generic system’s step response, derive the exact closed-form DDJ expression of DE, and verify its validity by mean of circuit simulation. Prototyped in 65-nm CMOS technology, it achieves a figure-of-merit of 4.6 mW/Gb/s and an output jitter of 10.8 pspp at 10 Gb/s under a PRBS $2^{31}-1$ pattern. The data eyes measure 0.62-UI-horizontal and 19.5%-vertical openings after −20-dB channel loss. The die area is 0.0071 mm2. [ABSTRACT FROM AUTHOR]

In this paper, we propose and analyze a pulse-output digital-to-frequency converter (DFC) generating square waves, which uses a digital-to-time converter (DTC) to correct the spurious tones (spurs) in the output spectrum. We focus on high-level architectural potential, discuss the design features of a DTC suitable for the proposed system, and explore possibilities and limits of this approach in terms of cleanness of the output spectrum. The behavioral model simulations confirm the theoretical analysis presented. Besides an analytical description of the output spurs, we derive a closed-form estimate of the worst-case spur, which leads to a simple design equation. This is useful to determine the DTC requirements [number of bits and integral non-linearity (INL)], given a certain spurious-free dynamic range (SFDR) target. We show that the maximum spur strength (in dBc) depends exclusively on the ratio between the output frequency and the clock frequency and the DTC features (number of bits, INL, and other impairments) and increases with the ratio by 6 dB/octave. [ABSTRACT FROM AUTHOR]

This paper presents a low power and low noise quadrature RC oscillator based on a frequency locked loop. Voltage swing control of each of the two sub-oscillators reduces the effect of 1/f noise on the accumulated jitter. In addition, the use of quadrature phases greatly relieves timing constraints of sampling operations and helps the reduction of power consumption. With a discrete-time modeling of the quadrature oscillator, noise analysis is also provided for quantitative estimation of the circuit-driven effects on the phase noise. The proposed oscillator is fabricated using 180-nm CMOS process in an active area of 0.058mm2. The measurement shows a period jitter of 0.047% and a standard deviation of 0.94% in untrimmed frequency (444.9kHz) in a wafer. The oscillator achieves a figure-of-merit of 155 dBc/Hz at 100 Hz offset frequency. [ABSTRACT FROM AUTHOR]

In this paper, a design method for high-order delay-lock loops (DLLs) is presented and verified through simulations and physical experiments. The general approach is based on selecting the closed-loop transfer function of the DLL, together with identifying the coefficients of the phase-detector and voltage-controlled delay line, and subsequently, solving for parameters of the loop filter of the DLL. Past DLL design approaches relied more on establishing a desired phase margin requirement than attempting to establish a desired input–output behavior. This limited the realization of DLLs to second order; largely a result of the complicated mathematics that arise. As the method proposed in this paper is based on selecting a desired closed-loop transfer function, the issues of stability or phase margin never come to the forefront. This paper will show how a DLL can be designed to achieve a fast-settling-zero-overshoot step response with large jitter-rejection capabilities. The method is simple and easy to execute. No optimization or iteration is necessary. The method is similar to the methods used to design active-RC filter circuits. A fully programmable experimental prototype involving a custom IC implemented in a 130-nm IBM CMOS process was constructed. DLLs with orders ranging from second to eighth will be investigated. [ABSTRACT FROM PUBLISHER]

A physical design methodology is presented to synchronize digital application specific integrated circuit (ASIC) designs by a resonant rotary clock network. One novelty of the proposed RotaSYN flow is that the ASIC products of RotaSYN can operate at previously unattainable (relatively) low-frequency ranges of hundreds of megahertz. The dynamic resonant frequency divider is used to implement the low-frequency operation; and low in comparison to the norm of gigahertz-range of operation for resonant clocking reported in this paper. In SPICE-based simulations, the efficacy of the proposed flow and novel algorithms in RotaSYN is demonstrated using performance metrics of the wirelength, skew, and power on international symposium on physical design-10 clock benchmark circuits. In addition, RotaSYN is compared to three publicly available industrial designs that include the ARM Cortex M0 against equivalent clocks generated with a traditional phase locked loop (PLL) and distributed with an industrial clock tree synthesis tool flow. The RotaSYN methodology is implemented at three different target frequencies of 880 MHz, 500 MHz, and 220 MHz for the industrial designs. SPICE simulations show an average of 29% power savings for the industrial designs overall, solely thanks to 66% power savings on the clock generation and distribution networks, operating at a frequency of 880 MHz on comparison to the PLL-based design with a clock tree synthesized with an industrial EDA tool. [ABSTRACT FROM AUTHOR]

This paper presents an all-digital bandpass $\Delta\Sigma $ time-to-digital converter (BP) $\Delta \Sigma $ TDC) for IF data conversion. The proposed TDC is based on a second-order resonator implemented by a cascade of two time-mode lossless discrete integrators (LDI), and a digital-to-time converter (DTC) in a feedback loop. The DTC is based on a new topology of double-edge voltage-controlled delay unit. The proposed TDC achieves bandpass quantization noise shaping and it does not require any complex calibration circuit to compensate for timing errors. To realize the time-mode LDI-based resonator, time-latches with some digital gates are employed. Moreover, a direct feed-forward compensation is utilized in the TDC to attain high signal-to-noise and distortion ratio (SNDR) by reducing the internal time-mode swing, thus relaxing the speed and area requirements on digital circuits leading to low-voltage operation. The prototype BP $\Delta \Sigma $ TDC achieves a 39.5-dB peak SNDR over a 0.2 MHz signal bandwidth at 42.8 MS/s while consuming less than 5 mW in a 1.2 V IBM 130-nm CMOS process. The proposed TDC is highly digital and occupies a core area of only 0.048 mm2. [ABSTRACT FROM AUTHOR]

Speed-path debugging at the post-silicon stage due to timing variations is a challenging problem in designing high-performance digital circuits. In this paper, we propose an efficient and scalable method for automatic speed-path debugging which is based on quantified Boolean formulas (QBF) to detect multiple erroneous paths when taking into account the timing variations. We have proposed new gate-level timing variation and path slowdown models which enable us to formulate such a debugging problem as a QBF problem. The results on the ISCAS’85 and ISCAS’89 benchmarks show that our method enjoys on average 52.4% decrease in the size model, and 63.1% decrease in debugging time in comparison with existing methods. Moreover in situations where existing methods due to the size explosion of abundant copies cannot be applied, the proposed method detects erroneous gates in a reasonable runtime. [ABSTRACT FROM AUTHOR]

To mitigate the excess timing margin in conventional digital integrated circuit design, resilient circuits were proposed. The current techniques however either have a large error-detecting register or have difficulty in wide-voltage-range (down to near-threshold) operation. In this paper, we propose a light-weight holosymmetrical transition detector (HTD) that can work reliably at near-threshold to normal VDD with fast response time. Combined with a conventional latch, the HTD-latch is used to replace the end point flip-flop for timing error prediction with an area overhead of only 9.5% over a conventional flip-flop. Besides, we optimize the speculation window and design an adaptive duty-cycle control mechanism to reduce the short-path padding overhead in a resilient circuit. In addition, with voltage scaling, we keep the system working at the point before the first failure by using local detection and global clock gating, which needs neither architectural circuit change nor complicated error recovery mechanism. We apply the above-mentioned three techniques on an eighth-order filter test chip in a 40-nm CMOS process. The measurement results demonstrate that the proposed HTD can work robustly at 0.474–1.1 V. With 4.37% area overhead in total, the proposed resilient technique improves performance by 179.31%/28.2% and energy efficiency by 45.6%/28.1% in a near- $V_{\mathrm {TH}}$ (0.474 V)/super- $V_{\mathrm {TH}}$ (1.1 V) operation, as compared with the baseline design. Therefore, our proposed HTD-based resilient technique can improve the energy efficiency of circuits by almost eliminating all the timing margins. [ABSTRACT FROM AUTHOR]

For wireline transmitters delivering a high-speed multi-level signal, such as pulse-amplitude-modulation-4 or duobinary, a high-performance multiplexer (MUX) is critical to serialize the low-speed parallel data into one full-speed output. To enhance the power efficiency and data eye’s opening, this paper proposes a universal 2-to-1 MUX, featuring a cross-quadrature clocking technique to enlarge the timing margin, and a simplified three-latch topology without delay buffers to boost the internal bandwidth (BW). The MUX ratios are extendable to 4-to-2 and 4-to-1, and their benefits are exemplified via a duobinary-signal transmitter. It further includes an output driver unifying the MUX-and-SUM operation, a BW-extended single-to-differential converter, and an active-inductor-embedded clock buffer for swing enhancement. Also, a predictive method for estimating the duobinary-signal data-dependent jitter according to the load capacitance of the output driver is developed. Fabricated in 65-nm CMOS, the transmitter exhibits a figure-of-merit of 1.3 mW/Gb/s at 36 Gb/s, while occupying a compact die area of 0.037 mm2. [ABSTRACT FROM AUTHOR]

This paper presents a single-chip impulse-radio (IR) radar transceiver that utilizes a novel continuous sweep-clock generator. While requiring low power and small area, the proposed clock generator enables a versatile IR radar operation with millimeter resolution. The radar detection range and update rate are adjustable by an on-chip delay command circuit or by an external master. The IR radar transceiver, working with transmission and reception clocks, incorporates a spectrum adjustable transmitter and a wide-band sampling receiver. The recovered echo pulses from the radar are distinguishable in an expanded time scale. For the first time, generalized analyses on the radar range for time-expansion IR radars are established. The single chip radar transceiver is fabricated in a 130-nm CMOS technology occupying a chip area of 1.0 mm2. The measurements show that the echo pulses are recovered with a millimeter range resolution, while dissipating 30 mW. Respiration motions are successfully captured with the prototype radar. [ABSTRACT FROM AUTHOR]

A 2.5–5.6 GHz low-phase-noise subharmonically injection-locked sub-sampling all-digital phase-locked loop with a dual-edge complementary switched injection technique is presented. While previously reported injection-locked phase-locked loops (ILPLLs) require additional circuitry for resolving a phase alignment mismatch between the PLL loop and injection path, the presented ILPLL exhibits a simplified architecture owing to the proposed injection technique and sub-sampling bang-bang phase detector (SSBBPD). Because the proposed injection technique exploits dual-edge injection, we analyze the performance impact of dual-edge injection when inaccurate injection timing occurs. This paper also offers an analysis of the injection technique based on the charge transfer and derives the realignment factor of the injection. With the proposed injection technique and the direct connection of the digitally controlled oscillator (DCO) clock to the SSBBPD, the timing mismatch between the PLL loop and injection path becomes insensitive to voltage and temperature drift. The proposed ILPLL prototype is fabricated in a 65-nm CMOS process and achieves a 168-fs integrated rms jitter over 1 kHz to 40 MHz at a 5-GHz output frequency with 156.25-MHz reference clock while consuming 15.4 mW with an active area of 0.06 mm2. [ABSTRACT FROM AUTHOR]

This paper demonstrates a completely on-chip implementation of expansion and compression of continuous-time, wideband, analog pulses. The input pulse is fed to a continuous-time filter whose delay exceeds the pulse duration. Once the pulse is completely inside the filter, it is stored in the form of the filter’s state-variables, which can completely reconstruct the pulse. Instantaneously decreasing or increasing the filter’s bandwidth at this instant results in the output pulse being expanded or compressed, respectively, compared with when the bandwidth is unchanged. A 1.6 mm2, 370 mW, 0.13 $\mu \text{m}$ prototype has a delay filter whose bandwidth can be switched between 870 and 472 MHz. It achieves $1.8\times $ pulse expansion and $1.7\times $ pulse compression with an rms error which is 33 dB below the peak-peak pulse amplitude. [ABSTRACT FROM AUTHOR]

In this paper, a dual-mode standing-rotary traveling-wave oscillator (S-RTWO) is analyzed. In order to force the conventional RTWO to oscillate in the standing wave mode, an ideal switch is used for shorting two differential nodes of the RTWO circuit. The closed-form equations, which describe the transitions of phases between the standing wave mode and the rotary traveling wave mode of the oscillator, are derived, and the delays of transitions between two modes of the oscillator are extracted by using these equations. Besides, the oscillation start-up delay is analyzed, and the closed-form equation for the start-up delay is obtained in terms of circuit elements. Finally, our theoretical results are compared with appropriate and accurate simulations to evaluate the validity of the delays analysis and the accuracy of the closed-form equations. Simulations of the dual-mode oscillator have been done in a 0.18- $\mu \text{m}$ CMOS technology with a 1.8-V supply voltage. The evaluations show very good agreement between analytical equations and simulation results, and confirm the validity and accuracy of the delays analysis. [ABSTRACT FROM AUTHOR]

A variable latency adder (VLA) reduces average addition time by using speculation: the exact arithmetic function is replaced by an approximated one, that is faster and gives correct results most of the times. When speculation fails, an error detection and correction circuit gives the correct result in the following clock cycle. Previous papers investigate VLAs based on Kogge-Stone, Han-Carlson or carry select topologies, speculating that carry propagation involves only a few consecutive bits. In several applications using 2's complement representation, however, operands have a Gaussian distribution and a nontrivial portion of carry chains can be as long as the adder size. In this paper we propose five novel VLA architectures, based on Brent-Kung, Ladner-Fisher, Sklansky, Hybrid Han-Carlson, and Carry increment parallel-prefix topologies. Moreover, we present a new efficient error detection and correction technique, that makes proposed VLAs suitable for applications using 2's complement representation. In order to investigate VLAs performances, proposed architectures have been synthesized using the UMC 65 nm library, for operand lengths ranging from 32 to 128 bits. Obtained results show that proposed VLAs outperform previous speculative architectures and standard (non-speculative) adders when high-speed is required. [ABSTRACT FROM PUBLISHER]

This paper deals with the analysis of the convergence properties of the max-consensus protocol in presence of asynchronous updates and bounded time delays on directed static networks. The work is motivated by real-world applications in distributed decision-making systems, for which max-consensus is an effective paradigm. The main result of this paper is that the strongly connectedness of the directed communication network is a sufficient condition for the asynchronous max-consensus protocol to let a distributed system converge in finite time. Implementation issues are also taken into account, by complementing the theoretical analysis with the definition of a mechanism to detect convergence in a distributed fashion. Finally, a numerical example is given, highlighting both the issues related to the failure of synchronous protocols applied to asynchronous settings and the effectiveness of the proposed asynchronous framework. [ABSTRACT FROM AUTHOR]

This paper presents simple but accurate expressions for the noise components caused by clock jitter, in the output signal of self-oscillating sigma delta modulators (SOSDM). Contrary to conventional continuous time sigma delta modulators (CTSDM), the SOSDM's loop contains a strong oscillation, whose attribution to the system's jitter caused noise has not previously been explored. In this paper, the SOSDM system is modeled, and the effect of the self oscillation, the input signal and the quantization noise on the jitter caused noise in the output signal, is calculated. Results are confirmed by system level simulations. [ABSTRACT FROM AUTHOR]

This paper presents a PLL supporting diverse low-power clocking needs including wide input (6–200 MHz) and output (0.15–5 GHz) frequency ranges and SSC operation. Fabricated in 14nm FinFET CMOS, a low-power switched-cap loop filter is employed to enable high −3dB PLL bandwidth (>40% of $f_{\mathrm{ REF}}=19.2$ MHz), and the proposed reference current generator (IrefGen) provides accurate current with <4% tolerance without the need for external components or on-chip precision resistors. IrefGen decouples PLL loop dynamics from feedback divide ratio and provides immunity to systematic capacitor variation. Power gating of switched-cap loop filter’s bias circuits results in more than 10% PLL total power savings. The PLL achieves 1.6-ps integrated RMS jitter at 4 GHz using 100-MHz reference while consuming 2.6 mW from 0.95 V. The PLL performance satisfies the stringent PCIe Gen2/3 jitter specifications without resorting to inductors. [ABSTRACT FROM AUTHOR]

Semiconductor technologies bring the possibility of embedding billions of components in a chip, allowing the design of complex integrated circuits. However, such levels of integration are not free and delay uncertainties grow steadily, which is increasingly challenging. Quasi-delay-insensitive (QDI) design promises to cope with such challenges, being less timing constrained than synchronous or bundled-data designs. However, two barriers to its wider adoption are: 1) missing methods to automatically implement QDI circuits and 2) enabling QDI semi-custom design. This paper proposes a new QDI design method that extends the null convention logic (NCL) asynchronous template. Also, it describes an associated semi-custom design flow for the extended template, which uses conventional electronic design automation tools to synthesize QDI circuits down to layout. The method enables using the full power of synthesis and optimization commercial tools. Illustrating this, the ISCAS85 benchmarks take 35%–43% less gates to implement, compared with conventional, pattern-based NCL design. A comparison with the Uncle tool provides indication that the proposed method is indeed a flexible and powerful approach to design asynchronous QDI circuits. Lastly, 16-b multiplier designed with the method until the layout level exhibits 170%–240% larger operations/Watt compared with an equivalent NCL design, and an almost 400% better operations/mm2 figure. [ABSTRACT FROM PUBLISHER]

Nowadays, the high power density and the process, voltage, and temperature variations became the most critical issues that limit the performance of the digital integrated circuits because of the continuous scaling of the fabrication technology. Dynamic voltage and frequency scaling technique is used to reduce the power consumption while different error recovery techniques are used to tolerate the process, voltage, and temperature variations. These techniques reduce the throughput by scaling down the frequency or flushing and restarting the errant pipeline. A resilient microarchitecture is introduced in this paper to tolerate the induced delays generated by the voltage scaling and the process, voltage, and temperature variations. This resilient microarchitecture detects and recovers the induced errors without flushing the pipeline and without scaling down the operating frequency. A resilient 16 b $\times16$ b MAC unit was fabricated using Global Foundry 65-nm technology with 18.26% area overhead and upto $1.65\times $ speedup. At the typical conditions, the maximum frequency of the conventional MAC unit is about 375 MHz while the resilient MAC unit operates correctly at a frequency upto 620 MHz. In case of variations, the resilient MAC unit tolerates induced delays up to 50% of the clock period while keeping its throughput equal to the conventional MAC unit’s maximum throughput. At 375 MHz, the resilient MAC unit is able to scale down the supply voltage from 1.2 to 1 V saving about 29% of the power consumed by the conventional MAC unit. [ABSTRACT FROM PUBLISHER]

The use of a single-bit quantizer in a wideband CT \Delta \Sigma \textM is attractive, as the quantizer can be implemented in a power and area-efficient manner. Unfortunately, 1-bit CT $\Delta \Sigma $ Ms are plagued by a host of difficulties. Clock jitter and quantizer metastability are particularly problematic, and the higher loop filter linearity needed to process the full-scale feedback waveform results in increased power dissipation. The use of a finite impulse response (FIR) feedback DAC is a power efficient way of addressing the challenges above. However, even this technique runs into difficulties at multi-GHz clock rates. This paper introduces the idea of time-interleaved (TI) FIR feedback to enhance the performance of a conventional FIR DAC. A single-bit CT \Delta \Sigma \textM that uses a $2\times $ TI-FIR DAC achieves 67.6/68.8/76 dB SNDR/SNR/DR in a 60 MHz bandwidth. Designed in a low leakage 65 nm CMOS process, the modulator operates at 6 GHz and occupies only 0.07 mm2. Its Walden Figure of Merit is 56.5 fJ/lvl. [ABSTRACT FROM PUBLISHER]

A 1.5–3.3 GHz, 7 mW, all-digital delay-locked loop (ADDLL) designed in a UMC 130-nm CMOS technology is presented in this paper. The proposed ADDLL uses the modified successive approximation register to control a NAND-based coarse delay line, which enables wider operating frequency range and small intrinsic delay. The inverter-based fine delay line is controlled by an XOR-based up/down counter with dead-zone free phase detector to overcome the dead-zone problem of conventional phase detectors. The D-type flip-flops in the phase detector are modified to detect sub-ps level delay difference between the input and output clocks, so that a delay resolution of better than 1 ps is achieved in the proposed design. The combination of both coarse and fine locking processes gives outstanding performance in terms of residual phase difference and output jitter. The overall design occupies 0.0077 mm2 area. The experimental results show that the peak-to-peak and root mean square jitters are 12 and 1.629 ps at 3.3 GHz, respectively, while the input jitter is 2.6 ps peak-to-peak and 612 fs rms. [ABSTRACT FROM PUBLISHER]

The need for higher throughput and lower communication latency in modern networks-on-chip (NoC) has led to low- and high-radix topologies that exploit the speed provided by on-chip wires–after appropriate wire engineering–to transfer flits over longer distances in a single clock cycle. In this paper, motivated by the same principle of fast link traversal, we propose the RapidLink NoC architecture, which exploits said speed to rapidly transfer flits between adjacent routers using double-data-rate (DDR) link traversals. RapidLink is enhanced with novel low-cost DDR elastic buffers that pipeline link traversal (when needed) to multiple flow-controlled half-cycle segments, whereby each segment is driven with data on both the positive and negative edges of the clock. DDR link traversal leads to multiple NoC configurations that can markedly increase network performance without increasing the area/power cost of the NoC relative to state-of-the-art single-data-rate architectures. Extensive cycle-accurate network simulations and hardware implementation results demonstrate the efficiency of RapidLink and its potential as a scalable NoC architecture. [ABSTRACT FROM AUTHOR]

Tolerating timing error due to power supply noise (PSN) in digital circuits can be done with adding voltage margins. Conservative addition of voltage margins leads wastes of power reducing the battery life in Internet of Things (IoT) devices. This paper aims to provide guidelines to avoid over-design due to PSN especially for the low-cost IoT devices. To this end, we first present an accurate time-domain behavioral model of timing slack variation due to PSN accounting for the clock-data compensation. The accuracy of the model is verified against SPICE for complex designs, including AES engine and LEON3 processor. To prove the effectiveness of our model for reducing voltage margin, we utilize our model in standard VLSI design flow for various examples, such as timing slack versus noise frequency analysis, determining optimal value of an on-die capacitor, analyzing the effects of time borrowing technique, and PVT variation simulations. The analysis shows that the model helps reduce pessimism in estimated timing slack. [ABSTRACT FROM PUBLISHER]

Interconnect shielding is used in very large scale integration designs to prevent noise interference from the cross-coupling capacitance between adjacent signals. This paper takes advantage of the shields already present in the design and uses them to tune the propagation delay of the clock signals by space tapering, thus eliminating expensive and process variation sensitive dedicated delay buffers. The problem of obtaining the desired delay at a minimum shielding cost (silicon area) by tapering its spacing from the signal wires is solved. A clock-tree synthesis methodology that uses shields to obtain useful skews at the underlying flip-flops is proposed. The method was tested on an industrial 28-nm memory controller and ARM® processor designs, operated in 800-MHz and 1.6-GHz clock speed, respectively, and confirmed its viability for delivering the required useful skews to flip-flops. About 90% of the useful skew problems could be solved by shielding manipulations. [ABSTRACT FROM PUBLISHER]

In this paper, the impact of variations on single-edge triggered flip-flops (FFs) is evaluated for a wide range of topologies. In particular, this Part II explicitly considers sources of variations such as voltage, temperature and variations induced by the clock network. The effect of variations on the energy and its tradeoff with performance is also investigated. This paper complements the previous Part I, which is focused on process variations and flip-flop timing. From a design perspective, the presented results provide well-defined guidelines for variation-aware selection of the flip-flop topologies, and for early budgeting of variations before detailed circuit design. Results are put into the technology scaling perspective through comparison of results at 65 and 28 nm. The results show that the technology scaling does not affect either the main findings of this analysis or the ranking of the considered topologies. [ABSTRACT FROM AUTHOR]

We present a low-power indirect time-of-flight (iTOF) image sensor with fixed depth noise compensation and dual-mode imaging for depth dynamic range (DDR) enhancement. To reduce the power consumption from high-frequency pixel modulation, a TX driver with a single-sided clock chain is employed in the sensor. The inherent phase delay of the clock chain and the delay of the row bus are measured using row-parallel and column-parallel time-to-digital converters (TDCs) to compensate for the column and row fixed depth noise (FDN). To achieve a wide depth dynamic range (WDDR), the reconfigurable pixels and column circuits support dual-mode: short-range (SR) and long-range (LR) modes. A WDDR image is generated in a single frame through the mixed reconfiguration of the pixel array and interpolation. In addition, the temporal noise is suppressed without a significant time budget through a fast multiple sampling (FMS) scheme with 10b successive approximation register (SAR) analog-to-digital (ADCs). A prototype iTOF image sensor was fabricated using a 110 nm frontside illumination (FSI) CMOS image sensor (CIS) process and fully characterized. The sensor achieved a DDR of 4 m (0.7 to 4.7 m) with less than 1.7% nonlinearity and 0.9% depth noise. The FDN was suppressed to less than 2.1 cm at a low power consumption below 70 mW through the proposed compensation scheme using row and column TDCs. The temporal noise was only 0.48 mV $_{\mathbf {rms}}$ owing to the FMS. [ABSTRACT FROM AUTHOR]

Pulsed latches are gaining increased visibility in low-power ASIC designs. They provide an alternative sequential element with high performance and low area and power consumption, taking advantage of both latch and flip-flop features. While the circuit reliability and robustness against different process, voltage, and temperature variations are considered as critical issues with current technologies, no significant reliability study was proposed for pulsed latch circuits. In this paper, we present a study on the effect of different PVT variations on the behavior of pulsed latches, considering the effect on both the pulser and the latch. In addition, two novel design approaches are presented to enhance the reliability of pulsed latch circuits, while keeping their main advantages of high performance, low power, and small area. Experiments performed using Synopsys 28nm PDK demonstrate the ability of the proposed approaches to keep the same reliability level at different supply voltages and temperatures in the presence of process variations, with a very small area overhead of around 3%. The two proposed designs have negligible power overhead when running at nominal supply voltage, and they have higher yield per unit power when compared with the traditional design at different voltages and temperatures. [ABSTRACT FROM AUTHOR]

Bias phenomenon has been a ubiquitous problem in the designs of digital True Random Number Generator (TRNG). Circuit performance can be improved with some auxiliary modules such as analog circuits and post-processing components, which usually involve the compromising of cost, compatibility, throughput, and security as well. In some cases only sub-optimal designs can be achieved. In this paper, by utilizing the diverse timing characteristics of different initial states, a staged-running Self-timed Ring (STR) architecture, which is able to suppress the degree of bias, is proposed. The proposed architecture is compared with some conventional free-running architectures using a Xilinx Zynq-7000 Field Programmable Gate Array (FPGA) platform for a throughput of 100 Mbps. With the increase of the ring size, the bias degree of the newly proposed structure is within a negligible level of less than 1%; whereas those of the conventional architectures can exceed 10%. Statistical tests were also conducted and the results show that the quality of randomness rises as the complexity in initial-state mapping and the ring nodes of the proposed structure increases. The test passes the National Institute of Standards and Technology (NIST) test suite with high p-values. [ABSTRACT FROM PUBLISHER]

Dynamic flip-flop conversion (DFFC) is a time borrowing method for improving the performance of digital circuits. Existing types of DFFC [11], [12] suffer from successive critical and critical feedback paths that are frequently seen in digital circuits. Moreover, they are unable to increase the performance of the designs with short sequential depth. In this paper, we introduce a hybrid technique which utilizes DFFC together with a dynamic clock stretching mechanism. Our technique is able to mitigate the problems of successive critical and critical feedback path structures even in the presence of process variations. The results show that our hybrid technique is able to increase the performance of some ITC'99 and ISCAS'89 benchmarks by 24.4% on average while DFFC Type C increases the performance only by 8.4% on average. Furthermore, we have shown that our hybrid technique is able to tolerate process variations, 18% power supply variation, and 100 °C temperature variations, 27.3%, 16.4%, and 13.3% better than the state-of-the-art methods on average, respectively. [ABSTRACT FROM PUBLISHER]

This paper introduces an adaptive CMOS impulse-radio ultra-wideband (IR-UWB) range finder with scalable resolution for localization applications and presents a brief demonstration of its operation. The distance resolution of the proposed range finder can be adapted to the ranging environment using a two-step time-to-digital converter (TDC) with scalable delay cells. Using the scalable time resolution of the TDC, the proposed range finder can control its maximum detectable distance and range resolution without any change in hardware. The proposed CMOS IR-UWB range finder has been implemented with a 0.11- \mu\textm process; the effective areas of the transmitter and receiver are 0.065 mm2 and 0.27 mm2, respectively. The range finder has a range 8 m, with 2.9 mm scalable resolution. The power consumptions of the transmitter and receiver are 1.5 mW and 42 mW, respectively. [ABSTRACT FROM PUBLISHER]

This paper presents a dynamic timing control technique to prevent timing errors in a pipeline under variations. Timing errors in a pipeline are prevented by borrowing time from the following stage and resolving the borrowed time by stretching the next clock cycle. This paper analyzes the operating principles of the proposed technique; presents the design of the required circuit components; and demonstrates its operation through fabrication and measurement of a prototype test-chip designed in an 180 nm CMOS process. The measurement results demonstrate that a system employing the dynamic timing control technique can operate in a wider frequency and voltage range. [ABSTRACT FROM AUTHOR]

This paper presents comprehensive analyses of power-performance tradeoffs in current-mode logic (CML)-based transmitters via equation-based optimization and provides practical design guidelines that can help achieving optimum power efficiency. An accurate equation-based optimization framework was developed for this purpose, and using this framework, key circuit-level design parameters were found with specific design specifications and process technologies. The proposed optimization framework can determine optimum clock edge-rate (i.e., ratio of rise/fall time to clock period) and inter-stage voltage swings that enable significant power savings without affecting performance. Various transmitter design tradeoffs were analyzed for 45-nm, 65-nm, and 90-nm technologies considering data rate, clock edge-rate, and inter-stage swing optimization. Based on the analysis results, we determined the most energy-efficient data rate that can be achieved with acceptable power overhead for each technology node. Also, we identified the optimal clock edge-rate and inter-stage voltage swings in CML gates that achieved minimum transmitter power dissipation. Our analysis results indicate that, when properly optimized, overall transmitter power consumption can be reduced by up to 43% with inter-stage swing optimization with all other design constraints held constant. [ABSTRACT FROM AUTHOR]

Razor-based circuits can run faster or at a lower voltage than those designed to work at the worst case corner. However, all known implementations are prone to failures due to the non-deterministic timing behavior introduced by metastability, even in the case where sufficient time is left for resolution. This paper analyzes the causes why Razor-based circuits fail and proposes a new scheme combining the Razor principle with stoppable clocks in a GALS setting. This scheme avoids any timing failure due to metastability and does not require any checkpointing or pipeline restarting logic, other than the usual auxiliary latch to store valid data. The experiments show how the Razor principle can be extended to any generic logic circuit, and not just to microprocessors with sophisticated pipeline flush/recovery mechanisms. In this way, the performance/power benefits of Razor can be adopted without the complex architectural changes required by the various Razor schemes in the literature. [ABSTRACT FROM AUTHOR]

In this paper, split into Part I and II, the impact of variations on single-edge triggered flip-flops (FFs) is comparatively evaluated across a wide range of state-of-the-art topologies. The analysis explicitly considers fundamental sources of variations such as process/voltage/temperature (PVT), as well as the clock network (clock slope variations). For each topology, the variations of performance, robustness against hold violations, energy and leakage are statistically evaluated and compared. The impact of layout parasitics is explicitly included in the circuit design loop. The presented results provide well-defined guidelines for variation-aware selection of the flip-flop topologies, and estimates for early budgeting of variations before detailed circuit design. Also, the analysis enables a deeper understanding of the sensitivity to variations of existing topologies across a wide range of sizes and loads. In particular, this Part I introduces the methodology, the targeted flip-flop topologies and investigates the impact of process variations on flip-flop timing. [ABSTRACT FROM PUBLISHER]

An accurate performance evaluation of jitter-power figure-of-merit (FOM) for multiplying delay-locked loop (MDLL) is presented. For a typical MDLL employing a single-ended multiplying-delay ring voltage-controlled oscillator (MDVCO), it can be tuned via the capacitive loads to uphold a constant normalized phase noise (PN) across different frequencies for better jitter-power performance. Linear approximation and z-domain PN model are utilized to simplify the analysis with excellent agreement between the time-domain simulation and z-domain approximation. The influences of the asymmetric waveform, flicker noise corner, frequency error and reference noise are also discussed and then ignored based on the reasonable approximation. Under a given process, reference clock frequency and supply voltage, the ideal FOM can be derived theoretically. Based on these insights, the predicted FOM can be the benchmark metric in the design of MDLL for the possible best jitter-power performance. [ABSTRACT FROM AUTHOR]

This paper presents the design of a continuous-time \Delta\Sigma modulator (CTDSM) to be used in an ultrasound beamformer for biomedical imaging. To achieve better resolution, the prototype modulator operates at 1.2 GHz. It incorporates a digital excess loop delay (ELD) compensation to replace the active adder in front of the internal quantizer. A digitally controlled reference-switching matrix, combined with the data-weighted averaging (DWA) technique, results in a delay-free feedback path. A multi-bit FIR feedback DAC, along with its compensation path, is used to achieve lower clock jitter sensitivity and better loop filter linearity. The modulator achieves 79.4 dB dynamic range, 77.3 dB SNR, and 74.3 dB SNDR over a 15 MHz signal bandwidth. Fabricated in a 65 nm CMOS process, the core modulator occupies an area of only 0.16 mm^2 and dissipates 6.96 mW from a 1 V supply. A 58.6 fJ/conversion-step figure of merit is achieved. [ABSTRACT FROM AUTHOR]