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In this paper, the adaptive fuzzy control of switched stochastic nonlinear systems with set-time prescribed performance based on event-driven mechanism is studied. The creative part of this paper is that based on the set-time performance function, a modified event-triggered strategy that considers asynchronous switching to deteriorate system performance without strict assumptions is presented, which avoids Zeno behavior and saves communication resources. Then, by using backstepping recursive design technique, It $\hat {o}$ ’s differential lemma and mode-dependent average dwell time (MDADT) method, a novel adaptive performance control scheme is proposed, which can ensure that all the variables in the system are semiglobally uniformly ultimately bounded (SGUUB) in probability and the tracking error gets into prescribed boundary no later than an arbitrarily adjusted setting time. Finally, the proposed algorithm is applied to a RLC circuit and its practicability is verified via simulation results. [ABSTRACT FROM AUTHOR]

This paper presents a low-power and area efficient 10-bit SAR ADC with higher side-reset-and-set (HSRS) switching scheme and hybrid capacitive-MOS (CAP-MOS) DAC. The HSRS switching scheme consumes zero switching energy for the two most-significant bits and skips unnecessary switching without using any auxiliary circuit. It is further verified in this paper that the HSRS switching scheme shows lower nonlinearity compared with the conventional CDAC structure with the same unit capacitor size and matching condition. This additional advantage permits using DAC topologies with lower total capacitance under given linearity requirement. A hybrid CAP-MOS DAC is adopted to reduce the total capacitance of the DAC, which consumes lower static current and chip area than the conventional hybrid capacitive-resistive DAC under the same settling requirement. The prototype 10-bit SAR ADC is implemented in a 0.18- $\mu \text{m}$ CMOS technology, showing an SNDR/SFDR of 56.43 dB/71 dB at 90-kHz input, under a 0.6-V power supply, while consuming $1.01~\mu \text{W}$ at 200 kS/s for a figure of merit of 9.32 fJ/conv.-step. The ADC occupies only a small active area of 0.0675 mm2. [ABSTRACT FROM AUTHOR]

This paper presents a millimeter-wave wide tuning range voltage-controlled oscillator (VCO) incorporating two switchable decoupled VCO cores. When the first core is switched on producing the low frequency band (LFB) signal and the second core is off, the inductors of the second core are reused to create additional buffers that pass the LFB signal to the output buffers. The generated high frequency band (HFB) signals by the second core when turned on, are directly fed to the output buffers. Producing the outputs of both VCO cores across same terminals without utilizing active/passive combiners and coupled inductors will enhance the phase noise performance of the VCO, increase its output power, and reduce the chip size. Fabricated in a 65-nm CMOS process, the VCO achieves a measured wide tuning range of 26.2% from 54.1 to 70.4 GHz while consuming 7.4–11.2-mA current from 1-V power supply. The peak measured phase noise at 10-MHz offset is −116.3 dBc/Hz and the corresponding FOMT and FOM varies from −180.96 to −191.86 dB and −172.6 to −183.5 dB, respectively. The VCO core area occupies only $0.1 \,\, \times 0.395\,\,\mu \text{m}^{{2}}$. [ABSTRACT FROM AUTHOR]

This paper presents a low-power and area efficient 10-bit successive approximation register (SAR) analog-to-digital (ADC) with a hybrid capacitive-MOS consisting of a 7-bit MSB capacitive DAC (CDAC) and a 3-bit LSB MOS DAC (MDAC), which consumes less power and much smaller chip area than a pure CDAC. Instead of using a string of eight MOS transistors to control one unit capacitor, the 3-bit LSB MDAC is realized by a MOS string with four native MOS transistors to control two unit capacitors, which allows higher voltage drop and more reliable operation for each unit MOS. The overall energy consumption of the proposed CAP-MOS DAC is reduced by 56.2% compared to a Vcm-based 10-bit pure CDAC with the same unit capacitance. Under the sampling rate of 200 kS/s, the prototype 10-bit SAR ADC implemented in a 0.18- ${\mu }\text{m}$ CMOS technology achieves a signal-to-noise-and-distortion ratio / spurious-free dynamic range of 56.91 /68.56 dB at 99-kHz input under a 0.6-V power-supply, while consumes $1.76~{\mu }\text{W}$ at 200 kS/s for a figure of merit of 15.38 fJ/step. The peak DNL and INL are +0.27/−0.21 LSB and +0.43/−0.45 LSB, respectively. The ADC occupies a small active area of 0.097 mm2. [ABSTRACT FROM AUTHOR]

Nowadays, more and more RF systems include switchable matching networks to decrease the impact of the environment-dependent antenna impedance on the RF front end performance. This paper reviews the theoretical lower limit on the required number of matching states to match VSWR ranges and then presents an analysis of hardware implementations to actually implement a suitable switchable matching network. A number of matching network topologies are analyzed: PI networks, loaded transmission lines, branch line coupler based circuits, single circulators and cascaded circulators. In our investigation only narrow-band applications are targeted. For the various circuit implementations the required number of matching states for each hardware implementation is compared to the theoretical minimum number of states required for the same matching in order to benchmark their hardware implementation overhead. It appears that a matching network using cascaded circulators is the closest to the theoretical optimum for networks with a relatively low number of states: this type of matching network was implemented and analyzed in more detail. [ABSTRACT FROM AUTHOR]

Design details and analysis of the properties of a hysteresis switching controller for the Ćuk converter are provided in this paper. The design is based on a switching control law which minimizes a common Lyapunov function derivative for the converter's continuous modes of operation. These continuous modes of operation are both marginally stable which causes some particularities in the design procedure. The design also meets the specifications in terms of the converter's duty ratio and the frequency limitations. The proposed hysteresis controller performance is analyzed with respect to the operating modes of the converter and illustrated with a number of representative and relevant simulations. [ABSTRACT FROM PUBLISHER]

The cooperative output regulation problem for singular multi-agent systems subject to static networks was studied recently under the assumption that each follower system satisfies the standard assumption. In this paper, we further study the same problem for singular multi-agent systems subject to jointly connected switching networks. First, by introducing a static output feedback control, we remove the unnecessary standard assumption on the singular system in the existing result. Then, we derive a reduced-order normal multi-agent system and obtain a distributed output measurement feedback control law based on the existing result on the normal multi-agent system. Finally, we show that the composition of the static output feedback control law and the distributed output measurement feedback control law solves the cooperative output regulation problem for the original singular multi-agent system. Our result enlarges the class of systems whose cooperative output regulation problem is solvable. [ABSTRACT FROM AUTHOR]

This paper investigates the formation control problem for linear multi-agent systems under switching directed topologies. Based on absolute or relative outputs, we propose two distributed observer-based event-triggered control schemes. Both schemes can guarantee the boundedness of formation errors under sufficient conditions. The schemes can also avoid Zeno behaviors by giving an estimation for the lower bound of sampling intervals. Finally, simulations and experiments validate the proposed approaches. [ABSTRACT FROM AUTHOR]

This paper presents a sliding mode dynamic output feedback controller design for Markovian jump systems under a communication network. For the inaccessible states and uncertain parts of Markovian jump systems, a novel integral-type sliding mode output feedback controller combined with system states and dynamic controller states is proposed. An event-triggered mechanism is introduced to reduce network bandwidth and resources requirements. The augmented dynamic system and complete control framework are presented together. The reachability of the novel integral-type sliding mode is proved. Then, based on delay-dependent Lyapunov functions, free-weighting matrices, and a singular value decomposition approach, a less conservative sufficient condition is proposed to ensure exponential stability with a weighted $\mathcal {L}_{2}$ - $\mathcal{ L}_{\infty}$ disturbance performance. Finally, a numerical and a DC-DC switched boost converter circuit simulations that verify the feasibility and effectiveness of the proposed controller are presented. [ABSTRACT FROM AUTHOR]

Energy harvesting techniques provide solutions for powering battery-free circuits or even for charging storage elements such as batteries or super capacitors. In this paper a self-starting switched-capacitor approach based on three-stage charge pump that is appropriate to thermoelectric and photo-voltaic energy harvesting, is carried out in a 28 nm ultra-thin buried oxide (UTBB) fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. By taking advantage of the FD-SOI substrate characteristics, the forward-body-biasing (FBB) technique is applied in order to improve switch conductances. In addition, a sizing exploration of standard N-type and flipped-well P-type devices operating as switches is advanced, in order to provide optimum balance between their conductances. Extensive simulation results validate the proper operation of the charge pump at a minimum input voltage of 150 mV, and show a maximum efficiency peak of 63.3% at an input voltage of 350 mV and load a current of 500 nA. [ABSTRACT FROM AUTHOR]

The reduction of the nominal supply voltage of CMOS technologies with scaling comes with the decrease of the maximum tolerable voltage of the devices. This poses challenges in implementing circuit blocks that are compliant with standardized communication protocols or deal with off-chip signals in voltage domains larger than the nominal supply (e.g., 1.8 V, 3.3 V, 5 V). Design techniques such as cascoding, voltage shifting and adaptive biasing are effective at removing the need for customized voltage resistant input/output (I/O) devices since they prevent intolerable voltage drops. However, at the input of multiple-channel blocks, the design of switches of multiplexers results critical as the input and the output nodes can assume values beyond the signal range, causing harmful biasing configurations. This paper presents the architecture of a switch for input channel multiplexers able to handle signals up to twice the nominal supply voltage of the employed devices. Its effectiveness has been proved by implementing a 1.6V switch with the core MOS transistors of the 28nm CMOS technology with 0.96V nominal supply voltage. The comparison with a benchmark switch based on 1.8V I/O devices showed that both a larger area (slightly more than twice) and static current consumption ($40\mu \text{A}$) are required. [ABSTRACT FROM AUTHOR]

This paper presents a new energy efficient successive approximation analog-to-digital converter (ADC) using a charge recycling and LSB-down switching scheme for the capacitive digital-to-analog converter (CDAC). Compared to the conventional binary weighed CDAC, the proposed technique exhibits a 95% reduction in switching energy, a 50% reduction in capacitor area, and with 30% reduction in nonlinearity under the same unit capacitor size and matching condition. The improvement on the switching energy consumption is the best among reported CDAC switching techniques. To validate the technique, a prototype of 10-bit ADC is fabricated in a 0.13 \mum CMOS technology using standard capacitors. With a unit capacitor size of 30 fF, the ADC consumes 15.6 \muW from a 0.5 V digital supply and a 1 V analog supply. The measured signal-to-noise-plus- distortion ratio is 54.6 dB (ENOB=8.8) at 1.1 MS/s. The FOM is 31.8 fJ/conv.-step, which is among the best when normalized to the same unit capacitor size. [ABSTRACT FROM AUTHOR]

This paper proposes a new switching sequence with the asymmetric placement of weighting elements for a unary digital-to-analog converter (DAC). The proposed sequence is based on a so-called knight’s tour according to the modified Warnsdorf’s rule. To estimate the efficiency of the proposed switching sequence, a 10-bit resistive DAC has been designed and fabricated in the UMC 180-nm technology. Experimental results show that in comparison with an array of weighting elements without compensation of the systematic error, the proposed switching sequence reduces the maximal integral (INL) and the mean INL by 20% on the average in the temperature range from −40 °C to 85 °C. Besides that, the maximal INL does not depend on the temperature, while the mean INL decreases with temperature increase. [ABSTRACT FROM AUTHOR]

This paper presents a low-energy 64-Kb eight-transistor (8T) one-read/one-write dual-port image memory with a 28-nm fully depleted SOI (FD-SOI) process technology. Our proposed SRAM adopts a selective sourceline drive (SSD) scheme and a consecutive data write technique for improving active energy efficiency at low voltage. The novel SSD scheme controls sourceline voltage and eliminates leakage energy at unselected columns in read operations. We fabricated a 64-Kb 8T dual-port SRAM in the 28-nm FD-SOI process technology. The 8T SRAM cell size is $0.291 \times 1.457\,\,\mu \text{m}^{2}$. The test chip exhibits 0.48-V operation at an access time of 135 ns. The energy minimum point is at a supply voltage of 0.56 V and an access time of 35 ns, where 265.0 fJ/cycle in write operations and 389.6 fJ/cycle in read operations are achieved. These factors are, respectively, 30% and 26% smaller than those of the 8T dual-port SRAM with the conventional scheme. [ABSTRACT FROM AUTHOR]

This paper presents the design of integrated boost and buck switched-capacitor power converters with high efficiency and fast start-up time. An analysis method is determined to evaluate the key performance parameters of integrated power converters, and techniques are proposed to improve the energy conversion efficiency and the dynamic response. Boost and buck structures are modeled and compared in static and transient conditions, including the losses due to parasitic elements. A switch bootstrapping technique prevents short-circuit losses, improves driving capability and start-up time, and enhances the overall efficiency. Moreover, the application of a charge-reuse technique reduces the dynamic power losses of the integrated structures. Prototypes of the integrated power converters were fabricated in a 180-nm CMOS process. Measurement results based on the proposed techniques are presented, demonstrating the improvements in steady-state and transient characteristics with a good correlation between measured and predicted results. [ABSTRACT FROM AUTHOR]

This paper presents an area- and power-efficient dual-output switched capacitor (DOSC) dc–dc buck converter for wearable biomedical devices. The DOSC converter has an input voltage range between 1.05 and 1.4 V and generates two simultaneous regulated output voltages of 1 and 0.55 V. The DOSC consists of two main blocks: a switched capacitor regulator and an adaptive time multiplexing (ATM) controller. The switched capacitor regulator generates a single regulated voltage using pulse frequency modulation based on a predetermined reference voltage. In addition, the ATM controller generates two simultaneous output voltages and eliminates the reverse current using pulse width modulation during the switching between the output voltages. Addressing the reverse current problem is important to reduce the output voltage droop and improve the performance. The proposed converter supports load currents of 10– $350~\mu \text{A}$ and 1– $10~\mu \text{A}$ at load voltages of 1 and 0.55 V, respectively. The DOSC circuit is fabricated in 65-nm CMOS, and it occupies an active area of 0.27 mm2. Measured results show that a peak efficiency of 78% is achieved at a load power of $300~\mu \text{W}$. [ABSTRACT FROM AUTHOR]

A 14 bit 500 MS/s current-steering digital-to-analog converter (DAC) was designed and fabricated in 0.13 \mum CMOS process. For traditional wide-band current-steering DACs, the spurious-free dynamic range (SFDR) is limited by nonlinear distortions from the code-dependent load variations and the code-dependent switching glitches. They are analyzed in this paper and mitigated by the proposed complementary switched current sources (CSCS) and time-relaxed interleaving digital- random-return-to-zero (TRI-DRRZ), respectively. The proposed techniques are fabricated and measured, with an SFDR of 84.8 dB at 11 MHz signal frequency and 73.5 dB at 244 MHz. The DAC consumes 299 mW from a mixed power supply of 1.2 V and 2.5 V with an active area of 1.85\times 0.65\ mm^2. [ABSTRACT FROM AUTHOR]

To provide wide frequency tuning range (FTR) with compact implementation area, a new inductive tuning method is introduced in this paper for CMOS 60 GHz voltage controlled oscillator (VCO). The inductive tuning is based on a switching inductor-loaded transformer by configuring different current return-paths in the secondary coil of the transformer. Different from previous inductive tuning methods, the proposed VCO topology can achieve wide FTR for multiple sub-bands at 60 GHz within compact area by only one transformer. Two 60 GHz VCOs are demonstrated in 65 nm CMOS with design targets for the maximum FTR and the balanced phase noise in each sub-band, respectively. As measured by experiments, the first VCO (asymmetric) achieves a wide FTR of 25.8% from 51.9 to 67.3 GHz with phase noise variation of \pm8.2 dB (-90.2 to -106.7 dBc/Hz at 10 MHz offset) in all sub-bands; and the second VCO (symmetric) realizes a low phase noise variation of \pm2.5 dB (-105.9 to -110.8 dBc/Hz at 10 MHz offset) in all sub-bands with a FTR of 14.2% from 57.0 GHz to 65.5 GHz. [ABSTRACT FROM PUBLISHER]

This paper proposes a novel T-type multilevel inverter (MLI) based on the switched-capacitor technique. The proposed inverter not only achieves that the maximum voltage stress of the switches is less than the input voltage but also has a voltage boost capability, which makes it suitable in high voltage applications. It is worth mentioning that the proposed inverter features two topology extension schemes which help it achieve a higher output level and voltage gain. With the merit of low voltage stress and reduced power devices, a seven-level inverter can be achieved using only two capacitors. Moreover, capacitor voltage self-balancing capability can simplify the complexity of the circuit and control. The topology, operating principle, modulation strategy and analysis of the capacitor of the inverter are presented. The superiorities of the proposed inverter are investigated by comparing with recently proposed hybrid MLIs and switched-capacitor MLIs. Finally, a seven-level prototype is constructed to validate the correctness of the theoretical analysis and the feasibility and effectiveness of the proposed inverter. [ABSTRACT FROM AUTHOR]

This paper presents a low-profile and autonomous piezoelectric energy harvesting system consisting of an extraction rectifier and a maximum power point tracking (MPPT) circuit for powering portable electronics. Synchronized switch harvesting on capacitor-inductor (SSHCI) technique with its unique two-step voltage flipping process is utilized to downsize the ponderous external inductor and extend application areas of such harvesting systems. SSHCI implementation with small flipping inductor-capacitor combination enhances voltage flipping efficiency and accordingly attains power extraction improvements over conventional synchronized switch harvesting on inductor (SSHI) circuits utilizing bulky external components. A novel MPPT system provides robustness of operation against changing load and excitation conditions. Innovation in MPPT comes from the refresh unit, which continually monitors excitation conditions of piezoelectric harvester to detect any change in optimum storage voltage. Compared with conventional circuits, optimal flipping detection inspired from active diode structures eliminates the need for external adjustment, delivering autonomy to SSHCI. Inductor sharing between SSHCI and MPPT reduces the number of external components. The circuit is fabricated in 180 nm CMOS technology with 1.23 mm2 active area, and is tested with custom MEMS piezoelectric harvester at its resonance frequency of 415 Hz. It is capable of extracting 5.44x more power compared to ideal FBR, while using $100~\mu $ H inductor. Due to reduction of losses through low power design techniques, measured power conversion efficiency of 83% is achieved at 3.2 V piezoelectric open circuit voltage amplitude. Boosting of power generation capacity in a low profile is a significant contribution of the design. [ABSTRACT FROM AUTHOR]

This paper proves a novel sampling theorem with constant amplitude and variable width pulses. The theorem states that any bandlimited baseband signal within \pm0.637 can be represented by a pulsewidth modulation (PWM) waveform with unit amplitude. The number of pulses in the waveform is equal to the number of Nyquist samples and the peak constraint is independent of whether the waveform is two-level or three-level. The proof of the sampling theorem uses a simple iterative technique that is guaranteed to converge to the exact PWM representation whenever it exists. The paper goes on to develop a practical matrix based iterative technique to generate the PWM waveform that is guaranteed to converge exponentially. The peak constraint in the theorem is only a sufficient condition. In fact, many signals with higher peaks, e.g., lower than Nyquist frequency sinusoids, can be accurately represented by a PWM waveform. [ABSTRACT FROM PUBLISHER]

This paper presents fully integrated switched-capacitor boost-buck power converters with conversion ratios 5, 7, and 1/5. Such converters operate over a voltage range extended beyond the device ratings due to a low-voltage-stress configuration, accumulation-mode NMOS capacitors, and a circuit technique for switch bootstrapping. After modeling the simple and the symmetrical ladder converters, we determined methods for assessing the device working voltages and for optimizing the sizes of capacitors and switches. The key performance parameters were compared and the losses due to non-linear parasitic capacitances were calculated. The characterization of the prototypes in a 1.8–3.3-V, 0.18- $\mu \text{m}$ CMOS process demonstrated a 15 V range, a 5.4 mW/mm2 output power density, and good correlation between measured and predicted results. [ABSTRACT FROM AUTHOR]

This paper investigates the adaptive fuzzy output feedback event-triggered control problem for a class of switched nonlinear systems with sensor faults. Due to that the unknown nonlinearities of the systems are more general and the sensor undergoes faults, the considered problem is difficult to be addressed by existing schemes. Therefore, fuzzy logic systems are employed to approximate unknown nonlinear terms and a fault compensation coefficient is introduced to compensate for the effect of sensor failures. Then, a state observer is established for estimating unmeasured states. By choosing a suitable common Lyapunov function, an adaptive fuzzy output feedback fault-tolerant event-triggered controller is derived. It is proven that the proposed scheme can guarantee that the system output tracks the desired trajectory effectively, all states of the resulting closed-loop system are semi-globally uniformly ultimately bounded, and the Zeno phenomenon is excluded. Finally, two simulation examples, which include a switched RLC circuit system and a numerical example, are presented to show the the effectiveness of the proposed strategy. [ABSTRACT FROM AUTHOR]

In this paper, we propose a new scheme to directly power a 4.9–5.6GHz LC oscillator from a recursive switched-capacitor DC-DC converter. A finite-state machine is integrated to automatically adjust the conversion ratio and switching frequency of the converter such that its DC output voltage is within ±5% of the desired 1V across input voltage range 1.3–2.2V and < 2mA load current conditions. A gate-driver circuit is embedded in each switch of the converter to guarantee constant on-resistance across PVT variations without sacrificing device reliability. Furthermore, a spur reduction block (SRB) is embedded in the oscillator to suppress the ripple induced spurs by stabilizing its tail current. Both the converter and the oscillator are implemented in 40-nm CMOS technology. The measured peak power efficiency of the converter is 87%, while its spot noise is < 1.5nV/ $\sqrt {\mathrm{ Hz}}$ , which does not degrade the phase noise of the oscillator. The SRB suppresses the spur to < −65dBc under the 30mVpp ripple of the converter. [ABSTRACT FROM AUTHOR]

This paper presents a systematic method to analyze $N$ -path mixers and filters consisting of periodically switched $RC$ -networks of arbitrary order. It is assumed that each capacitor periodically exchanges charge with the rest of the network during the on-phase of the switching clock, then samples its charge, and holds it perfectly until the next on-phase. This assumption allows for using the adjoint network for simplified analysis of the harmonic transfer functions that describe the signal transfer and folding. Moreover, harmonic transfer cancellations due to the $N$ -path implementation with $N$ equal capacitors switched by $N$ non-overlapping clocks are systematically analyzed. The method is applied to a recently published $N$ -path filter-mixer combination and verified by simulations. [ABSTRACT FROM AUTHOR]

This paper proposed a high efficiency boost converter targeting thermoelectric generator energy harvesting. The proposed converter adopts the critical conduction mode rather than the discontinuous mode to reduce the conduction loss, which can improve the peak efficiency at high input power. To reduce the minimum input voltage, an adaptive on-resistance switch, which can automatically change the high side and low side on-resistance according to the input voltage, is used. To maximize the output power, a maximum power point tracking circuit is designed to track the internal source resistance. Radio frequency (RF) kick-up and low voltage startup are used to improve the cold start voltage. The proposed converter is implemented in a 0.18- $\mu \text{m}$ standard CMOS process, which occupies a chip area of about 0.48 mm2. Measurement results show that the peak efficiency of the converter can be up to 90.8% and 60% at 180 and 20 mV of the open-circuit voltage, respectively. Owing to the cold startup circuit, the proposed converter can start successfully with 260-mV open-circuit voltage or −16-dBm RF input. Moreover, the open-circuit voltage can be further lowered to 12 mV with 1.5- $\mu \text{W}$ output power after startup. [ABSTRACT FROM AUTHOR]

An efficient self-powered synchronous electric charge extraction CMOS interface circuit dedicated to piezoelectric harvesters is proposed in this paper. Self-powered peak detection (PKD) and switch circuits are used to reduce quiescent current so that the backup or pre-charged power can be saved. A new low phase lag (LPL) PKD circuit is designed to improve the synchronous extraction efficiency, which only requires one detection capacitor to perform positive and negative PKD. The circuit can be set at general mode (G-mode) or LPL mode (LPL-mode). Under LPL-mode, the phase lag can be reduced typically by 50%, the synchronous extraction efficiency can obtained up to 94%, while the output power can reach 659~\mu \textW when the piezoelectric transducer original open-circuit voltage V\mathrm{ oc,org}=5 V, which is 3.56 times of that of full-bridge rectifier standard energy harvesting circuit at the maximum power point. The minimum harvesting startup voltage is 1.7 V and is independent of the energy storage capacitor voltage V\mathrm{ DC} . The harvesting efficiency can still reach 71.3% at V\mathrm{ oc,org}=5 V. The size of the active area is 0.5 mm2 in a 0.18- \mu \textm CMOS technology. Circuit may be invoked as a functional block for energy autonomous wireless sensor network node of the Internet of Things. [ABSTRACT FROM PUBLISHER]

This paper presents a piezoelectric-based power management solution for battery-free wireless remote switches (BWSs). The proposed BWS IC, including a piezoelectric (PE) energy harvester and a buck converter, can collect the energy generated by a single PE-button press, and then supply that energy to a wireless transmitter to send a message. By combining a rectifier using the synchronized switch harvesting on inductor technique and a 6:1 series–parallel switched-capacitor converter, the proposed PE energy harvester can maximize the collected amount of energy, while supplying it at a low output voltage. In addition, by employing a switching-based start-up scheme and a variable ON-time pulse-frequency modulation scheme, the proposed buck converter can reduce the loss associated with charging the output capacitor during start-up, and then deliver the largest possible energy to the load, while maintaining low voltage ripples and high-power efficiency. A prototype BWS IC fabricated with high-voltage 250-nm CMOS technology was shown to be capable of harvesting a total energy of 246~\mu \textJ from a single button-pressing of a 300-mm2 lead magnesium niobate-lead titanate PE disc. More than 200~\mu \textJ was delivered to the load, sufficient to transmit a 4-B-long message via a 2.4-GHz wireless USB channel over a 10-m distance. [ABSTRACT FROM AUTHOR]

This paper presents a low-power, area-efficient 11-b single-ended successive-approximation-register (SAR) analog-to-digital converter (ADC) targeted for biomedical applications. The design features an energy-efficient switching technique with an error cancelling capacitor network. The input range is twice the reference voltage. The ADC’s loading of the previous stage is reduced by using a single-ended structure, and by eliminating the largest capacitor in the array. The common mode voltage of the input signal can be used as reference voltage. All building blocks were designed in subthreshold for power efficiency, with an asynchronous self-controlled SAR logic. The ADC was fabricated in 0.18 – \mu \textm CMOS 2P4M process. The measured peak SNDR was 60.5 dB, the SFDR was 72 dB, the DNL +0.6/−0.37 LSB, and the INL +0.94/−0.89 LSB. The total power consumption was 250 nW from 0.75-V supply voltage. [ABSTRACT FROM PUBLISHER]

This paper proposes an ultralow power, high precision sub bandgap voltage reference (sub-BGR) for low-voltage self-powered devices. A novel ultralow power curvature compensation circuit is proposed to improve the temperature coefficient over a wide temperature range. A switch capacitor voltage divider with improved leakage current reduction switches is used to obtain a high accuracy and a low power. To minimize the clock feedthrough and charge injection in the switches, a clock scaling down circuit is proposed, that effectively improves the line sensitivity (LS) of the sub-BGR. The proposed sub-BGR is implemented in a 0.18- \mu \textm standard CMOS process with a total area of 0.061 mm2. After measuring 30 chips, the average power consumption is 83 nW at 0.55 V of supply at 27 °C. In the supply voltage range of 0.55 to 1 V, the LS is 0.059%/V, and the error is ±0.75% ( $3\sigma $ ) after trimming. [ABSTRACT FROM PUBLISHER]

This paper studies asymptotic output synchronization for a class of dynamical networks with identical nonlinear nodes and switching topology. The node dynamics are characterized by a quadratic form of incremental-dissipativity. The output synchronization problem of the switched network is first converted into the set stability problem for the interconnected nonlinear system with a particular selection of input-output pair, which preserves dissipativity. Then, synchronization under arbitrary switching among self-synchronizing subnetworks and synchronization by design of switching among subnetworks, where none of them is necessarily self-synchronizing, are investigated by using the common Lyapunov function method and the single Lyapunov function method, respectively. Algebraic synchronization criteria for both cases are established, and the obtained results are applied to the investigation of coupled biochemical oscillators and coupled Chua's circuits. [ABSTRACT FROM AUTHOR]

Traps that are located in the gate oxide of MOSFETs have been established as a cause of low-frequency noise phenomena. Analysis of such noise is usually based on frequency domain, stationary models. It has been shown that such simplistic models produce erroneous results for circuits with time-varying bias conditions. Tian proposed an idealized trap model with the goal of capturing the nonstationary behavior of oxide traps, and were able to elucidate the experimentally observed large noise power reduction in switched MOSFET circuits which eluded any explanation obtainable with legacy stationary models. In this paper, we build on their seminal work and first identify an oversight in their model derivation which had produced an incorrect expression for the single trap noise spectrum. We next derive the correct spectrum expression, verify it against detailed idealized trap simulations and discuss its implications. The idealized trap model is amenable to analytical derivations and useful as a first stage in understanding nonstationary trap noise. We then demonstrate that noise simulations based on a detailed trap description implemented in a compact MOSFET model in a circuit simulator are needed for an accurate characterization of low-frequency noise in switched MOSFET circuits that matches experimental results. [ABSTRACT FROM AUTHOR]

Slewing in switched capacitor (SC) circuits reduces the available time for linear settling, and hence increases the nonlinear settling error. This transient demand in current can be supplied by making the bias currents larger in the operational transconductance amplifier (OTA). However, this increases the static power consumption significantly. In this paper a slewing mitigation technique is presented where just the right amount of charge is provided at the switching instant to the SC circuit so that OTA does not need to provide high peak current. This may eliminate slewing altogether, and allows using OTAs with less static current for the same settling accuracy. The operation of the proposed technique is illustrated by incorporating it in a second-order delta-sigma modulator (DSM). The modulator was designed and simulated in a 65nm CMOS process. Post-layout extracted simulations with optimized design show more than 12 dB improvement in signal to noise and distortion ratio (SNDR) for the same static power. Alternatively, compared to a DSM without such technique, the same performance can be achieved with 30% less power. [ABSTRACT FROM AUTHOR]

This paper is concerned with the $H_\infty $ control problem for switched systems under the event-triggered sampling, the quantization control and the state-dependent switching. The dynamic event-triggered strategy and the quantization control are utilized to adjust the signal transmission and relieve the transmission load. Different from the existing dynamic event-triggered strategies, the triggering condition only needs to be monitored at discrete time. Moreover, the state-dependent switching law is designed by using only the discrete state information. Under the event-triggered sampling, the quantization control and the state-dependent switching, sufficient conditions are proposed to guarantee the $H_\infty $ performance. A switched RLC system is utilized to verify the results in the simulation. [ABSTRACT FROM AUTHOR]

This paper presents a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) that uses a digital-to-analog converter (DAC) configurable window switching technique. By reusing the capacitors in the DAC, the proposed window switching scheme yields window boundaries to determine whether the input is located within the window, and thus avoid unnecessary capacitor switching. The proposed window SAR ADC improves the conversion efficiency and ADC linearity. A qualitative analysis of prior window switching schemes is presented to elaborate for various applications. A low-input capacitance of 1 pF was adopted to relax the input and reference buffers. A prototype ADC was implemented in 180-nm CMOS occupying an active area of 0.1 mm2. At 20 MS/s, it consumes a total power of 1.22 mW from a 1.5-V supply. The measured peak signal-to-noise and distortion ratio and spurious-free dynamic range were 61.7 and 79 dB, respectively. At the Nyquist rate, the measured effective number of bits (ENOB) was 9.53, equivalent to a figure-of-merit (FOM) of 83 fJ/conversion-step. In low-power mode (100 kS/s), it consumed a total power of $1.5~\mu \text{W}$ from a 0.7-V supply. At the Nyquist rate, the measured ENOB was 9.82, equivalent to a FOM of 16.6 fJ/conversion step. [ABSTRACT FROM AUTHOR]

Dynamic average-value models (AVMs) for AC-DC rectifier circuits are generally formulated in state-space form and hence are straightforward to implement in state-variable-based simulation languages. In the nodal analysis-based approach used in electromagnetic transient (EMTP-type) simulation packages, the development of AVMs requires additional effort to reformulate and interface the models with the external ac and dc networks. This paper proposes a new averaged-circuit model for three-phase line-commutated rectifiers which is directly interfaced with the ac and dc networks, thereby achieving a simultaneous solution of the respective variables in EMTP-type solution. The proposed model is verified against conventionally interfaced model, as well as detailed switching model of the original rectifier circuit. A significant improvement of numerical accuracy and stability of the solution is demonstrated even at fairly large time steps. [ABSTRACT FROM AUTHOR]

This paper presents a systematic classification of auxiliary circuit schemes for feeding fast load transients in switching power converters. The classification is based on the types of the implementation methods, practical constraints and performance. In particular, auxiliary circuits are classified according to the ways in which they are connected with the power supplies and loads, as well as the choice of control methods. Designed as a shunt output, the “intruding” type of auxiliary circuits is effective and less dissipative. Moreover, to reduce complexity, auxiliary circuits may be designed in the form of a bridge output, and employs a “non-intruding” type of control scheme. Furthermore, provision of pre-informed loading condition leads to further simplification of auxiliary circuitry and improvement of efficiency. Experimental measurements are provided to support the analysis of the properties of various types of circuits. [ABSTRACT FROM PUBLISHER]

Nonlinear circuits may be synchronized with interconnections that evolve in time incorporating mechanisms of adaptation found in many biological systems. Such dynamics in the links is efficiently implemented in electronic devices by using memristors. However, the approach requires a massive amount of interconnections (of the order of N^2 , where $N$ is the number of nonlinear circuits to be synchronized). This issue is solved in this paper by adopting a memristor crossbar architecture for adaptive synchronization. The functionality of the structure is demonstrated, with respect to different switching characteristics, via a simulation-based evaluation using a behavioral threshold-type model of voltage-controlled bipolar memristor. In addition, we show that the architecture is robust to device variability and faults: quite surprisingly, when faults are localized, the performance of the approach may also improve as adaptation becomes more significant. [ABSTRACT FROM PUBLISHER]

This paper presents a nonlinear state-space model (SSM) for a low power 28-nm complementary metal–oxide–semiconductor switched-capacitor digital-to-analog converter. The proposed model utilizes current–voltage (I-V) input and output relationships for passive devices, which are described by a set of first-order differential equations. The proposed model significantly increases accuracy when compared with the state-of-the-art models. The SSM simulation results have been verified using SpectreRF transistor-level simulations and validated by on-chip measurements. [ABSTRACT FROM AUTHOR]

This paper presents the design and implementation of a 10-bit ultra-low voltage energy-efficient successive approximation register (SAR) analog-to-digital converter (ADC). The proposed first 2-bit guess (F2G) scheme reduces the DAC switching energy by 90% and improves the DNL and INL by \sqrt 3 /2 in theory compared with the conventional approach. By employing majority-vote comparison at the conversions of LSBs, the noise requirement of comparator can be relaxed by half. With the segmented and bundled routing, the parasitic capacitors of bottom-plates of DAC array are reduced to improve power efficiency and speed. Implemented in 90-nm CMOS technology, the test chip occupied a core area of 0.03 mm2. The prototype consumes 67.3 nW at 150 kS/s from a single 0.3 V supply voltage and achieves an ENOB of 8.85 bits and an SFDR of 70.7 dB at Nyquist input, respectively. The resultant Walden’s FoM and Schreier’s FoM are 0.97 fJ/conv.-step and 175.5 dB, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a piezoelectric energy harvesting circuit, which integrates a Synchronized Switch Harvesting on Inductor (SSHI) circuit and an active rectifier. The major design challenge of the SSHI method is flipping the capacitor voltage at optimal times. The proposed SSHI circuit inserts an active diode on each resonant loop, which ensures flipping of the capacitor voltage at optimal times and eliminates the need to tune the switching time. The diodes of the SSHI circuit are also used as a rectifier to further simplify the controller. The key advantage of the proposed circuit is a simple controller, which leads to low power dissipation of the proposed circuit to result in high efficiency. The proposed circuit is self-powered and capable of starting even when the battery is completely drained. The circuit was fabricated in BiCMOS 0.25~\mu \text m technology with a die size of 0.98 \times 0.76 mm2. Measured results indicate that the proposed circuit increases the amount of power harvested from a piezoelectric cantilever by 2.1 times when compared with a full bridge (FB) rectifier and achieves a power conversion efficiency of 85%. The proposed circuit dissipates about 24~\mu \text {W} while the controller alone only 1.5~\mu \text {W}$ . [ABSTRACT FROM AUTHOR]

This paper presents a new method for detecting and reversing the polarity of a low-voltage thermoelectric generator (TEG) in inductor-based converters. The proposed technique makes use of the inductor response to a voltage change due to the flip in the TEG polarity. The inductor voltage provides two distinguishable states which correspond to the normal and the reversed TEG polarity. A switch matrix circuit is then used to correct the polarity by physically reversing the TEG connection. The detection circuit along with the switch matrix provide a positive input voltage from the TEG to the inductor-based converter. The proposed technique is an efficient polarity detection with all-digital implementation, fully integrated, small area and power overhead. The prototype chip is fabricated in 65-nm CMOS and occupies an area of 0.09 mm2. Measurement results confirm a maximum efficiency of 70% at 50 mV TEG voltage and 40~\mu \text A output current. The proposed technique is part of an autonomous thermal energy harvesting system that detects and corrects the TEG polarity. [ABSTRACT FROM AUTHOR]

High step-up conversion is an indispensable feature for the power processing of low voltage renewable sources in grid-connected systems. Motivated by this necessity, this paper presents a study on non-isolated dc-dc converters based on the conventional Boost converter that can provide such feature with high efficiency. By the topological variation and gain cell concepts, it is demonstrated that these converters can be treated as a unique generalized converter, called Boost Converter with Gain Cell (BCGC). The operating principle, the key waveforms and the components stresses of the BGCG are analyzed for the continuous-conduction mode, independently of the employed gain cell. A methodology to create the gain cells is developed from the combination of coupled inductors and voltage multiplier techniques. In order to verify the realized analysis, a 150 W prototype concerning to the proposed generalized converter and able to operate with several different gain cells is developed for the comparison between theoretical and experimental static gain results. [ABSTRACT FROM PUBLISHER]

Switching currents of simultaneous switching output (SSO) buffers can cause significant power-supply-induced jitter (PSIJ) and uncertainty in the output voltages. The bit error rate (BER) can be simulated by considering all possible input data patterns with a long data sequence; however, it requires large computational efforts. In this paper, the SSO waveforms are analytically calculated, including the rise time of the input voltage, and the probability density functions (PDFs) of the waveforms are analytically calculated. The PDFs of the SSO step responses are combined with the inter-symbol interference (ISI) PDF extraction. The statistical eye and BER eye diagrams obtained from the proposed method are validated with HSPICE simulations. The effects of the SSO patterns as well as the channel ISI are successfully included in the proposed method. Also, the effects of input rise time and the number of parallel SSO buffers are investigated, and the proposed method is extended for analysis of SSO buffers with the data bus inversion (DBI) coding. The method should be practically useful for design of wideband memory I/O interfaces and low-cost consumer devices by reducing the computational time of the jitter and BER drastically. [ABSTRACT FROM PUBLISHER]

A simple graph with four nodes and eleven branches is defined. Its branches are filled in different ways with passive elements (capacitors, inductors, diodes) or replaced by shortcircuits in order to get potential voltage step-up switching cells. These cells are inserted in boost converter, obtaining thus non-isolated power electronics circuits with a very high dc gain. Such circuits are necessary today in the green energy systems. The proposed circuits feature a lower voltage stress on its semiconductors (both switch and diodes) than that on the equivalent devices of a boost stage. A state-space-based dc and ac analysis allows for deriving the dc gain, the switches voltage and current stresses, and the frequency characteristics of the obtained converters. The steady-state analysis is performed for both the continuous and discontinuous conduction mode operations. The converters belonging to the new family are compared between them and then compared with available solutions of similar complexity as defined by the component count. Simulation and experimental results confirm the theoretical equations. [ABSTRACT FROM PUBLISHER]

This paper investigates the problem of leader-following consensus of a linear multi-agent system on a switching network. The input of each agent is subject to saturation. Low gain feedback based distributed consensus protocols are developed. It is established that, under the assumptions that each agent is asymptotically null controllable with bounded controls and that the network is connected or jointly connected, semi-global leader-following consensus of the multi-agent system can be achieved. Numerical examples are presented to illustrate this result. [ABSTRACT FROM PUBLISHER]

The design and analytical modeling of a high efficiency energy harvester comprising a passive voltage-boosting network (VBN) and a switching charge pump rectifier (CPR) is presented in this paper. To improve the power conversion efficiency (PCE), the VBN increases the voltage at the input of the CPR and provides control signals for switching. Unlike traditional Schottky and diode-connected MOS transistor rectifiers, the proposed orthogonally switching CPR (OS-CPR) comprises MOS transistors as voltage-controlled switches. Analytical models for the OS-CPR are developed and presented. Circuit-level optimization techniques are employed to reduce conduction and switching losses. Simulated in a 90 nm standard CMOS technology (IBM 9RF), a 5-stage 915 MHz OS-CPR achieves a dc voltage of 1.35 V and a PCE of 11.9% with a 1 M\Omega load at -18.2 dBm available input power (PS,AV). To show technology scalability of the design, the OS-CPR is also validated using AMS 0.18 \mum high-voltage (HV) CMOS technology. When benchmarked with traditional rectifiers, the OS-CPR (under similar conditions) achieves a higher PCE and a higher output dc voltage. The OS-CPR is easily scalable to operate over multiple sub-GHz ISM frequency bands. [ABSTRACT FROM PUBLISHER]

This paper initiates a systematic methodology for generating various grid multiwing hyperchaotic attractors by switching control and constructing super-heteroclinic loops from the piecewise linear hyperchaotic Lorenz system family. By linearizing the three-dimensional generalized Lorenz system family at their two symmetric equilibria and then introducing the state feedback, two fundamental four-dimensional linear systems are obtained. Moreover, a super-heteroclinic loop is constructed to connect all equilibria of the above two fundamental four-dimensional linear systems via switching control. Under some suitable conditions, various grid multiwing hyperchaotic attractors from the real world applications can be generated. Furthermore, a module-based circuit design approach is developed for realizing the designed piecewise linear grid multiwing hyperchaotic Lorenz and Chen attractors. The experimental observations validate the proposed systematic methodology for grid multiwing hyperchaotic attractors generation. Our theoretical analysis, numerical simulations and circuit implementation together show the effectiveness and universality of the proposed systematic methodology. [ABSTRACT FROM PUBLISHER]

The high-speed successive-approximation-register (SAR) analog-to-digital converters (ADCs) rely on the switched capacitive digital-to-analog converter (CDAC) to perform the fast transition, which causes voltage ripples at the output of the reference circuits. Such ripples lead to the reference error that eventually prolongs the time for DAC settling. To minimize such error with a short available time, it either demands a power-hungry reference buffer or large die area for the decoupling. In this paper, we offer a comprehensive analysis of the reference errors in SAR ADCs with a practical reference network circuit (RNC) in consideration. A circuit model is developed in order to quantify the error amplitude for the critical DAC settling condition. Based on the proposed model, the settling behavior of the DAC with reference buffer can be precisely characterized, leading to a better understanding about the design tradeoff of the RNC. Finally, the developed model is verified by both circuit level simulations and measurement results. [ABSTRACT FROM AUTHOR]

Motivated by different applications in circuits, electromagnetics, and optics, this paper is concerned with the synthesis of a particular type of linear circuit, where the circuit is associated with a control unit. The objective is to design a controller for this control unit such that certain specifications on the parameters of the circuit are satisfied. It is shown that designing a control unit in the form of a switching network is an NP-complete problem that can be formulated as a rank-minimization problem. It is then proven that the underlying design problem can be cast as a semidefinite optimization if a passive network is designed instead of a switching network. Since the implementation of a passive network may need too many components, the design of a decoupled (sparse) passive network is subsequently studied. This paper introduces a tradeoff between design simplicity and implementation complexity for an important class of linear circuits. The superiority of the developed techniques is demonstrated by different simulations. In particular, for the first time in the literature, a wavelength-size passive antenna is designed, which has an excellent beamforming capability and which can concurrently make a null in at least eight directions. [ABSTRACT FROM PUBLISHER]