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Energy harvesting techniques provide solutions for powering battery-free circuits or even for charging storage elements such as batteries or super capacitors. In this paper a self-starting switched-capacitor approach based on three-stage charge pump that is appropriate to thermoelectric and photo-voltaic energy harvesting, is carried out in a 28 nm ultra-thin buried oxide (UTBB) fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. By taking advantage of the FD-SOI substrate characteristics, the forward-body-biasing (FBB) technique is applied in order to improve switch conductances. In addition, a sizing exploration of standard N-type and flipped-well P-type devices operating as switches is advanced, in order to provide optimum balance between their conductances. Extensive simulation results validate the proper operation of the charge pump at a minimum input voltage of 150 mV, and show a maximum efficiency peak of 63.3% at an input voltage of 350 mV and load a current of 500 nA. [ABSTRACT FROM AUTHOR]

The high-speed successive-approximation-register (SAR) analog-to-digital converters (ADCs) rely on the switched capacitive digital-to-analog converter (CDAC) to perform the fast transition, which causes voltage ripples at the output of the reference circuits. Such ripples lead to the reference error that eventually prolongs the time for DAC settling. To minimize such error with a short available time, it either demands a power-hungry reference buffer or large die area for the decoupling. In this paper, we offer a comprehensive analysis of the reference errors in SAR ADCs with a practical reference network circuit (RNC) in consideration. A circuit model is developed in order to quantify the error amplitude for the critical DAC settling condition. Based on the proposed model, the settling behavior of the DAC with reference buffer can be precisely characterized, leading to a better understanding about the design tradeoff of the RNC. Finally, the developed model is verified by both circuit level simulations and measurement results. [ABSTRACT FROM AUTHOR]

An efficient self-powered synchronous electric charge extraction CMOS interface circuit dedicated to piezoelectric harvesters is proposed in this paper. Self-powered peak detection (PKD) and switch circuits are used to reduce quiescent current so that the backup or pre-charged power can be saved. A new low phase lag (LPL) PKD circuit is designed to improve the synchronous extraction efficiency, which only requires one detection capacitor to perform positive and negative PKD. The circuit can be set at general mode (G-mode) or LPL mode (LPL-mode). Under LPL-mode, the phase lag can be reduced typically by 50%, the synchronous extraction efficiency can obtained up to 94%, while the output power can reach 659~\mu \textW when the piezoelectric transducer original open-circuit voltage V\mathrm{ oc,org}=5 V, which is 3.56 times of that of full-bridge rectifier standard energy harvesting circuit at the maximum power point. The minimum harvesting startup voltage is 1.7 V and is independent of the energy storage capacitor voltage V\mathrm{ DC} . The harvesting efficiency can still reach 71.3% at V\mathrm{ oc,org}=5 V. The size of the active area is 0.5 mm2 in a 0.18- \mu \textm CMOS technology. Circuit may be invoked as a functional block for energy autonomous wireless sensor network node of the Internet of Things. [ABSTRACT FROM PUBLISHER]

This paper presents a nonlinear state-space model (SSM) for a low power 28-nm complementary metal–oxide–semiconductor switched-capacitor digital-to-analog converter. The proposed model utilizes current–voltage (I-V) input and output relationships for passive devices, which are described by a set of first-order differential equations. The proposed model significantly increases accuracy when compared with the state-of-the-art models. The SSM simulation results have been verified using SpectreRF transistor-level simulations and validated by on-chip measurements. [ABSTRACT FROM AUTHOR]

This paper presents an efficient numerical methodology to obtain the frequency response of switched-capacitor filters based on the circuits' differential equations. This methodology uses a non-hierarchical approach in which the non-ideal effects of the transistors (in the switches and in the amplifier) are taken into consideration, allowing the accurate computation of the frequency response, even in the case of incomplete settling in the SC branches. The accuracy is demonstrated by comparing the results obtained using the proposed methodology with those obtained using transient electrical simulation results for three different SC circuits: a first order SC passive filter, a second order SC lowpass filter, and a second order SC bandpass filter, showing that the results are in good agreement with the more time consuming electrical simulation of the circuits. [ABSTRACT FROM PUBLISHER]

Switching currents of simultaneous switching output (SSO) buffers can cause significant power-supply-induced jitter (PSIJ) and uncertainty in the output voltages. The bit error rate (BER) can be simulated by considering all possible input data patterns with a long data sequence; however, it requires large computational efforts. In this paper, the SSO waveforms are analytically calculated, including the rise time of the input voltage, and the probability density functions (PDFs) of the waveforms are analytically calculated. The PDFs of the SSO step responses are combined with the inter-symbol interference (ISI) PDF extraction. The statistical eye and BER eye diagrams obtained from the proposed method are validated with HSPICE simulations. The effects of the SSO patterns as well as the channel ISI are successfully included in the proposed method. Also, the effects of input rise time and the number of parallel SSO buffers are investigated, and the proposed method is extended for analysis of SSO buffers with the data bus inversion (DBI) coding. The method should be practically useful for design of wideband memory I/O interfaces and low-cost consumer devices by reducing the computational time of the jitter and BER drastically. [ABSTRACT FROM PUBLISHER]

Designing a SPICE model is a critical step toward understanding the behavior of the resistive random access memory (RRAM) devices when integrated in memory design for the future generation storage devices. In this paper, a SPICE model is developed for the \textrmTa2\textrm{O}5/\textrm{TaO}x bi-layered RRAM. The proposed model emphasizes the impact of the change in the switching layer thickness on the device behavior at low resistance state (LRS), high resistance state (HRS), and the transitional period. The validity of the proposed model is verified through using three different sets of experimental data from \textrmPt/Ta2\textrm{O}5/\textrm{TaO}x/\textrm{Pt} RRAM with switching layer thickness smaller than 5 nm. The SPICE model reproduced all the major features from the experimental results for the SET and RESET processes and also the asymmetric and the symmetric characteristics in HRS and LRS, respectively. The proposed SPICE model matches the measured experimental results with an average error of < 11% and a maximum error of < 70%. It also showed stable behavior for its HRS and LRS regions under different types of input signals. The model is parameterized in order to fit into \textrmTa2\textrm{O}5/\textrm{TaO}x RRAM devices with switching layer thickness smaller than 5 nm, thus, facilitating the model usage. The model can be included in the SPICE-compatible circuit simulation and is suitable for the exploration of the \textrmTa2\textrm{O}5/\textrm{TaO}x bi-layered RRAM device performance at circuit level. [ABSTRACT FROM AUTHOR]

Motivated by different applications in circuits, electromagnetics, and optics, this paper is concerned with the synthesis of a particular type of linear circuit, where the circuit is associated with a control unit. The objective is to design a controller for this control unit such that certain specifications on the parameters of the circuit are satisfied. It is shown that designing a control unit in the form of a switching network is an NP-complete problem that can be formulated as a rank-minimization problem. It is then proven that the underlying design problem can be cast as a semidefinite optimization if a passive network is designed instead of a switching network. Since the implementation of a passive network may need too many components, the design of a decoupled (sparse) passive network is subsequently studied. This paper introduces a tradeoff between design simplicity and implementation complexity for an important class of linear circuits. The superiority of the developed techniques is demonstrated by different simulations. In particular, for the first time in the literature, a wavelength-size passive antenna is designed, which has an excellent beamforming capability and which can concurrently make a null in at least eight directions. [ABSTRACT FROM PUBLISHER]

Traps that are located in the gate oxide of MOSFETs have been established as a cause of low-frequency noise phenomena. Analysis of such noise is usually based on frequency domain, stationary models. It has been shown that such simplistic models produce erroneous results for circuits with time-varying bias conditions. Tian proposed an idealized trap model with the goal of capturing the nonstationary behavior of oxide traps, and were able to elucidate the experimentally observed large noise power reduction in switched MOSFET circuits which eluded any explanation obtainable with legacy stationary models. In this paper, we build on their seminal work and first identify an oversight in their model derivation which had produced an incorrect expression for the single trap noise spectrum. We next derive the correct spectrum expression, verify it against detailed idealized trap simulations and discuss its implications. The idealized trap model is amenable to analytical derivations and useful as a first stage in understanding nonstationary trap noise. We then demonstrate that noise simulations based on a detailed trap description implemented in a compact MOSFET model in a circuit simulator are needed for an accurate characterization of low-frequency noise in switched MOSFET circuits that matches experimental results. [ABSTRACT FROM AUTHOR]

Dynamic average-value models (AVMs) for AC-DC rectifier circuits are generally formulated in state-space form and hence are straightforward to implement in state-variable-based simulation languages. In the nodal analysis-based approach used in electromagnetic transient (EMTP-type) simulation packages, the development of AVMs requires additional effort to reformulate and interface the models with the external ac and dc networks. This paper proposes a new averaged-circuit model for three-phase line-commutated rectifiers which is directly interfaced with the ac and dc networks, thereby achieving a simultaneous solution of the respective variables in EMTP-type solution. The proposed model is verified against conventionally interfaced model, as well as detailed switching model of the original rectifier circuit. A significant improvement of numerical accuracy and stability of the solution is demonstrated even at fairly large time steps. [ABSTRACT FROM AUTHOR]

This paper presents a systematic classification of auxiliary circuit schemes for feeding fast load transients in switching power converters. The classification is based on the types of the implementation methods, practical constraints and performance. In particular, auxiliary circuits are classified according to the ways in which they are connected with the power supplies and loads, as well as the choice of control methods. Designed as a shunt output, the “intruding” type of auxiliary circuits is effective and less dissipative. Moreover, to reduce complexity, auxiliary circuits may be designed in the form of a bridge output, and employs a “non-intruding” type of control scheme. Furthermore, provision of pre-informed loading condition leads to further simplification of auxiliary circuitry and improvement of efficiency. Experimental measurements are provided to support the analysis of the properties of various types of circuits. [ABSTRACT FROM PUBLISHER]

A third-order passive switched-capacitor low-pass filter is presented together with experimental results. The current input-voltage output filter structure realizes complex-conjugate poles although it is composed of switches and capacitors. The results are verified with measurements performed on the filter prototype integrated in a 0.13- $\mu \text{m}$ CMOS technology. The prototype has a cut-off frequency of 470 kHz, 150- $\mu \text{W}$ power consumption from 1.2-V power supply, 92-dB SFDR, and an active area of 0.06 mm2. The switch-capacitor filter was obtained using a continuous-time model that is also described here and is useful for design, analysis, and simulation of oversampled switched-capacitor circuits. The model is applicable to a variety of topologies including multi-phase passive switched-capacitor filters, switched-capacitor integrators, as well as switched-capacitor dc/dc converters. [ABSTRACT FROM AUTHOR]

An analytical method is presented to characterize stepwise adiabatic circuits (SACs). In this method, the SACs are modeled as a discrete time system. Unlike previous methods, the stability is verified for arbitrary load capacitor ratios. Moreover, this method presents analytical derivations to offer an area/energy efficient design methodology. MATLAB simulations, post-layout simulations in the CMOS 0.18 \mum technology, silicon measurements, and measurements based on discrete components confirm the precision of the analytical derivations. Using the proposed design methodology, a capacitive tank has been designed which reduces the energy consumption by 20% while the total size of the tank capacitors is smaller than 0.4CL. Additionally, a new switching procedure for the SACs is presented. This procedure stabilizes the voltage levels without reverse switching, unlike previously reported methods. Thus preserving the energy efficiency, it improves the speed by a factor of up to two, since the tank recycles its charge inherently. Moreover, the capacitive load can retain its charge after the charging process and let the tank charges another load capacitor. As a result, the proposed switching procedure can be used in multi-cycle circuits such as the capacitive DAC of a SAR ADC in which the load capacitor must hold its charge after charging process is finished. [ABSTRACT FROM PUBLISHER]

In order to combat the exponentially growing leakage power in modern microprocessors, researchers have proposed the use of alternative power-gating structures that can yield higher leakage savings with a much lower performance impact. A prime contender is an emerging CMOS-compatible power-gating device, the nanoelectromechanical systems (NEMS) switch. Compared to transistors, NEMS switches have zero off-state leakage, so for very long periods of sleep, their effectiveness is unparalleled. For systems with periods of faster on/off rates, however, their slower switching speed, high activation energy, and finite device lifetime become drawbacks. This motivates an exploration to determine whether NEMS switches are capable of fast, fine-grained power-gating. In this article, we provide an accurate energy model of functional-unit power-gating that allows us to effectively compare transistors and NEMS switches. It is also fast enough to support the optimization of a wide variety of circuit- and system-level parameters, including supply voltage, threshold voltage, and power-gating scheduler aggressiveness. Using this framework, we show that NEMS switch power-gates along with an ideal oracle power-gating policy can achieve an average 29.5% drop in total functional unit energy, compared to only 23.5% with transistor power-gates. A more realistic hardware-based policy for NEMS switches yields a 28.9% drop, compared to a 23.0% drop with transistors. [ABSTRACT FROM AUTHOR]

A new switching circuit analysis technique is proposed in which the reverse recovery and junction capacitance non-idealities of diode-based switches are incorporated into a state plane analysis of the circuit. Accurate state plane modeling of the reverse recovery process is based on the development of new generalizations of the classic charge control model. Using as an example a zero-voltage switching dc transformer possessing high sensitivity to diode characteristics, these generalizations are shown to be necessary to achieve accurate results across all operating modes. The proposed circuit analysis technique produces excellent modeling agreement with results measured on a hardware prototype of the dc transformer circuit. [ABSTRACT FROM AUTHOR]