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The series-paralleling technique of dc-dc converters is utilized in various domains of electrical engineering for improved power conversion. Previous studies have proposed and classified the control schemes for the series-paralleled converters. However, they have several restrictions and lack diversity. The purpose of this paper is to propose passivity-based control (PBC) for the diverse output series-parallel connection of dc-dc converters. It is proved that the output series-paralleled converters regulated by PBC are asymptotically stable. The output series-paralleled converters are numerically simulated to confirm the asymptotic stability. PBC is shown to maintain the stability of the output series-paralleled converters with diverse circuit topologies, parameters, and steady-states. The result of this paper theoretically supports the numerical and experimental considerations in the previous studies and justifies the further extension of the series-parallel connection. [ABSTRACT FROM AUTHOR]

This paper presents a novel ultra-low power maximum power point tracking (MPPT) technique with a wide tracking range. An indirect, non-interrupting approach using a novel timing-based algorithm is proposed. The proposed MPPT technique is self-adaptive and applicable to the various types of photovoltaic cells without external reconfiguration or the change of passive components. In addition, a variable gain is employed in the one-hot barrel shift register to reduce the transient response time. A test chip was fabricated in 65-nm CMOS technology. The test chip can harvest energy with the input voltage range of 0.4 V to 1.7 V and the step response time of less than 100 ms at the minimum supply voltage of 0.8 V. The tracking efficiency is up to 96.2% when supplied by a photovoltaic micro-cell array using an irradiation range of 200 lux to 1000 lux. [ABSTRACT FROM PUBLISHER]

The DC-DC converter severs as one of the crucial components in DC microgrid applications. In this paper, a novel low frequency current-mode control strategy is proposed to improve overshoot suppression performance for the boost converter against load current and source voltage disturbances. The control strategy is presented as a cascade dual-loop structure composed of a dynamic current-loop controller with asymmetric saturation and a PI form voltage-loop controller. With the low frequency information of disturbances, the designed dynamic current-loop controller delivers not only promising disturbance suppression but also superior reference current tracking. Simulation and experiment results are provided to illustrate the superiority of the proposed strategy on overshoot suppression. [ABSTRACT FROM AUTHOR]

This paper proposes a family of integrated multiple output isolated dc–dc converters, in which switches are hybrid utilized. Compared with the conventional separate $N$ -output isolated converter, which employs $2N$ primary switches, only $N$ +1 switches are required in the primary side of proposed converters to independently regulate $N$ secondary output voltages. Therefore, the number of switches is greatly reduced, contributing to lower cost. In this paper, detailed topology derivation is first introduced. A diversity of integrated multiple output topologies is derived with different cell connections and different cell configurations, including the asymmetrical flyback, forward as well as a half-bridge. Their performance characteristics are different and thus they are suitable for different applications. Then, in order to obtain a comprehensive insight of the proposed converters, a simplified dual-output asymmetrical flyback converter with three primary switches is taken as an example to be introduced in detail. Each output voltage in the converter is regulated with individual duty cycle, and zero-voltage-switching operation is achieved for all switches over the whole load range. Finally, experimental results based on a prototype circuit with two 12-V/3-A and 5-V/4.8-A outputs are also provided to validate converter effectiveness. [ABSTRACT FROM PUBLISHER]

This paper proposes a low power area-efficient multi-mode voltage clamper circuit called pseudo differential pair and applies it into an error amplifier (EA) which can be used in DC-DC converters as a practical design example. In addition to a normal amplifying mode, the error amplifier has two extra operation modes with the help of the voltage clamper, which can limit the maximum output voltage and the maximum sink current, respectively. By inserting this pseudo differential pair of only three transistors in the intermediate stage of the amplifier, a voltage-current feedback is introduced to achieve the voltage limiting function without bringing resistive load to the output stage or unwanted effects to the input stage. The frequency compensation of the EA is also reused in the voltage limiting loop to make the whole block more compact. The circuit is implemented in a $0.35~\mu \text{m}$ BCD process. The verification results match the theoretical analysis very well, which proves that the proposed voltage clamper can effectively enhance transient response of the converter control loop and improve system reliability. Only additional 0.001689 mm2 active area is occupied for about 2X transient speed improvement with fair open loop amplifying performance. [ABSTRACT FROM AUTHOR]

This paper presents a fully integrated galvanically isolated dc–dc converter with data communication. The converter, which is fabricated in a 0.35- \mu \textm BCD technology, is made up of only two silicon dice and adopts two 6-kV on-chip transformers. It takes advantage of a customized architecture, which uses the isolated power control link to transfer bidirectional half-duplex data, thus reducing the overall silicon area and package size. The proposed dc–dc converter delivers up to 93-mW output power with 19% maximum power efficiency and an output voltage ranging from 2.4 V to 3.3 V, while achieving a data rate up to 50 Mb/s. [ABSTRACT FROM AUTHOR]

This paper presents an efficiency-enhanced low-profile zero-voltage-transition (ZVT) synchronous non-inverting buck-boost converter for 48-V tens-of-Watt output applications. By only using three auxiliary components shared between two switching nodes, zero-voltage switching (ZVS) of all four power switches and zero-current switching of the auxiliary switch are achieved in the proposed converter to minimize the switching power loss. Compared with the existing ZVT topologies, the proposed converter reduces the required number of auxiliary components, thereby decreasing the converter volume and power loss. In addition, the proposed converter can be configured into the buck mode with full ZVS capability to support a wide input range from 36 V to 90 V. Experimental results show that the proposed converter can operate at 1 MHz and deliver a maximum output power of 75 W. The measured peak power efficiencies achieve 92.5% and 96.3% in the buck-boost mode and buck mode, respectively. Compared with the state-of-the-art ZVS-based buck-boost counterpart, the proposed converter reduces the volume of the auxiliary circuit by ~2 times even with 28% increase in the maximum load current and two times reduction in the switching frequency, and provides higher peak power efficiencies in both buck-boost and buck modes. [ABSTRACT FROM AUTHOR]

This paper presents a double-isolated dc-dc converter exploiting integrated LC galvanic barriers. The converter consists of only two dice both fabricated in a 0.35- $\mu \text{m}$ BCD technology with a thick-oxide back-end for 5-kV galvanic isolation. It uses a novel architecture to transmit power and the control feedback signal across two double isolation barriers, which are performed by integrated isolation capacitors and transformers. A resonant mode operation for the isolation networks is exploited to boost efficiency with respect to traditional converter schemes based on series-connected isolation components. Measurements of the dc-dc converter at 3.3-V power supply demonstrate 100-mW dc output power with a power efficiency of 16.8% at a regulated output voltage of 3.3 V. [ABSTRACT FROM AUTHOR]

This paper presents a time-division-multiplexed (TDM) clocked-analog low-dropout regulator (CLDO) that shares one controller between multiple output channels. Clocked-analog operation is introduced to create idle periods that enable the shared controller to independently regulate different output channels through time-division multiplexing. Furthermore, an asynchronous transient enhancing technique is presented. Thanks to the controller sharing, the TDM CLDO is more area-efficient than conventional designs for supplying multiple outputs, especially when power stages and on-chip loads are small. To verify the effectiveness of the TDM CLDO, a dual-channel version is fabricated in a 130 nm CMOS process. Measurement results show that it can independently track two 100 kHz $0.3~\rm V_{pp}$ sinusoidal signals with 4 mV average output error at $100~\Omega $ load and 6 MHz clock frequency. For load transient responses, it can independently regulate two output channels to 1.05 V and 0.95 V with 41 mV/88 mV and 67 mV/39 mV overshoot/undershoot when both channels experience 5 mA current steps at $1.2~\rm V_{dd}$. To the best of our knowledge, this is the first time that hardware sharing is implemented for continuous closed-loop systems. [ABSTRACT FROM AUTHOR]

This paper presents the design and measurement of an RF energy harvesting and power management unit that operates across a wide range of available input power, from −24 to +15dBm. The system comprises an adaptive impedance matching network, a single-stage cross-coupled differential-drive rectifier, a start-up charge pump, an adaptive buck-boost converter, a maximum power point tracking (MPPT) circuit and a control loop to regulate the load voltage. The MPPT circuit controls the switching frequency of the buck-boost converter and configures the impedance matching network, optimizing the interfaces between the rectifier and antenna and between the rectifier and the storage capacitor, guaranteeing that the power is being harvested at maximum efficiency. To boost the rectifier output, to accumulate energy in the storage capacitor and to provide energy to the load, a single-inductor buck-boost converter that has two inputs and three outputs is used. Circuit techniques that reduce the power consumption of the control circuits and that allow for adapting the interfaces between the antenna, the rectifier and the load are presented. The peak harvesting efficiency of the system is 40.2%, when presented with an RF source of -9.1dBm available power and 403.5MHz frequency. [ABSTRACT FROM AUTHOR]

A disturbance observer-based control (DOBC) approach is proposed in this paper for control design and qualitative robustness analysis of PWM-based DC-DC buck power converters. A disturbance compensation gain is constructed for the composite control algorithm to cancel the unmatched uncertainties in the output voltage channel. Rigorous criterion is provided to show the quantitative robustness between controller parameters and circuit uncertainties. The DOBC approach delivers not only a promising disturbance rejection performance but also a superior property of tracking performance recovery. The feasibility and efficiency of the proposed approach is validated by experimental results based on LabVIEW real-time control test setup. [ABSTRACT FROM AUTHOR]

Chain-link modular multilevel direct dc-dc converters (CLMMCs) have attracted much interest recently in for dc power systems because they achieve higher device utilization, lower power losses and they are physically more compact than the alternative front-to-front modular multilevel dc-ac-dc converters (FFMMCs). The CLMMCs rely on circulating an internal ac current to manage energy balance of the sub-module (SM) stacks but this current inevitably contributes to extra current stresses for circuit components and can also lead to excess reactive power circulation within the converter. This paper presents a circuit analysis that there exists a frequency value for the internal ac components that may minimize the current stresses and avoid excessive reactive power circulation. For illustration, the circuit analysis is applied to one of the base formats, the buck-boost CLMMC as an example. The key relationship between the CLMMC and the standard dc-ac modular multilevel converter is explored and established. The equivalent circuits for their dc and ac components with consideration of SM capacitance and SM voltage ripples are created and analyzed in detail, and a full derivation is provided for the specific ac frequency. From this example, this analytical method is extended and applied to other base formats of CLMMCs. The theoretical analysis and results are verified by a set of full-scale simulation examples and down-scaled experiments on a laboratory prototype. [ABSTRACT FROM AUTHOR]

This paper presents a galvanically isolated dc-dc converter with multi-channel communication exploiting a single isolation transformer. The proposed architecture makes compliant both regulated output power and data transmission on the same isolation physical link by using ASK modulation of the power signal and data/control signal multiplexing. The dc-dc converter consists of two integrated chips fabricated in 0.18- $\mu \text{m}$ BCD and 0.13- $\mu \text{m}$ CMOS technologies, respectively, along with a thick polyimide transformer chip able to comply with reinforced isolation requirements. The dc-dc converter delivers an isolated output power up to 50 mW at 3.3-V output voltage, while providing three data channels with a data rate up to 10 Mb/s. [ABSTRACT FROM AUTHOR]

In this paper, a piecewise quadratic slope compensation technique for eliminating subharmonic oscillations in dc-dc switching converters is studied. With this technique, a self-generated signal is used in the compensation scheme resulting in a naturally full duty cycle stability domain. The expression of the piecewise quadratic compensating signal within a switching cycle is derived. It is obtained that the steady-state value of the amplitude of this signal is the same as in the conventional linear slope compensation scheme that guarantees stability for all values of the duty cycle. However, in the piecewise quadratic scheme this is achieved without exact knowledge of the inductance value nor sensing the input and the output voltages. The stability of the converter under the considered compensation scheme is also guaranteed for all values of the duty cycle with voltage loop open. A boost converter under peak current mode control is used to validate the theoretical results both by numerical simulations and by experiments. Simulation results are analyzed and compared to the performances of the state-of-art techniques with voltage loop closed. [ABSTRACT FROM AUTHOR]

In this paper, we propose a new scheme to directly power a 4.9–5.6GHz LC oscillator from a recursive switched-capacitor DC-DC converter. A finite-state machine is integrated to automatically adjust the conversion ratio and switching frequency of the converter such that its DC output voltage is within ±5% of the desired 1V across input voltage range 1.3–2.2V and < 2mA load current conditions. A gate-driver circuit is embedded in each switch of the converter to guarantee constant on-resistance across PVT variations without sacrificing device reliability. Furthermore, a spur reduction block (SRB) is embedded in the oscillator to suppress the ripple induced spurs by stabilizing its tail current. Both the converter and the oscillator are implemented in 40-nm CMOS technology. The measured peak power efficiency of the converter is 87%, while its spot noise is < 1.5nV/ $\sqrt {\mathrm{ Hz}}$ , which does not degrade the phase noise of the oscillator. The SRB suppresses the spur to < −65dBc under the 30mVpp ripple of the converter. [ABSTRACT FROM AUTHOR]

It is essential to retain improved efficiency in a dc–dc converter over a wide load current range to extend the battery-life in portable devices. This requires a multi-mode controller, consisting of pulse-width-modulation (PWM) and pulse-frequency-modulation (PFM) schemes. However, existing approaches attempt to integrate structurally different controllers; thus it is difficult to achieve a seamless controller transition. While a digital platform offers controller configurations, it remains difficult to identify a suitable digital PWM/PFM technique and decide on its sampling mechanism to achieve stable behavior. This paper proposes a unified digital PWM/PFM scheme which shares a common digital PWM (DPWM) block and has the provisions for online controller configuration and automatic (switching) frequency adaptation. The proposed scheme retains improved efficiency over a wide operating range and inherently achieves seamless controller transitions. Further, a unified discrete-time framework is proposed for the analysis and design of the proposed multi-mode controller. Buck and boost converter prototypes are tested and the proposed controller is implemented using a field-programmable-gate-array device. [ABSTRACT FROM AUTHOR]

The output voltage regulation problem of a PWM-based dc-dc buck converter under various sources of uncertainties and disturbances is investigated in this paper via an optimized active disturbance rejection control (ADRC) approach. Aiming to practical implementation, a new reduced-order generalized proportional integral (GPI) observer is first designed to estimate the lumped (possibly time-varying) disturbances within the dc-dc circuit. By integrating the disturbance estimation information raised by the reduced-order GPI observer into the output prediction, an optimized ADRC method is developed to achieve optimized tracking performance even in the presence of disturbances and uncertainties. It is shown that the proposed controller will guarantee the rigorous stability of the closed-loop system, for any bounded uncertainties of the circuit, by appropriately choosing the observer gains and the bandwidth factor. Experimental results illustrate that the proposed control solution is characterized by improved robustness performance against various disturbances and uncertainties compared with traditional ADRC and integral model predictive control (MPC) approaches. [ABSTRACT FROM PUBLISHER]

An efficient micro-scale solar power management architecture for self-powered Internet-of-Things node is presented in this paper. The proposed architecture avoids the linear regulator and presents a complete on-chip switched capacitor-based power converter in order to achieve higher end-to-end efficiency. Unlike traditional architectures, where the harvested energy processes twice, the proposed architecture processes the harvested energy only once before it reaches to the load circuit, irrespective of the ambient conditions. The system efficiency has been improved by ~12% over the traditional architecture. The entire power management system has been designed using 0.18- \mu \textm CMOS technology node, and the circuit simulations demonstrate that the proposed architectural changes bring in a system efficiency of 82.4% under different light conditions. In addition to that, a hardware setup is created using commercially available ICs and photovoltaic cells, to validate that the proposed power management system is practically realizable. [ABSTRACT FROM PUBLISHER]

Energy harvesting is an emerging technology for powering wireless sensor nodes, enabling battery-free operation of these devices. In an energy harvesting sensor, a power management circuit is required to regulate the variable harvested voltage to provide a constant supply rail for the sensor circuits. The power management circuit needs to be compact, efficient, and robust to the variations of the input voltage and load current. A closed-form power expression and custom control algorithm for regulation of a switched-capacitor DC-DC converter with optimal conversion efficiency are proposed in this paper. The proposed regulation algorithm automatically adjusts both the voltage gain and switching frequency of a switched-capacitor DC-DC converter based on its input voltage and load current, increasing the power efficiency across a wide input voltage range. The design and simulation of a fully integrated circuit based on the proposed power managing approach is presented. This power management circuit has been simulated in a 0.25 \mum standard CMOS process and simulation results confirm that with an input voltage ranging from 0.5 V to 2.5 V, the converter can generate a regulated 1.2 V output rail and deliver a maximum load current of 100 \muA. The power conversion efficiency is higher than 74% across a wide range of the input voltage with a maximum efficiency of 83%. [ABSTRACT FROM AUTHOR]

In this paper, the start-up response of a digitally controlled dc-dc boost converter with a constant power load is studied. A mathematical expression of the system response during start-up is derived using a nonlinear averaged model. The time-domain response of the system during start-up when the converter is operating under current limitation mode is derived by analytically integrating the mathematical equations describing the dynamic behavior. Numerical simulations from a detailed switched model validate the theoretical results and a good agreement is obtained. A boost converter prototype is built to validate the theoretical finding and the numerical simulations. It is observed that even when the analysis and the simulation predict zero inrush current, the experimental circuit still exhibits an unsuitable initial current peak and an unacceptable transient response during start-up. This phenomenon is mainly attributed to the presence of an unavoidable delay due to the computation time required by the digital control platform. The resulting inrush current is more pronounced in the presence of nonlinear load such as a CPL and saturable inductor. Some solutions are proposed to mitigate the inrush current problems. Simulations results taking into account the delay and experimental measurements demonstrate the validity of the proposed solutions. [ABSTRACT FROM AUTHOR]

This paper presents a one-stage AC-DC voltage regulator with dual-output for inductively powered applications. In order to maximize the circuit performances, more than one independent regulated output voltage is often required to cater for different sub-modules in a system. The typical two-stage implementation which consists of a rectifier and a multiple-output DC-DC converter limits the overall power conversion efficiency of the receiver. A new architecture which is able to rectify and regulate two or more output voltages simultaneously in a single-stage is proposed and thereby improving the overall power conversion efficiency substantially. In addition, an energy-efficient control scheme is adopted to control the multiple switches in the architecture. Since no inductor is required in the proposed one-stage conversion structure, the cross-regulation problem that used to exist in a multiple-output switching converter has been eliminated. Apart from this, it is easier to be integrated with a system-on-chip (SoC) due to its minimized footprint. The tri-mode dual-output design was fabricated in standard $0.18~\mu \text{m}$ CMOS process. It delivers a maximum output power of 114mW. The measured peak power conversion efficiency is 91.7% at dual regulated output voltages of 1.8V and 2V. [ABSTRACT FROM AUTHOR]

High step-up conversion is an indispensable feature for the power processing of low voltage renewable sources in grid-connected systems. Motivated by this necessity, this paper presents a study on non-isolated dc-dc converters based on the conventional Boost converter that can provide such feature with high efficiency. By the topological variation and gain cell concepts, it is demonstrated that these converters can be treated as a unique generalized converter, called Boost Converter with Gain Cell (BCGC). The operating principle, the key waveforms and the components stresses of the BGCG are analyzed for the continuous-conduction mode, independently of the employed gain cell. A methodology to create the gain cells is developed from the combination of coupled inductors and voltage multiplier techniques. In order to verify the realized analysis, a 150 W prototype concerning to the proposed generalized converter and able to operate with several different gain cells is developed for the comparison between theoretical and experimental static gain results. [ABSTRACT FROM PUBLISHER]

In this paper the stability and sensitivity function of three basic dc-dc converter with the consideration of circuit parasitics has been analyzed for analog and digital controller implementation. The steady state and small-signal analysis has been used to derive the mathematical expressions for uniformly sampled voltage-mode controlled converters. The effect of digital controller using the ratio of sampling to carrier frequency has been analyzed. The sampling frequency limits the voltage gain in the stepped manner and also affects the stability of the digitally controlled converter. The sensitivity function has been defined for voltage gain with respect to various system parameters. The maximum affected regions on duty ratio scale with corresponding parasitic variable have been discussed. The detailed stability analysis has been carried out for digitally implemented three basic dc-dc converters, i.e., buck, boost, and buck-boost circuits. The analytical results are verified with the simulations performed in PSCAD/EMTDC. An FPGA controller is considered as digital controller for the dc-dc converter and verification of the results through experiment. [ABSTRACT FROM PUBLISHER]

We are considering the problem of controlling a DC-DC switched power converter of the Buck type. The converter involves an inherent control limitation; accordingly the control signal (duty ratio) can only take values in the interval (0, 1). In the relevant literature, such a physical control limitation is generally not taken into account when designing the converter regulators. This is only dealt with in the control implementation stage, placing an isolated limiter between the (linear) controller and the controlled system. Furthermore, the presence of such a limiter is generally ignored when analyzing the closed-loop control system. In the present paper, the control signal limitation is dealt with using a nonlinear regulator that involves an internal limiter. The resulting closed-loop control system is shown to be equivalent to a nonlinear feedback involving a linear dynamics block in closed-loop with a nonlinear static element. Using absolute stability tools, sufficient conditions are established for the involved feedback to be L2-stable. If these conditions are respected when choosing the control design parameters then the regulator meets its objectives (closed-loop stability and output reference tracking). It is worth noting that, though the focus is made on a specific power converter, the paper includes an important theoretical dimension that may be of general interest. [ABSTRACT FROM AUTHOR]

This paper presents a design procedure of high-frequency loosely inductive coupled wireless power transfer (LIC-WPT) system based on class-E^2 dc-dc converter, taking into account the power loss reduction of inverter, coupling part, and rectifier simultaneously. Analytical expressions including the dc-to-dc efficiency of the WPT system are derived and the efficiency deterioration mechanism is explained by the circuit model. Through the analytical expressions, the design procedure for satisfying both the class-E switching conditions and power loss reductions at the coupling part is proposed from the circuit-theory viewpoint. The class-E^2 WPT system designed by the proposed design procedure achieves high dc-to-dc efficiency at low coupling coefficient, in particular, compared with those designed by the previous design strategies. The validity and effectiveness of the proposed design procedure were confirmed by PSpice simulations and circuit experiments. [ABSTRACT FROM PUBLISHER]

A maximum-power-point-tracking DC-DC boost converter to harvest energy from sub-\muW power sources is presented. For available input-power levels below 1 \muW, voltage boosting is achieved by operating all circuits in the sub-threshold region, and by switching the DC-DC converter at tens of Hz, thereby reducing switching losses. The paper further explores the possibility of energizing the DC-DC inductor for an optimum duration, such that switching and resistive losses are minimized. The sub-\muW energy harvesting circuit uses an area of 0.2 mm^2 on a standard 180 nm CMOS process, and utilizes an auxiliary voltage source for start-up. The designed and fabricated system is more than 50% efficient when the available power is greater than 2 \muW. The circuit can harvest energy whenever the available power is more than 0.3 \muW. Efficiency at 0.3 \muW is 25%, at 0.5 \muW is 37% and at 1 \muW is 48%. The complete IC consumes 50 nA for internal operations and the input voltage can be as low as 70 mV. [ABSTRACT FROM PUBLISHER]

This paper presents a 100 mV input, 500 mV output single-inductor multiple-output (SIMO) based step-up dc-dc converter with adaptive gate biasing (AGB) technique implemented in 0.18 \mum CMOS technology for thermoelectric energy harvesting. The proposed AGB technique and near-threshold voltage (near-VTH) energy redistribution control (ERC) ensure high conversion efficiency over a wide range of load currents. The proposed method automatically reduces conduction and switching losses of power MOSFETs without the need for auxiliary power converters or additional off-chip inductors. The AGB technique reduces conduction and switching losses under heavy-load and light-load conditions, respectively. The experimental results show that the efficiency of the proposed converter is enhanced by 25.5% and 18% at output load currents of 1500 \muA and 50 \muA, respectively. The proposed step-up dc-dc converter achieves the lowest output voltage and provides the highest conversion efficiency of 83.4% to date in standard CMOS process for thermoelectric energy harvesting. [ABSTRACT FROM AUTHOR]

Power management of mobile digital systems-on-chip necessitates large voltage regulation performances. DC/DC converters used to supply digital cores are facing stringent constraints with respect to load transients, reference tracking and accuracy. The fast transient response offered by sliding-mode control is well suited to DC/DC converters with fast varying load. Fixed switching-frequency is also mandatory for EMI and noise related issues. Fixed-switching frequency sliding-mode control has been experimented as a multi-loop system. There is a necessity to investigate the stability when multi-loops interact and the parameter set for each loop is quite large. The paper details a methodology for the stability analysis of a frequency-controlled sliding-mode DC/DC converter. The proposed stability analysis takes the possible cross-interactions into account and can be used to optimise the DC/DC controller without the limitations of a non-interaction criterion. As a verification a DC/DC converter is implemented in CMOS 130 nm. Experimental results agree with the analysis main recommendations. [ABSTRACT FROM AUTHOR]

This paper proposes a systematic sizing methodology for switched-capacitor DC/DC converters aimed at maximizing the converter efficiency under the die area constraint. To do so, we propose first an analytical solution of the optimum switching frequency to maximize the converter efficiency. When the parasitic capacitances are low, this solution leads to an identical contribution of the switches and transfer capacitors to the converter output impedance. As the parasitic capacitances increase, the optimum switching frequency decreases. Secondly, optimum capacitor and switch sizes for maximum efficiency are provided. We show that the overdrive voltage strongly impacts the optimum switch width through the modification of their conductance. To support the sizing methodology, a model of the efficiency of switched-capacitor DC/DC converters is developed. It is validated against simulation and measurement results in 65 nm and 0.13 \mu\ m CMOS, respectively. The proposed sizing methodology shows how the converter efficiency can be traded-off for die area reduction and what is the impact of parasitic capacitances on the converter sizing. [ABSTRACT FROM AUTHOR]

Digital control of switching power converters is an area which has seen increased attention in recent years. However, quantization in the feedback loop from the analog-to-digital (A/D) converter and the digital pulse width modulator (DPWM) may cause limit cycle oscillations to manifest, which are generally seen as being undesirable. This paper presents an analysis of the limit cycle behavior found in a multiple-sampled digitally controlled buck converter. The limit cycles which may arise in the system are characterized and conditions to prevent these oscillations from occurring are presented. [ABSTRACT FROM AUTHOR]

The general structure of a multilevel multistate dc–dc converter is introduced, which is a hybrid between inductor-based (buck) converters and capacitor-based (switched capacitor) converters. The control of the new converter is hybrid between switched capacitor converters and buck converters, where the coarse tuning of the output voltage is achieved through the selection of an appropriate operating region similar to an SC converter, while fine tuning is achieved through the adjustment of a duty cycle value similar to a buck converter. A silicon implementation of a four-level four-state hybrid converter is presented as a specific example of the general hybrid converter structure. A new state interleaving technique was employed resulting in an increased effective switching frequency of the converter. Silicon measurements of the integrated four-level four-state converter on a 65-nm GF technology show that the converter can cover a wide range of output voltage values achieving a peak efficiency of 93% with a power density of 47 mW/mm2. The implemented converter attains a response time in the sub- ${\mu }\text{s}$ range with output voltage ripples below 50 mV. [ABSTRACT FROM AUTHOR]

In this paper, a single-chip 60-V battery charger prototype is presented. The newly proposed charge mode transition can ensure smooth transitions between incremental current (IC), constant current (CC), and constant voltage (CV) modes. The charger sources a current of 136 mA in CC mode and has an efficiency up to 92% during the charging sequence. Intentional saturation of both the IC and CV regulation loops ensure the stability of the charger throughout the charging sequence. Bonding PAD designed to remove the constraints on the aspect ratio of input transistors as a prevention of antenna effect is also disclosed. The proposed design has been implemented on silicon using the TSMC 0.25 μm 1-poly 3-metal bipolar-CMOS-DMOS (BCD) 60-V process. [ABSTRACT FROM PUBLISHER]

This paper presents a design-oriented analytical approach for predicting fast-scale instability in power electronics converters under voltage-mode control strategy. This approach is based on the use of the ripple amplitude of the feedback control voltage as an index for predicting subharmonic oscillations in these systems. First, the work revisits the stability analysis technique based on the nonlinear discrete-time model, demonstrating that the ripple amplitude can be included within the expression of the Jacobian matrix of this model, hence giving a mathematical support to extend the ripple index to more complex topologies. A simple but representative buck converter under voltage-mode control is used to illustrate the approach. Using the ripple-based index, closed-form expressions of stability boundaries are derived. Unlike other available results obtained from existing methods, the stability boundary, in this work is expressed analytically in terms of both power stage and controller design parameters. Moreover, one can determine how these parameters are involved in the closed form expressions and, furthermore, how each parameter affects the stability of the system. The approach is validated by numerical simulations from the state equations and also experimentally within a wide range of the design parameter space. [ABSTRACT FROM PUBLISHER]

Frequency characteristics of the total feedback loop of a current-mode buck DC-DC converter in the discontinuous conduction mode (DCM) are examined by formulating an equivalent small-signal transfer function using a proposed block structure that does not suffer direct influence from the current feedback. Utilizing this transfer function, it is clarified that the type of the compensation slope in a current feedback loop affects the loop frequency characteristics in DCM, and in terms of stability, high voltage gain and large 0-dB frequency bandwidth, the quadratic compensation slope is more effective than the linear compensation slope. The validity of the proposed block structure and formulations and the effectiveness of applying a quadratic compensation slope instead of a linear compensation slope in DCM are verified by comparing calculation results, SPICE simulation results and evaluation results using circuit and measurement data from an MOS current-mode buck DC-DC converter IC that had been previously fabricated. More than 10-dB higher voltage gain, three times larger 0-dB frequency bandwidth, more than 10-degree larger phase margin and faster recovery time in load current change are realizable in DCM compared with the case using a linear compensation slope. [ABSTRACT FROM AUTHOR]

We introduce the cyclic switched-capacitor dc–dc converter for single-input multiple-output power delivery. We focus on applications in stacked voltage domain (SVD)-based systems, and show that the cyclic architecture is robust to load current mismatches. We analyze such converters and give intuition for their power losses. We give experimental results from an SVD based power management integrated circuit (PMIC), designed and fabricated in a 130nm CMOS technology. The PMIC is a combination of a 2/3 stage reconfigurable cyclic SC dc–dc converter and a linear regulator. It can drive $3\times 3$ mA loads with the input supply voltage varying from 2.35–3.65V. [ABSTRACT FROM AUTHOR]

A sensor circuit to measure the output power of a dc–dc boost for photo-voltaic (PV) maximum power point tracking (MPPT) application is presented. The proposed approach obviates the need for a series current sense resistor and a complex current/voltage digitization and multiplication circuitry required for calculating power. Thereby, this technique does not require analog multipliers, analog-to-digital converters, digital signal processor, and FPGA, thus reducing the bill of material, silicon area, and power consumption of the overall system. Additionally, it provides the dc electrical isolation between the high output voltage of the boost converter and the low-voltage integrated CMOS power sensor circuit. The proposed power sensor circuit is implemented using a switched capacitor differentiator and a voltage-to-time converter. This approach results in lower complexity, lower silicon area, lower power consumption, and lower component count for the overall PV MPPT system. Designed in a 180-nm CMOS process, the circuit can operate with a supply voltage of 1.8 V. It achieves a power sense accuracy of 7.6%, occupies a die area of 0.0519 mm2, and consumes a power of 0.748 mW. [ABSTRACT FROM AUTHOR]

Traditional wireless power transfer (WPT) systems usually adopt the single-phase-shift (SPS) control method to maintain a constant output current or a constant output voltage for various applications. However, the current-stress on one side is much higher than that of the other side especially under operating conditions with high voltage conversion ratio and light-load. This phenomenon actually can be proven by the established mathematical model of the current-stress of WPT systems using SPS control. This large current-stress will damage power devices and lower the efficiency of WPT systems. In addition, it will result in an increase of system total cost because of the need for the devices with the higher volt-ampere rating. A control strategy based on dual-phase-shift control is developed for WPT systems with an active rectifier to reduce the maximum value of current-stresses on both sides as well as to maintain a constant output voltage or current. Consequently, the system efficiency can be improved compared to traditional WPT systems with SPS control. A scaled-down experimental prototype is constructed to verify the effectiveness of the proposed WPT topology and the control method. Experimental results show that the proposed method can reduce the maximum current-stress significantly and improve the system efficiency compared to traditional WPT systems under SPS control. [ABSTRACT FROM AUTHOR]

A built-in self-test (BIST) technique that enables tracking of loop parameters of integrated DC–DC converters without affecting the normal mode of operation is presented. A digital pseudo-noise based stimulus and a mixed signal cross-correlation based analysis technique is used to derive on-chip impulse response, with minimum computational requirements in comparison to a digital correlator approach. Using measured impulse response, open-loop phase margin and closed-loop unity-gain frequency are estimated within 5.2% and 4.1% error, respectively, for the load current range of 30 mA to 200 mA. Converter parameters, such as natural frequency, Q -factor, and center frequency are estimated within 3.6%, 4.7%, and 3.8% error, respectively, over load inductance of 4.7 \mu \text{H} to 10.3 \mu \text{H} , and filter capacitance of 200 nF to 400 nF. A 5 MHz switching frequency, 5 V to 8.125 V input voltage range, voltage-mode controlled DC-DC buck converter is designed for the proposed model reference based parametric and non-parametric BIST analysis. The converter output voltage range is 3.3 V to 5 V and supported maximum load current is 450 mA with a peak efficiency of 87.93%. The proposed converter is fabricated on a 0.6 \mu \textm 6 layer-metal SOI technology with a die area of 9 mm2. The system identification circuitry occupies 3.8% of the converter area with 530 \mu \textA quiescent current during operation. [ABSTRACT FROM PUBLISHER]

A method for large-signal behavior verification of power electronics dc-dc converters subject to uncertain variations in operating conditions is proposed. This method relies on the computation of the reach set, i.e., the set of all possible trajectories that arise from different initial conditions, unknown-but-bounded inputs, and inherent switching. Large-signal behavior verification is accomplished by checking that the reach set remains within the region of state space defined by performance requirements, e.g., output voltage tolerance specifications, component voltage and current limits. Algorithms to solve the reachability problem for power electronics converters operating under both open- and closed-loop control are provided along with simulations illustrating the proposed method. [ABSTRACT FROM PUBLISHER]

In this article, first integrated circuit (IC) implementation of parallel synchronized switching harvesting on inductor (p-SSHI) is presented for triboelectric energy harvester targeting 1 Hz to 5 Hz mechanical motions. It is accompanied by on-chip buck and switched capacitor DC-DC converters, all capable of handling 70 V levels. Unlike piezoelectric harvesters, triboelectric nanogenerators (TENGs) can produce very high open-circuit voltages; thus, the proposed system utilizes this property within the technology limits to maximize the extracted power. An in-house manufactured TENG using steel and polytetrafluoroethylene (PTFE) is modeled for sub-5 Hz motions. The energy is extracted and stored in an external capacitance until its voltage reaches 70 V, which is achieved in three press-and-release mechanical cycles. 70-to-2 V down conversion is carried on by 70-to-10 V buck converter followed by a 10-to-2 V switched capacitor DC-DC converter. A chip is manufactured in $0.18~\mu \text{m}$ HV BCD process with an active area of 6.25 mm2. End-to-end peak efficiency is measured as 32.71% for 1 Hz motion with a 722 $\mu \text{W}$ total power delivery to the load for 4 ms. [ABSTRACT FROM AUTHOR]

This article presents a compact power management solution for a pipeline analog-to-digital converter (ADC), employing only a switching-mode power converter. By directly powering the ADC using a boost DC-DC converter, the power delivery network (PDN) exhibits an overall-high power efficiency. The proposed foreground ADC calibration calibrates the ripple error induced from the power converter, which obviates the need for well-regulated supply and reference voltage offered by low-efficiency linear low-dropout regulators (LDOs). A chip integrates the boost DC-DC converter and the pipelined ADC with an external power inductor. The prototype, implemented in 65-nm CMOS, occupies 2.34-mm2 of total active area (9.4% - ADC, 2.6% - power controller and switches, and 88% - output capacitance). In the measurement, the boost converter, switching at 31.25MHz, converts a 0.5V input to 1.2V and delivers 22.8mW of power to the pipeline ADC. The boost DC-DC converter supplies all voltage domains, including analog/digital power supply and reference. The resulting overall system power efficiency is 78.6%. Sampled at 500MS/s, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 34.7/39.9dB without/with the ripple calibration for an input frequency of 177MHz, respectively. [ABSTRACT FROM AUTHOR]

This article presents guidelines for designing the power supply blocks of RF oscillators. To preserve their spectral purity, the requirements on the noise and ripple of the supply voltage are firstly evaluated based on the oscillator supply pushing factor and the oscillator Figure-of-Merit (FOM). Those specifications are then employed to design and estimate the power efficiency of an analog low-dropout regulator (LDO) and a switched-capacitor DC-DC converter. As a proof of concept, a 2:1 or 3:2 switched-capacitor DC-DC converter is implemented and directly connected to our previously published 4.9 – 5.5 GHz LC oscillator. The converter provides a 1V supply voltage with a noise ≤ 0.9nV/ $\sqrt {Hz}$ at 1MHz and does not affect the inherent phase noise of the oscillator. The ripple amplitude of the converter is 30mV while its effect is suppressed by the spur reduction block embedded in the oscillator. [ABSTRACT FROM AUTHOR]