Search

In this paper, the adaptive fuzzy control of switched stochastic nonlinear systems with set-time prescribed performance based on event-driven mechanism is studied. The creative part of this paper is that based on the set-time performance function, a modified event-triggered strategy that considers asynchronous switching to deteriorate system performance without strict assumptions is presented, which avoids Zeno behavior and saves communication resources. Then, by using backstepping recursive design technique, It $\hat {o}$ ’s differential lemma and mode-dependent average dwell time (MDADT) method, a novel adaptive performance control scheme is proposed, which can ensure that all the variables in the system are semiglobally uniformly ultimately bounded (SGUUB) in probability and the tracking error gets into prescribed boundary no later than an arbitrarily adjusted setting time. Finally, the proposed algorithm is applied to a RLC circuit and its practicability is verified via simulation results. [ABSTRACT FROM AUTHOR]

This paper studies stability of stochastic impulsive switched systems. Different from exponential Lyapunov function and average dwell-time in the previous works, general Lyapunov function and fixed dwell-time are implemented in this paper to analyze input-to-state stability and global stability of stochastic impulsive switched systems. Two cases are investigated, that is, the case that the continuous dynamics is stable and the case that the discrete dynamics is stable. To implement multiple Lyapunov functions, there are two subcases considered in this paper: the subcase that the estimates on the derivatives of the multiple Lyapunov functions are the same and the subcase that the growths of the multiple Lyapunov functions by the jumps are the same. For aforementioned different cases, sufficient stability conditions are established for stochastic impulsive switched systems. Finally, the developed theory is illustrated through examples from networked control systems and synchronization problem of 3-D novel chaotic circuit systems. [ABSTRACT FROM PUBLISHER]

In this paper, a novel class of quaternion-valued memristive neural networks (QVMNNs) that considers both the spatial factor and Markov jump phenomenon is proposed, the finite/fixed-time anti-synchronization (F/FTAS) of which is investigated. It is worth mentioning that the considered master and slave systems are assumed to jump along two inconsistent Markov chains, which is a first attempt at the issue of the anti-synchronization of Markovian systems and may be more realistic than most existing Markovian systems’ models. Then, a suitable feedback controller is designed, such that the error system can be finite/fixed-time stable. Moreover, by integrating algebraic inequality technologies and Lyapunov theory, a new F/FTAS theorem can be obtained for the proposed systems. Finally, this paper provides two examples, so that the rationality, superiority, and practical value of the main results can be illustrated. [ABSTRACT FROM AUTHOR]

Although the cyber-physical system stability is widely studied, scholars focus more on system stability with communication time delay. Therein, grid-connected inverters with the digital control system are regarded as one simplest and typical cyber-physical system. Meanwhile, the switching/sampling frequency of the inverter is always selected as low as possible from an efficiency viewpoint, resulting in unavoidable delay time. This delay time is apt to cause the system instability, which is more prone to severity under weak grid. To this end, this paper provides a minimum switching/sampling frequency for grid-connected inverters. Firstly, the system impedance model with equivalent delay time is constructed, which is based on padé approximate approach. This equivalent delay time consists of three parts, i.e., sampling delay time in cyber/physical level, calculation delay time in cyber level and pulsewidth modulation delay time in physical level, which reflects the cyber-physical interaction impact. Furthermore, the stability forbidden criterion is applied to make the switching/sampling frequency solving process become Hurwitz matrix identification problem through space mappings. Based on these space mappings, an adaptive step search approach is adopted to obtain the minimum switching/sampling frequency. Finally, the proposed approach can well evaluate the system stability under different frequencies through simulation and experiment. [ABSTRACT FROM AUTHOR]

This paper presents a low-power and area efficient 10-bit SAR ADC with higher side-reset-and-set (HSRS) switching scheme and hybrid capacitive-MOS (CAP-MOS) DAC. The HSRS switching scheme consumes zero switching energy for the two most-significant bits and skips unnecessary switching without using any auxiliary circuit. It is further verified in this paper that the HSRS switching scheme shows lower nonlinearity compared with the conventional CDAC structure with the same unit capacitor size and matching condition. This additional advantage permits using DAC topologies with lower total capacitance under given linearity requirement. A hybrid CAP-MOS DAC is adopted to reduce the total capacitance of the DAC, which consumes lower static current and chip area than the conventional hybrid capacitive-resistive DAC under the same settling requirement. The prototype 10-bit SAR ADC is implemented in a 0.18- $\mu \text{m}$ CMOS technology, showing an SNDR/SFDR of 56.43 dB/71 dB at 90-kHz input, under a 0.6-V power supply, while consuming $1.01~\mu \text{W}$ at 200 kS/s for a figure of merit of 9.32 fJ/conv.-step. The ADC occupies only a small active area of 0.0675 mm2. [ABSTRACT FROM AUTHOR]

In this paper, we propose a scheme to design the reconfigurable filtering power divider with arbitrary operating channels based on external quality factor ($Q_{\mathbf {e}}$) control. By using an input feeding line, ${n}$ resonators, and $m$ output feeding lines, the $n^{\mathbf {th}}$ -order $m$ -way filtering power divider topology can be obtained with a simple configuration. A coupled-line output feeding structure loading with multiple PIN diodes is proposed to adjust the output $Q_{\mathbf {e}}$ values. Design theories for obtaining the desired $Q_{\mathbf {e}}$ values are provided. Then, the filtering power divider can be fully reconfigured in the states with one to $m$ operating channels. Good input matching can be achieved without using an additional reconfigurable impedance matching network in all these states, resulting in a size and loss reduction. For verification, a 2nd-order 4-way reconfigurable filtering power divider is designed, fabricated, and measured. As compared to the reported reconfigurable power dividers, the proposed design shows the merits of fully reconfigurable operating channels, favorable filtering responses, low insertion losses, high isolation, and a simple structure. [ABSTRACT FROM AUTHOR]

This paper presents a 1.5-GS/s 6-bit single-channel loop-unrolled successive approximation register (SAR) analog-to-digital converter (ADC) using speculative capacitive DAC (CDAC) switching control technique. The proposed SAR ADC achieves a high sampling rate by eliminating additional delays in typical loop-unrolled SAR ADCs related to settling time constraints in their CDACs. Specifically, the CDACs are duplicated and controlled in speculative ways so that the CDAC outputs passage to their next values before completing the regeneration operation of comparators, thereby improving timing constraints for successive approximations. The switching power overhead from the CDAC speculation is mitigated by introducing an energy-efficient CDAC control technique that produces desired voltage transients with minimal power overheads. The prototype of the proposed SAR ADC is fabricated in a 28-nm CMOS technology and occupies an active area of 0.0038-mm2. The design consumes 5.8 mW from a 1.2-V supply. The ADC achieves 1.5-GS/s sampling frequency with a 31-dB SNDR at a low input frequency and a 28.6 dB at the Nyquist frequency without applying any offset calibration techniques, achieving the highest sampling frequency among the 6-bit single-channel loop-unrolled SAR ADCs reported. [ABSTRACT FROM AUTHOR]

This paper presents a single-stage tri-path buck converter with reduced inductor current and self-balanced flying capacitor voltage. The proposed converter introduces capacitor paths to reduce the average inductor current and inductor current ripple, hence decreasing the conduction loss. Operating with two states per conversion cycle, it exhibits a relatively low voltage conversion ratio of ${D}$ /(1 $+\,\,2{D}$). Besides, it realizes a self-balanced flying capacitor voltage in the charge redistribution phase. Similar to the conventional buck converter, the proposed converter in continuous-current mode only has two complex poles. Therefore, we design a Type-III compensator to obtain a good transient response. Moreover, the circuit does not require extra supplies for gate drivers due to the reutilization of the flying capacitor voltages, eliminating additional circuit and power overheads. The proposed converter, validated in a 65-nm standard CMOS technology, regulates a 0.7 V – 1 V output voltage from a 3.3 V – 4 V input voltage, delivering a maximum output power of 270 mW. The peak efficiency is 84%, with a switching frequency up to 5 MHz. [ABSTRACT FROM AUTHOR]

The search for a compatible application of memristor-CMOS logic gates has remained elusive, as the data density benefits are offset by slow switching speeds and resistive dissipation. Active microdisplays typically prioritize pixel density (and therefore resolution) over that of speed, where the most widely used refresh rates fall between 25–240 Hz. Therefore, memristor-CMOS logic is a promising fit for peripheral I/O logic in active matrix displays. In this paper, we design and implement a ternary 1–3 line decoder and a ternary 2–9 line decoder which are used to program a seven segment LED display. SPICE simulations are conducted in a 50-nm process, and the decoders are synthesized on an Altera Cyclone IV field-programmable gate array (FPGA) development board which implements a ternary memristor model designed in Quartus II. Our approach to logic synthesis demonstrates a potential way forward for simulating large-scale memristor-CMOS circuits without embedded RRAM for functional verification, and our SPICE results show an improvement in data density of a variety of decoders by a factor between 3.6-8.5. While the switching speed of memristors are one of several bottlenecks to using them in combinational logic, the comparatively slow refresh rates of typical microdisplays indicate this to be a tolerable trade-off, which promotes data density over speed. [ABSTRACT FROM AUTHOR]

This paper presents the theory of a novel memcomputing paradigm based upon a memristive version of standard Cellular Nonlinear Networks. The insertion of a nonvolatile memristor in the circuit of each cell endows the dynamic array with the capability to store and retrieve data into and from the resistance switching memories, obviating the current need for extra memory blocks. Choosing the parameters of each cell circuit so that the memristors may undergo solely sharp transitions between two states, each processing element may be approximately described at any time as one of two first-order systems. Under this assumption, the classical Dynamic Route Map may be employed to synthesise and analyse the data storage and retrieval genes. A new system-theoretic methodology, called Second-Order Dynamic Route Map, is also introduced for the first time in this paper. This technique allows to study the operating principles of arrays with second-order processing elements, as is the case, in the proposed network, if the set up of cell circuit parameters induces analogue memristive dynamics. This paper shows how the novel tool may be adopted to investigate the operating mechanisms of a cellular array with second-order cells, which compute the element-wise logical OR between two binary images. [ABSTRACT FROM AUTHOR]

This paper adopts a quantization-dependent Lyapunov function to study the output feedback stabilization problem of a switched system subject to output event-triggered sampling and quantization. First, a new event-triggered mechanism related to quantization parameters is proposed, which can obtain a trade-off between the event-triggered frequency and quantization density on the premise of ensuring asymptotic stability of the switched system. Moreover, sufficient conditions are obtained to ensure asymptotic stability of the switched system by a quantization-dependent Lyapunov function. Lastly, through a numerical simulation and PWM-driven boost converter system, we demonstrate the availability of the proposed quantization-dependent Lyapunov function and event-triggered mechanism methods based on quantization parameters, respectively. [ABSTRACT FROM AUTHOR]

The series-paralleling technique of dc-dc converters is utilized in various domains of electrical engineering for improved power conversion. Previous studies have proposed and classified the control schemes for the series-paralleled converters. However, they have several restrictions and lack diversity. The purpose of this paper is to propose passivity-based control (PBC) for the diverse output series-parallel connection of dc-dc converters. It is proved that the output series-paralleled converters regulated by PBC are asymptotically stable. The output series-paralleled converters are numerically simulated to confirm the asymptotic stability. PBC is shown to maintain the stability of the output series-paralleled converters with diverse circuit topologies, parameters, and steady-states. The result of this paper theoretically supports the numerical and experimental considerations in the previous studies and justifies the further extension of the series-parallel connection. [ABSTRACT FROM AUTHOR]

This paper presents a gate driver for a GaN-based half-bridge structure operating in a buck converter with input voltage >40 V or a boost converter with output voltage >30 V. Two 500 pF on-chip capacitors are utilized to construct three-level gate drivers, providing a near- $V_{{\text {DD}}}$ negative voltage for gate of the rectifier switch to eliminate the induced pulse on the gate from the high dv / dt slew rate of $V_{\text {X}}$ when the main switch is turned on. The dead time controller tunes the delay of the gate signal of the rectifier switch by sensing the slope of $V_{\text {X}}$ , thus the near-optimal zero-voltage switching can be achieved with deviation < 3 ns. The GaN driver is implemented with a 0.18- $\mu \text{m}$ BCD process. The efficiencies can be improved by 8.33% and 6.87% at light load in a buck and a boost converter due to the dead-time control. The peak efficiencies of 20 V–12 V and 12 V–18 V conversions are 86.37% and 84.39%, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a discrete-time low-noise amplifier for miniaturized sensor nodes. Such amplifier achieves a noise efficiency factor of 1.01 and a power efficiency factor of 1.63, improving the noise efficiency of an analog front-end. The proposed preamplifier employs discrete-time parametric amplification by modulating the capacitance of a MOS varactor. The sampling noise is minimized by adopting a high oversampling ratio of the input voltage, leading to an input-referred noise of 520 nVrms in a 1 kHz bandwidth. Also, the power consumption is reduced by using a 34-phase stepwise charging technique. The multiphase soft-charging technique is implemented using multiple time-interleaved cells and allows to significantly reduce the current consumption without introducing any significant penalty in terms of additional noise or area occupation. A two-stage parametric amplifier is introduced to provide higher gain, and suppress the noise contribution of the following amplifier chain. The proposed two-stage complementary preamplifier is followed by a third continuous-time stage, that employs a current-reuse inverter-based architecture. The contribution to the total noise efficiency factor of such amplifier is attenuated by the gain of the previous two-stage parametric preamplifier. As a result, the third stage provides gain programmability, while degrading the NEF of the entire chain by less than 10%. [ABSTRACT FROM AUTHOR]

In this paper, the finite-time sliding mode control issue is studied for a series of semi-Markov jump systems subject to actuator faults, where an asynchronous control method is adopted to overcome the non-synchronous phenomenon between the system mode and controller mode. Additionally, the event-triggered protocol, which determines whether the transmission of data should be performed according to the threshold condition, is introduced to alleviate the burden of data transmission in the communication channel. This paper aims to devise an asynchronous event-triggered sliding mode control law so as to guarantee the trajectories of the resulting closed-loop system can be forced onto the predefined sliding surface in a finite-time interval. Thence, by means of the mode-dependent Lyapunov functions and the finite-time theory, sufficient conditions are derived to assure that the closed-loop system is mean-square finite-time bounded in both reaching and sliding motion phases. Eventually, a numerical example and a tunnel diode circuit model are presented to illustrate the availability and practicability of the proposed approach. [ABSTRACT FROM AUTHOR]

This paper presents a nonlinear analytical model for an inverter-based switched-capacitor Class-D RF power amplifier (SCDPA). The root causes of the SCDPA AMAM and AMPM nonlinearities are studied. The major factors affecting SCDPA nonlinearities are identified as the unequal on-resistances of selected cell and unselected cell. Specifically, time-varying resistance of the switch, different transistor responses during the transition and parasitic resistance on the supply path (IR drop) are analyzed. Then, the system-level result, like EVM and power spectral density, can be obtained with nonlinear behavior of PA. The results of model calculation, schematic simulation, and measurement are presented and compared with validate the model both on transistor level and system level. This paper, for the first time, provides an accurate design guidance to enable fast architecture study and quick circuit-level prototype with close-to-optimum component initial parameters. It can be expanded to more architectures, therefore helps to pave the path to future design automation for highly linear SCDPAs. [ABSTRACT FROM AUTHOR]

This paper proposes a configurable direct digital frequency synthesizer (DDFS) based on the lookup-table (LUT)- rotation architecture. To break through the limitation of the single mode, the proposed DDFS is the first attempt which supports four-mode switching on chip. Taking the advantages of small LUT size and pipelined rotation, the DDFS achieves both high-speed and high-resolution properties. The multi-bit rotation tree is helpful to reduce the latency and register usage, which improves the agility and energy efficiency of the DDFS. A partition problem is raised in this paper, and we estimate the optimal solution through both the theory and experiment. Based on the partition, an output can achieve the highest spurious-free dynamic range (SFDR) with as small as possible LUT size. The functionality of the proposed DDFS has been validated in a Xilinx ZedBoard field-programmable gate array. The synthesis and layout results show that the chip achieves maximum 102-dBc SFDR and 2.2-GHz clock frequency. The power consumption and latency cycles reach minimum 6.9 mW/GHz and 7 cycles, which are 20% and 30% reduction compared with the state-of-the-art DDFS. [ABSTRACT FROM AUTHOR]

The performance of analog integrated circuits is often limited by the noise generated in its components. Several circuit techniques exist for mitigating the effects of the low-frequency noise. In this paper, a novel approach is described, which can also reduce even-order distortion, another major limitation of analog circuits. It may also allow the use of single-ended circuits in applications where usually differential structures are needed. In most cases, the resulting single-ended circuit will be much simpler than the fully or pseudo-differential one. It does not require common-mode feedback circuitry, nor single-ended-to-differential and differential-to-single-ended conversions at the input and output ports. The amplifiers may be single-ended, using, e.g., inverter-based circuits, and the use of baluns can be avoided. The number of pins and pads of the chip can be reduced. In addition, the single-ended opamps of the circuit may require less power than differential ones. These factors and the omission of the common-mode feedback circuits as well as the single-ended/differential converters will usually allow significant power savings. [ABSTRACT FROM AUTHOR]

To effectively use the network resources, a suitable event-driven communication scheme is proposed for the networked switched systems in this paper. Under the EDCS, a finite-time filter is designed for switched systems, which does not synchronize with the switched systems. Different from the existing finite-time problems, finite-time boundedness (FTBs) and input–output finite-time stability (IO-FTSy) are simultaneously considered in this paper. Some sufficient conditions are established to check the properties of the FTBs and the IO-FTSy of the event-driven asynchronous filtering error system by constructing a reasonable Lyapunov–Krasovskii functional and using the average dwell time approach. All the matrix inequalities can be converted to linear matrix inequalities so as to design the event-driven asynchronous filter. The applicability of the proposed filtering scheme is demonstrated via a mass-spring system model. [ABSTRACT FROM AUTHOR]

This paper addresses the consensus problem for two-layered MASs (multi-agent systems) subject to attacks on communication edges. Unlike most existing two-layered MAS models, the considered MASs are allowed to have heterogeneous inner communication topologies between the different layers. By using the linear transformation technique, some sufficient criteria are first given to achieve consensus among the leaders within the leader layer where the condition that the interaction topology has directed spanning trees with a fixed root required in most existing works has been removed. Furthermore, based on the relative outputs, observer-based controllers are designed to achieve node-to-node consensus among the two layers. By developing a new kind of multiple Lyapunov function (MLF) based on a bisection search method, some criteria are established under which the node-to-node consensus error will converge into a bounded set asymptotically. It is interestingly found that a less conservative average dwell time (ADT) constraint is obtained for achieving node-to-node consensus by utilizing the proposed MLF compared with that yielded by the traditional MLF constructed from nonsingular $M$ matrix theory. Moreover, we show that consensus can be achieved asymptotically in the layered MASs with the same inner topology subject to synchronous attacks under some suitable conditions. Finally, the effectiveness of the criteria is verified by simulation on networking linear oscillators. [ABSTRACT FROM AUTHOR]

This paper presents a multi-mode boost converter to achieve the high efficiency over a wide input voltage range for thermoelectric energy harvesting (TEH) applications. Under high, medium, and low input voltages, continuous conduction mode (CCM), critical conduction mode (CRM), and discontinuous conduction mode (DCM) are adopted to improve the conversion efficiency, respectively. Moreover, a constant peak current (CPC) control scheme is proposed to realize high efficiency under ultra-low input voltage. The proposed converter is implemented in a $0.18 \mu \text{m}$ standard CMOS process, which occupies a chip core area of about 1.0 mm $\times0.9$ mm. It achieves >60% efficiency in the range of TEG open-circuit voltage $V_{S}$ from 20 mV to 500 mV, and a peak efficiency of 91.4%. Moreover, after the startup is completed, an efficiency of 37.1% under the $V_{S}$ as low as 10 mV can be achieved. [ABSTRACT FROM AUTHOR]

This paper presents a foreground calibration method for both a sampler and a track-and-hold (T/H) buffer bandwidth mismatch in highly time-interleaved analog-to-digital converters (TI-ADCs). The T/H buffer bandwidth mismatch stems from the length difference of interconnect lines between the buffer and the channel ADC, while the sampler bandwidth mismatch arises from the mismatch in a switch and a sampling capacitor. To address both mismatches along with other mismatches residing in TI-ADCs, this papers utilizes least-squares (LS) minimization technique in order to extract mismatch parameters while injecting a sinewave at two distinct frequencies. Programmable capacitor arrays (PCAs) are used to tune the bandwidth of sampler, and correcting buffer bandwidth mismatch is performed in digital-domain. The method presented here is scalable to arbitrary number of interleaved paths, and can easily be combined with existing calibration methods for gain, offset, and timing-skew mismatches. Numerical experiment via Monte-Carlo simulations demonstrates significant performance improvement in the spurious-free dynamic range (SFDR) from 38 dB to 75 dB for a 32-channel time-interleaved ADC model that includes all major mismatches. [ABSTRACT FROM PUBLISHER]

This paper deals with the problem of observer-based fault estimation (FE) for discrete-time nonlinear systems via a weighted switching approach. A pair of variable weights is introduced in an efficient but straight-forward way, and thus, the space spanned by the prescribed normalized fuzzy weighting function can be divided into a set of non-overlapping subspaces. A new fuzzy switching FE observer is proposed by designing exclusive FE observer gain matrices for each non-overlapping subspaces, and thus, less conservative off-line designed conditions for the proposed fuzzy switching FE observer are obtained than the previous results by adequately taking advantage of the characteristic information of each non-overlapping subspaces. More importantly, the process of on-line deciding the current subspace’s index at each sampled point is very straightway and some previous time-consuming online operation is avoided, i.e., it can be said that the on-line computational burden also is alleviated in this paper. Finally, the proposed theoretical result is applied to a tunnel diode circuit and the advantages over existing literature are validated by means of objective comparisons. [ABSTRACT FROM AUTHOR]

Passively-integrated memristors are the most prospective candidates for designing high-speed, energy-efficient, and compact neuromorphic circuits. Despite all the promising properties, experimental demonstrations of passive memristive crossbars have been limited to circuits with few thousands of devices until now, which stems from the strict uniformity requirements on the IV characteristics of memristors. This paper expands upon this vital challenge and investigates how uniformity impacts the computing accuracy of analog memristive circuits, focusing on neuromorphic applications. Specifically, the paper explores the tradeoffs between computing accuracy, crossbar size, switching threshold variations, and target precision. All-embracing simulations of matrix multipliers and deep neural networks on CIFAR-10 and ImageNet datasets have been carried out to evaluate the role of uniformity on the accuracy of computing systems. Further, we study three post-fabrication methods that increase the accuracy of nonuniform 0T1R neuromorphic circuits: hardware-aware training, improved tuning algorithm, and switching threshold modification. The application of these techniques allows us to implement advanced deep neural networks with almost no accuracy drop, using current state-of-the-art analog 0T1R technology. [ABSTRACT FROM AUTHOR]

Aiming at a class of switched uncertain nonlinear strict-feedback systems under the action of average dwell time switching signal, this paper proposes a novel adaptive neural network output feedback tracking control based on the consideration of the full state constraints. The controller is proposed based on neural networks. One of the key characteristics of the system discussed is that the state variables cannot be measured and the system states need to be kept within the constraint ranges. For the sake of estimating the unmeasured states, the observer is constructed. In order to ensure all states which are within the time-varying boundary, the tangent barrier Lyapunov function (BLF-Tan) is selected in the design process. The boundedness of the closed-loop signals with average dwell time is guaranteed by the designed controllers and all the states limit in their constrained sets. It has been proved that the output tracking error converge to a small neighborhood of zero. In addition, the significance of the presented control strategy is verified and tested by a simulation example. [ABSTRACT FROM AUTHOR]

In this paper, the issue of open-switch faults of voltage source inverter (VSI) is studied, an adaptive fast voltage-based real-time open-switch fault location method is proposed. Firstly, for each switching period, the voltage deviation is calculated by the expected voltage and estimated actual voltage, they are obtained via the mixed logical dynamic model (MLDM) and measured currents, respectively. Then, the voltage deviation of each phase is employed as a fault variable. By this way, avoiding the use of additional hardware, and embedding easily in system. Furthermore, considering the impact of sampling error, parameter error, dead time, delay time, and transition time, the adaptive threshold is designed. Finally, simulations and experiments are executed to verify the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

Memristors have proven to be an attractive feature for memory, logic-in-memory, and neuromorphic computing. Recently, radio-frequency memristive switches (RFMSs) have exhibited promising high-frequency performance, opening the possibility of their use in radio-frequency integrated circuit applications. In this paper, we present two novel topologies of Tunable Inductors using MEmristors, the memristive–via the switched tunable inductor and the multi-layer stacked inductor switched by an RFMS single-pole double-throw. The two inductor topologies are fully passive and are tuned by electrochemical metallization memristors. Memristive devices improve the performance of tunable inductors, as they provide low-area overhead, low-energy switching, and non-volatility, resulting in more compact and energy-efficient devices. The topologies are implemented and simulated in a momentum 3-D planar electromagnetic simulator. Simulation results show a maximum tunability of 296%, a quality factor of 18 at 5 GHz, and self-resonant frequency above 8.4 GHz. [ABSTRACT FROM PUBLISHER]

We reconsider the black box model by Urbanek of electric-arc in air-blast circuit breakers or in circuit breakers characterized by an electro-negative gas (e.g., SF6) as quenching medium. It has the unique characteristic to account for the dielectric breakdown that possibly reignites the arc. We show some of its main features that have been almost hidden from the first publication of the model in the literature. The conductance in the Urbanek model plays two roles: 1) it effectively represents the conductance of the burning arc when positive and 2) it is a thermodynamic indicator when negative. This thermodynamic indicator is used to eventually trigger a restrike of the arc. We show that this switching behavior can be formally analyzed by considering the model as an hybrid dynamical system. In this paper, we reconsider it and show its main dynamic properties through some case studies. [ABSTRACT FROM PUBLISHER]

High performance mixed signal (HPMS) platforms require stringent overall system and subsystem performance. The ability to design ultra-low power systems is used in a wide range of platforms including consumer, mobile, identification, healthcare products and microcontrollers. In this paper we present an overview of low power design techniques, challenges and opportunities faced in an industrial research environment. The paper presents strategies on the deployment of low power techniques that span from power-performance optimization scenarios accounting for active and standby operation modes to the development of multi-core architectures suitable for low voltage operation. [ABSTRACT FROM AUTHOR]

Three types of bifurcations (instabilities) in the DC-DC converter under valley current mode control (VCMC) are analyzed, which is an extension of a recent paper on the peak current mode control (PCMC). The three bifurcations are border-collision, period-doubling, and saddle-node bifurcations. The corresponding critical (instability) conditions are derived. The derived conditions divide the parameter space into different operating modes. Contrary to the general belief that the critical conditions for VCMC and PCMC are symmetric with respect to the duty cycle D=1/2, most critical conditions are actually asymmetric. The dynamics symmetry is converter, bifurcation, loading, and parameter dependent, verified by bifurcation diagrams and time-domain simulations. The VCMC boost converter has rich dynamics and it is extensively analyzed. [ABSTRACT FROM AUTHOR]

This paper presents a novel static digital pre-distortion (DPD) method for a current-steering digital-to-analog converter (CS-DAC). The proposed method utilizes the knowledge of the current cell array architecture to calculate the static mismatch currents of the cells. The mismatch values are stored in memory and added to the original input code to generate the new pre-distorted input word. The converter corrects the static error with its own current cells without incorporating an additional calibration DAC (CALDAC) or programmable current sources. This results in a reduction in area, power and simulation run times because of the simpler circuit design. An Overflow-Cell-Selection (OCS) is introduced as a novel solution to further enhance the static linearity of the converter. It also can be implemented as a software solution for already existing DAC designs which do not have an integrated DPD and lab/measurement equipment (e.g., arbitrary wave generator (AWG)). This poses as a strong differentiation factor compared to other state-of-the-art static DPD methods. The evaluation of the proposed DPD is done via simulations in MATLAB and on- chip measurements with a 14-bit CS-DAC in 16 nm. Single tone measurements show a performance gain of the total harmonic distortion (THD) of 12 dB. [ABSTRACT FROM AUTHOR]

In this paper, a novel constrained switching rule, called “time-triggered logical switching” (TTLS) is considered for switched logical dynamic systems (SLDSs). Compared with the general time-triggered switching, the activation mode of TTLS cannot be arbitrary and is pre-allocated according to the logic operation, which is more practical. The TTLS is described as an LDS, and according to the characteristics of LDS, the stability analysis of SLDSs with TTLS is converted into the stability analysis of SLDSs under the logical switching cycle sequences. Firstly, based on the equivalent algebraic form of SLDSs with TTLS, combining the Lyapunov theory of LDS with average dwell-time method, several sufficient conditions are put forward for ensuring the point stability of the considered SLDSs. Then, by defining the switching cycle invariant subset and constructing a new system, the set stability analysis of the original system is transformed into the point stability analysis of the new system, and further, the obtained results for the point stability analysis are applied to the set stability analysis. At last, the validity of obtained results is illustrated by simulation on gene and protein signaling activity patterns. [ABSTRACT FROM AUTHOR]

High step-up converters are often used in photovoltaic applications due to low voltage of photovoltaic modules. In this paper, a study of several voltage step-up cells added on primary and secondary sides of an isolated dc-dc SEPIC (single ended primary inductor converter) is made, in order to increase its static gain and synthesize a family of converters. To perform this study and select the most appropriate resulting converter, theoretical and comparative analyzes are accomplished. They include a brief description of each converter, tables and curves with relevant information, such as voltage gain, voltage stresses and component count, and the identification of the use of coupled inductor or transformer based on the analysis of dc magnetizing current. Moreover, theoretical analysis and experimental results on a 50 kHz and 200 W prototype of selected isolated SEPIC with voltage doubler cell are presented to validate the proposed topology and concept. [ABSTRACT FROM AUTHOR]

Robustness to electromagnetic interference (EMI) is one of the primary design aspects of state of the art automotive ICs like System Basis Chips (SBCs) which provide a wide range of analog, power regulation and digital functions on the same die. One of the primary sources of conducted EMI on the Local Interconnect Network (LIN) driver output is an integrated switching DC-DC regulator noise coupling through the parasitic substrate capacitance of the SBC. In this paper an adaptive active EMI cancellation technique to cancel the switching noise of the DC-DC regulator on the LIN driver output to ensure electromagnetic compatibility (EMC) is presented. The proposed active EMI cancellation circuit synthesizes a phase synchronized cancellation pulse which is then injected onto the LIN driver output using an on-chip tunable capacitor array to cancel the switching noise injected via substrate. The proposed EMI reduction technique can track and cancel substrate noise independent of process technology and device parasitics, input voltage, duty cycle and loading conditions of the DC-DC switching regulator. The EMI cancellation system is designed and fabricated on a 180nm Bipolar-CMOS-DMOS (BCD) process with an integrated power stage of a DC-DC buck regulator at a switching frequency of 2MHz along with an automotive LIN driver. The EMI cancellation circuit occupies an area of 0.7 mm2, which is less than 3% of the overall area in a standard SBC and consumes 12.5 mW of power and achieves 25 dB reduction of conducted EMI in the LIN driver output’s power spectrum at the switching frequency and its harmonics. [ABSTRACT FROM AUTHOR]

Silicon Carbide (SiC) MOSFETs are usually paralleled to increase the current capability for high power applications. While, the asymmetrical parasitic parameters of the wide-used laminated busbar can cause current imbalance for paralleled MOSFETs. The fast switching of SiC devices can further deteriorate the imbalance. However, the complex current paths and their mutual effects are seldom considered and effectively modeled for the parasitics of the busbar, which is not accurate enough to evaluate the current imbalance for the busbar connected with SiC devices. This paper proposes accurate modeling of the effective parasitic parameter of laminated busbars with paralleled SiC MOSFETs. The model incorporates not only the self-inductance and resistance but also the complex mutual coupling effect of all the current paths. Moreover, a switching period is divided into two durations for accurate effective parasitic models, in which the busbar can have different effective models regarding one physical structure. Furthermore, for easy evaluation of the current balance, a single effective model, namely equivalent model, is derived for a physical structure by replacing the complex mutual network. A specific laminated busbar for EV inverter is analyzed to prove the above theory, which is validated by simulation and experiment separately. [ABSTRACT FROM AUTHOR]

This paper presents a full hardware implementation of a magnetic tunnel junction based stochastic tunable bitstream generator. It provides highly accurate control of the switching probability, while showing important robustness to process and temperature variations. We propose a new architecture of sensing scheme based on the pre-charged sense amplifier approach that uses an asynchronous digital module to control the internal signals of the sense amplifier with the purpose of improving the reliability against the timing hazards and reducing the power consumption by detecting the end of the reading to stop the required static currents. The circuit also features a digital feedback loop that analyzes the output bitstream and adapt the current in such a way that the bitstream encodes precisely the required probability. This circuit features an important bit generation rate at a low energy cost. Based on an exhaustive characterization of the circuit, we provide a behavioral description in Verilog, with timing and power files to be integrated as a standard cell in the digital design flow for application level evaluation of the performance. Thus, we also provide a design and evaluation flow from device to digital level of abstraction. [ABSTRACT FROM AUTHOR]

This paper investigates the fixed-time stabilization problem for a class of nonlinear systems via event-triggered control. The event-triggered mechanism can be applied to the nonlinear system with the coexistence of low-order and high-order nonlinearities. In order to deal with these low-order and high-order terms as well as achieve the objective of fixed-time stabilization, the initial value of the system is divided into two cases, and then the event-triggered controller is designed, respectively. By switching control theory, it is proved that the nonlinear system is globally fixed-time stable under the designed controller and the Zeno behavior can be excluded. Finally, two simulations show that the proposed technology is effective. [ABSTRACT FROM AUTHOR]

In this paper, we present a reconfigurable Physically Unclonable Functions (PUF) based on the Spin-Orbit-Torque Magnetic Random-Access Memory (SOT-MRAM), which exploits thermal noise as the true dynamic entropy source. Therefore, the MRAM cells could be configured to random final states with stochastic switching mechanism. The proposed PUF is constructed and reconfigured by combining the small-capacity true random number generator (TRNG) and high-reliability secure hash algorithm (SHA-512), realizing the dynamic transformation between SOT-MRAM based last level cache and PUF (In-Cache-MPUF). Thanks to the full reconfigurability and the high endurance of SOT-MRAM, the proposed In-Cache-MPUF can achieve $10^{\textbf {14}}$ maximum PUF bits per cell, which has greatly motivated the implementations compared with the traditional weak PUFs utilizing the static entropy source of process variations. The Monte-Carlo simulation results using 40 nm technology and a compact MTJ model show that the proposed PUF has desirable randomness as the digitized bit streams passing all the NIST tests, achieving 50.0428% uniqueness as well as 49.9236% uniformity. It also shows comparable reliability to the state-of-the-art works: a maximum bit error rate of 0.14% and 0.12% at 100 °C and 0.9 V, respectively. In addition, the system level performance is tested and validated by gem5. [ABSTRACT FROM AUTHOR]

This paper considers weakly and strongly input-to-state stability (ISS) of a discrete-time time-varying delayed system with synchronous impulses and switches. By employing the uniformly asymptotically stable function and mode-dependent dwell time conditions, ISS criteria are derived using the Krasovskii and Razumikhin techniques. The time differences of the Krasovskii functionals or the Razumikhin functions can be mode-dependent and time-varying, which release constraints of some existing results. As subsequent results, we apply the derived ISS criteria to the multi-agent systems (MASs). Finally, two examples considering the quasi-consensus of MASs are given to verify the established results. [ABSTRACT FROM AUTHOR]

Varactors in RF CMOS processes often have significantly lower Q- factor ($Q_{VAR}$) than inductors and transformers at mm-wave frequencies. Direct connection of varactors to the outputs of an LC oscillator lowers overall tank Q, $Q_{T} < Q_{VAR}$ , and at the same time, increases the ratio of parasitic capacitance to total tank capacitance which limits frequency tuning range (FTR). Instead, magnetically coupling a varactor to the oscillator core using an asymmetric transformer, where the core is connected to the primary and varactor to the secondary, limits the drop in $Q_{T}$. The ratio of parasitic capacitance to total tank capacitance is also reduced. The varactor can also be operated in accumulation-mode, with a larger $Q_{VAR}$. Thus, both FTR and phase noise (PN), in comparison to traditional tanks in LC VCOs, are improved simultaneously. In this paper, two VCO prototypes are implemented in 65-nm CMOS. A 60 GHz self-mixing VCO with a VCO core operating at 20 GHz shows an FTR of 18.5%, a PN of −92.5 dBc/Hz at 1 MHz offset, and an FoM $_{T}$ of −187.1 dBc/Hz. A 25 GHz VCO shows an FTR of 29.9%, a PN of −107.9 dBc/Hz at 1 MHz offset, and an FoM $_{T}$ of −194.2 dBc/Hz. [ABSTRACT FROM AUTHOR]

This paper presents a millimeter-wave wide tuning range voltage-controlled oscillator (VCO) incorporating two switchable decoupled VCO cores. When the first core is switched on producing the low frequency band (LFB) signal and the second core is off, the inductors of the second core are reused to create additional buffers that pass the LFB signal to the output buffers. The generated high frequency band (HFB) signals by the second core when turned on, are directly fed to the output buffers. Producing the outputs of both VCO cores across same terminals without utilizing active/passive combiners and coupled inductors will enhance the phase noise performance of the VCO, increase its output power, and reduce the chip size. Fabricated in a 65-nm CMOS process, the VCO achieves a measured wide tuning range of 26.2% from 54.1 to 70.4 GHz while consuming 7.4–11.2-mA current from 1-V power supply. The peak measured phase noise at 10-MHz offset is −116.3 dBc/Hz and the corresponding FOMT and FOM varies from −180.96 to −191.86 dB and −172.6 to −183.5 dB, respectively. The VCO core area occupies only $0.1 \,\, \times 0.395\,\,\mu \text{m}^{{2}}$. [ABSTRACT FROM AUTHOR]

This paper develops fundamental limits of digital phased arrays and proposes to use this as a map for the future technology investment in this area. Phased arrays, which are becoming ubiquitous in everything from vehicles, to communication systems including cell phones, to drones, satellites, and of course military applications. There is a recent trend toward digital phased arrays where each element in the antenna array is digitized. This allows monolithic integrated circuit integration as well as providing new capability due to digital signal processing. Digital phased arrays are increasingly being implemented with reconfigurable logic. Digitization and reconfigurability comes at a cost of power, which is increasingly becoming the limitation in these systems. This paper develops the fundamental energy limits of digital computation, applies this to phased arrays, and discusses directions for potential future digital phased array development. [ABSTRACT FROM AUTHOR]

The main focus of this paper is the evolution of complex behavior in a system of coupled nonlinear memristor circuits depending on the applied coupling conditions. Thereby, the parameter space for the local activity and the edge-of-chaos domain will be determined to enable the emergence of the pattern formation in locally coupled cells according to Chua’s principle. Each cell includes a Niobium oxide-based memristor, which may feature a locally active behavior once it is suitably biased on the negative differential resistance region of its DC current-voltage characteristic. It will be shown that there exists a domain of parameters under which each uncoupled cell may become locally active around a stable bias state. More specifically, under these conditions, the coupled cells are on the edge-of-chaos, and can support the static and dynamic pattern formation. The emergence of such complex spatio-temporal behavior in homogeneous structures is a prerequisite for information processing. The theoretical results are confirmed by measurements as well as by the numerical simulations of the accurate device and circuit models. [ABSTRACT FROM AUTHOR]

This paper presents a low-power and area efficient 10-bit successive approximation register (SAR) analog-to-digital (ADC) with a hybrid capacitive-MOS consisting of a 7-bit MSB capacitive DAC (CDAC) and a 3-bit LSB MOS DAC (MDAC), which consumes less power and much smaller chip area than a pure CDAC. Instead of using a string of eight MOS transistors to control one unit capacitor, the 3-bit LSB MDAC is realized by a MOS string with four native MOS transistors to control two unit capacitors, which allows higher voltage drop and more reliable operation for each unit MOS. The overall energy consumption of the proposed CAP-MOS DAC is reduced by 56.2% compared to a Vcm-based 10-bit pure CDAC with the same unit capacitance. Under the sampling rate of 200 kS/s, the prototype 10-bit SAR ADC implemented in a 0.18- ${\mu }\text{m}$ CMOS technology achieves a signal-to-noise-and-distortion ratio / spurious-free dynamic range of 56.91 /68.56 dB at 99-kHz input under a 0.6-V power-supply, while consumes $1.76~{\mu }\text{W}$ at 200 kS/s for a figure of merit of 15.38 fJ/step. The peak DNL and INL are +0.27/−0.21 LSB and +0.43/−0.45 LSB, respectively. The ADC occupies a small active area of 0.097 mm2. [ABSTRACT FROM AUTHOR]

The technology for oxide resistive memories offers nowadays a number of different implementations and solutions. As a consequence, many models have been presented so far, generally technology-specific, representing a problem for the memory design standardization. Moreover, the computational effort can be reduced using memristive models with lower complexity but that grant at the same time good speed and numerical stability. In this paper, the authors try to find a compromise between accuracy and computational costs, proposing a simulation procedure based on a linear approximation of the memristive device model. The description, formally derived from the traditional linear model, has been implemented in Verilog-A and, thanks to the analysis of practical design cases on a reference architecture, has been demonstrated to be useful in highlighting critical parasitic effects related to the interaction of the memristive cells with the memory circuit periphery. Thanks to the approximated method, a computer simulation time saving up to 40% is achieved when simulating a full cross-bar memory device. The model parameters have been extracted from experimental curves obtained from HfO2 devices implemented in a 250-nm BiCMOS IHP technology. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive analysis of the intrinsic losses in hybrid envelope tracking power supply modulators used in envelope tracking power amplifier systems. The losses are computed entirely symbolically in terms of system parameters and a single design parameter. Resulting formulations are used to provide design insight into optimum biasing to minimize losses in a hybrid configuration, and establish the theoretical upper bound of achievable efficiency. To illustrate the value of this analysis, a Rayleigh distributed waveform is used to evaluate the performance of the hybrid modulator to describe OFDM and other complex modulation schemes. This paper demonstrates that the common convention of biasing the linear converter’s output stage to have zero average current is generally suboptimal from a loss perspective, and establishes how efficiency can be improved without modifying the underlying circuit topology. These findings are validated with a series of simulations modeling a hybrid modulator implemented in a 180-nm CMOS process. This paper derives for the first time, the intrinsic theoretical losses in the hybrid envelope modulator configuration. [ABSTRACT FROM AUTHOR]

This paper analyzes the intermodulation between the element transition rate and the output-dependent unit switching distortion, i.e., the switching distortion of one switching unit, in current-steering digital-to-analog converters (DACs). The analysis and experimental results reveal how this intermodulation affects the DAC linearity. Based on this, we also propose a technique, termed random pairwise swapping (RPS) to improve the linearity of dynamic-element-matching-decoded DACs. Compared with existing techniques, RPS needs no half-cycle RZ operations and, thus, has no related vulnerabilities. In addition, the RPS could deal with the mismatch between different channels effectively. A 14-bit experimental DAC is fabricated in a 65-nm CMOS process. Measured results at 1.0-GS/s show above 72-dBc SFDR within 422-MHz bandwidth and 8–10-dB image tone suppression by the proposed RPS technique. At 3.0 GS/s, the SFDR is over 60 dBc within 600-MHz bandwidth. [ABSTRACT FROM AUTHOR]

This paper describes simple, analytical expressions for a quadrature passive-mixer-based RF bandpass filter. We have analyzed the passive mixer clocked by the trapezoidal-shaped local (LO) signals with different rise and fall times. Obtained results show that the partially overlapping LO signals and/or large capacitance of low-noise amplifier load cause charge reduction of each baseband branch capacitance. This results in the filter characteristics degradation. To achieve good filter characteristics, short rise and fall time of the LO signal and/or appropriate mixer RF-node biasing is effective. Our analysis results agreed well with the data obtained from the Advanced Design System simulator. [ABSTRACT FROM AUTHOR]

In this paper, a detailed analysis and comparison of nanoelectromechanical systems (NEMS) and CMOS technologies for low power adiabatic logic implementation is presented. Fundamental limits of CMOS-based adiabatic logic are identified. Analytic relations describing the energy-performance for sub-threshold adiabatic logic are also explicitly derived and optimized. The interest of combining NEMS technology and adiabatic logic is described, and the key NEMS switch parameters that govern the dissipation-performance relationship are identified as the switch commutation frequency, its actuation voltage, and the contact resistance between the switch electrodes. Furthermore, NEMS-based adiabatic gates architectures are described. Finally, the contribution of the power-clock or energy recovery generator is estimated in order to compare CMOS and NEMS-based adiabatic architectures at the system level. The paper concludes with a detailed comparison of the energy-performance of the different explored technologies. [ABSTRACT FROM AUTHOR]

This paper reports a calibration scheme that can be used to correct the inter-stage gain error in two-stage analog-to-digital converters (ADCs). We measure the static nonlinearity at the raw ADC outputs and compensate it through a feedback path to adjust the gain in the analog domain, which avoids the dynamic range loss in the conventional pure digital calibrations. The proposed scheme detects the error via the missing-code-occurrence probability (MCOP), which is insensitive to the comparator offset and has better immunity to its noise. Besides the gain error, we discuss other DAC linearity issues, such as the implementations of the reference buffer and the low-dropout (LDO) regulator. To verify the MCOP calibration, we design a 12-bit successive-approximation-register ADC, employing the bridge-DAC, in 65-nm CMOS. We integrate the ADC operating at 100 MS/s with the MCOP calibration, the reference buffers, and the LDO. The measurement results demonstrate the linearity enhancement after the proposed calibration, where we improve the signal-to-noise-and-distortion ratio to 61.38 dB, leading to a FoM of 16.7 fJ/conversion step at the Nyquist input frequency. [ABSTRACT FROM AUTHOR]