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A logic diagnosis procedure provides information about the defects that are present in a faulty unit as a set of candidate faults. To obtain smaller, and more accurate, sets of candidate faults, a diagnostic test generation procedure produces a test set that distinguishes fault pairs. This paper observes that large sets of candidate faults are obtained when multiple defects are present in a faulty unit, even if a diagnostic test set is used for logic diagnosis. This points to the possibility that fault pairs do not provide a complete set of targets for diagnostic test generation. This paper analyzes the conditions that cause a large set of candidate faults to be formed under a particular logic diagnosis procedure and suggests new targets for diagnostic test generation. The experimental results for benchmark circuits demonstrate that a diagnostic test set can be improved by adding diagnostic tests for the new targets. [ABSTRACT FROM AUTHOR]

Test generation procedures target a variety of fault models in order to produce test sets that are effective for defect detection. This paper considers the likely scenario where two-cycle skewed-load tests are generated to detect single transition faults, and the test set is complemented with tests for single stuck-at faults that are not detected by the transition fault test set. For this scenario, this paper makes several unique observations that can be utilized to produce a single compact test set that consists only of two-cycle skewed-load tests for both fault models. The first observation is that a single-cycle test for a stuck-at fault can be transformed into a skewed-load test that is guaranteed to detect the stuck-at fault without performing logic or fault simulation. The second observation is that skewed-load tests, which are transformed from single-cycle tests for stuck-at faults, sometimes detect more transition and stuck-at faults than tests that were generated for transition faults. The third observation is that a static test compaction procedure, which is based on the modification and removal of tests, is effective in this context because it allows tests for stuck-at faults to detect more transition faults and vice versa. This paper describes a test compaction procedure based on these observations and presents experimental results for benchmark circuits to demonstrate the effectiveness of the procedure. [ABSTRACT FROM AUTHOR]

Analyzing the timing properties of asynchronous systems is essential for characterizing their performance and power. Previous work on timing showed that such systems under and-causality and fixed delay exhibit periodicity properties. We give a different graph-based rigorous proof of the exact timing behavior of more general classes of such systems, and conclude their exact periodicity property, where each of the signal transition will occur with the same period after finite occurrences. We established our results under weaker assumption about system connectivity/topology, and this paper provides the theoretical foundation, for the exact periodicity property to be applied and exploited in circuits containing a combination of synchronous and asynchronous components. We provide simulation-based results for several typical asynchronous circuit topologies to quantify this time period in practical circuits. We also provide an extension of our analysis and methods to the case of bounded delay systems. A key result that is a consequence of our analysis is that asynchronous circuits can be integrated with synchronous logic via a metastability-free interface, thereby eliminating the high-overhead synchronizers when an asynchronous circuit is fully surrounded by synchronous logic. [ABSTRACT FROM PUBLISHER]

Two challenges are combined when compressed tests are computed for path delay faults: 1) path delay faults that are important to detect are associated with long paths, and many of these faults are undetectable and 2) it may not be possible to compress a given test for a path delay fault. This paper addresses these challenges in the context of test data compression methods that are based on a linear-feedback shift-register (LFSR). The basic approach that this paper uses modifies initially random seeds for the LFSR into seeds that produce tests for detecting target faults. This approach can find seeds even if the available tests cannot be compressed into seeds. In addition, the procedure described in this paper also selects detectable path delay faults to address the presence of undetectable path delay faults in the set of target faults. For this purpose it uses a metric that measures the similarity between target and detected path delay faults, and attempts to compute seeds that increase the values of this metric. Experimental results are presented to demonstrate the ability of the procedure to detect path delay faults in benchmark circuits. [ABSTRACT FROM AUTHOR]

A diagnostic test generation procedure targets fault pairs in a set of target faults with the goal of distinguishing all the fault pairs. When a fault pair cannot be distinguished, it prevents the diagnostic test set from providing information about the faults, and consequently, about defects whose diagnosis would have benefited from a diagnostic test for the indistinguishable fault pair. This is referred to in this paper as a diagnostic hole. This paper observes that it is possible to address diagnostic holes by targeting different but related fault pairs, possibly from a different fault model. As an example, this paper considers the case where diagnostic test generation is carried out for single stuck-at faults, and related bridging faults are used for addressing diagnostic holes. Considering fault detection, an undetectable single stuck-at fault implies that certain related bridging faults are undetectable. This paper observes that, even if a pair of single stuck-at faults is indistinguishable, a related pair of bridging faults may be distinguishable. Based on this observation, diagnostic tests for pairs of bridging faults are added to a diagnostic test set when the related single stuck-at faults are indistinguishable. Experimental results of defect diagnosis for defects that do not involve bridging faults demonstrate the importance of eliminating diagnostic holes. [ABSTRACT FROM AUTHOR]

In deep submicron nodes, the final design patterning quality depends profoundly on the optical proximity correction (OPC) quality. The required pattern fidelity and CD uniformity can never be achieved without good OPC. However, OPC runtime-resource factor has been exponentially increasing every technology node reaching alarming levels, where the OPC cost in terms of resources and turn-around-time is becoming very expensive. In this paper, we present a novel approach for speeding up the OPC convergence process using our model-based initial bias methodology. Our proposed methodology is based on building generic compact bias-models that can predict the final OPC shapes with a good accuracy using the optical simulation parameters. As a result, the OPC initial condition is much closer to the final solution and more than half of the OPC iterations can be saved as a result. In this paper, we present the details of our methodology and our compact initial-bias model we are proposing. We also present our testing results on a 10 nm metal level, where almost 50% of the OPC iterations could be saved when we apply our methodology. [ABSTRACT FROM AUTHOR]

Efficient performance modeling of today’s analog and mixed-signal circuits is an important yet challenging task, due to the high-dimensional variation space and expensive circuit simulation. In this paper, we propose a novel performance modeling algorithm that is referred to as Bayesian model fusion (BMF) to address this challenge. The key idea of BMF is to borrow the information collected from an early stage (e.g., schematic level) to facilitate efficient performance modeling at a late stage (e.g., post layout). Such a goal is achieved by statistically modeling the performance correlation between early and late stages through Bayesian inference. Furthermore, to make the proposed BMF method of practical utility, four implementation issues, including: 1) prior mapping; 2) missing prior knowledge; 3) fast solver; and 4) prior and hyper-parameter selection, are carefully considered in this paper. Two circuit examples designed in a commercial 32 nm CMOS silicon on insulator process demonstrate that the proposed BMF method achieves up to $9\times $ runtime speed-up over the traditional modeling technique without surrendering any accuracy. [ABSTRACT FROM AUTHOR]

This paper addresses theoretical aspects of arithmetic circuit verification based on algebraic rewriting. Its goal is to advance the understanding of algebraic techniques for arithmetic circuit verification in the context of symbolic computer algebra. The paper offers a new insight into the arithmetic circuit verification problem, by viewing the computation performed by the circuit as the flow of digital data. In the proposed bit-flow model, the circuit is modeled as a network of logic components satisfying a bit-flow conservation law. We prove that the value of the flow of data in the circuit is invariant throughout the circuit and use this to prove soundness and completeness of the rewriting technique, independently from the computer algebra arguments. The efficiency of the method is illustrated with impressive results for large integer multipliers. The verification system and benchmarks are offered in an open source software environment. [ABSTRACT FROM AUTHOR]

Energy management is a critical challenge in multicore processors due to continuous technology scaling. Previous methods have mostly focused on the energy minimization of the processor cores. However, energy overhead of the off-chip voltage regulator (VR) has recently shown to be a nontrivial part of the total energy consumption and has been previously overlooked. In this paper, we propose an overall energy optimization method for the system that minimizes both per-core energy consumption and VR energy consumption using dynamic voltage frequency scaling and VR phase scaling by solving a comprehensive convex model. In order to improve the accuracy of the task latency model, a new task model considering both computation and memory access of the task is also developed. Furthermore, for better scalability and lower online overhead, we decompose our proposed convex method into two stages: 1) an offline stage and 2) an online stage. During the offline stage, we explore the convex model by assuming different numbers of active phases of the VR, various workload pressures and workload characteristics to collect the optimal frequency assignments under different scenarios. During the online stage, the specific frequency assignment for cores and optimal active phase number of the VR are selected and applied based on the actual workload pressure and its characteristics running on the cores. Experiments on real benchmarks show that when compared with the state-of-the-art approaches, which are oblivious to VR overheads and exploit slack time to achieve energy minimization, our method can achieve a significant energy saving of up to 22.4% with negligible online overhead. [ABSTRACT FROM AUTHOR]

This paper proposes a novel memristor-based multiplexer implemented by using NOT-material implication. The proposed design can be extended to arbitrary ${N}$ -bit inputs and the enable-port can be added to improve its structure. Furthermore, this structure can be applied in the cascade circuit and crossbar array. A novel peripheral read circuit is introduced to overcome the problem that it is difficult to read out the operation results stored in crossbar array with large scales. The feasibility and correctness of our design is verified by the HSPICE simulation results with voltage threshold adaptive memristor model. [ABSTRACT FROM AUTHOR]

Exploring the design space of computer architectures generally consists of a trial-and-error procedure where several architectural configurations are evaluated by using simulation techniques. The final goal of the multiobjective design space exploration (DSE) process is the identification of architectural configurations optimal for a set of target objective functions, typically power consumption, and performance. Simulations are computationally expensive making it rather hard to efficiently explore the design space to identify high-quality configurations in an acceptable exploration time when relying solely on a single-core machine to run simulations. To tackle this problem, engineers proposed solutions based on either: 1) the use of approximate analytic performance models to prune the suboptimal regions of the design space by reducing the number of simulations to run or 2) the use of parallel computing resources to run different simulations concurrently. In this paper we demonstrate that, to efficiently speedup the DSE process while fully exploiting the parallel computing infrastructure, we need to combine the two techniques together in a structured manner. In this paper, we investigate this issue and we propose a DSE solution that exploits approximate analytic prediction models to improve the simulation schedule on a parallel computing environment rather than to prune the number of simulations. Experimental results demonstrate that the proposed technique provides a speedup from 1.26\boldsymbol \times to 4\boldsymbol \times with respect to other parallel state-of-the art DSE techniques. [ABSTRACT FROM PUBLISHER]

3-D integrated circuits (3-D ICs) are expected to have shorter wirelength, better performance, and less power consumption than 2-D ICs. These benefits come from die stacking and use of through-silicon vias (TSVs) fabricated for interconnections across dies. However, the use of TSVs has several negative impacts such as area and capacitance overhead. To predict the quality of 3-D ICs more accurately, TSV-aware 3-D wirelength distribution models considering the negative impacts were developed. In this paper, we apply an optimal buffer insertion algorithm to the TSV-aware 3-D wirelength distribution models and present various prediction results on wirelength, delay, and power consumption of 3-D ICs. We also apply the framework to 2-D and 3-D ICs built with various combinations of process and TSV technologies and predict the quality of today and future 3-D ICs. [ABSTRACT FROM PUBLISHER]

Scalable compact models for passive elements are important in the Analog/RF circuit design and optimization. Traditional scalable modeling methods are mainly physical and manual based methods, which usually require deep physical insight and extensive human intervention. In this paper, an automatic scalable compact modeling method for generic passive elements is established. The proposed method is a unified parameter extraction and scalable modeling scheme with novel inner-loop correlated parameter extraction and outer-loop adaptive boundary compression techniques. Experimental results show that both accuracy and scalability have been achieved by the proposed method for industrial inductors and transformers with an acceptable computational cost. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a novel Verilog-A based memristor model for effective simulation and application. Our proposed model captures desired nonlinear characteristics using voltage-based state control. This model is flexible and accurate, it can exhibit all the behaviors of HP memristive device and a general class memristive device resistive random access memory which is important in logic and memory design. Furthermore, we can antiserially connect two proposed models to capture the ideal I – V characteristics of complementary resistive switch (CRS). We demonstrate that our proposed CRS model-based crossbar arrays can significantly reduce sneak path currents with high noise margin compared to traditional memristor-based architectures. [ABSTRACT FROM AUTHOR]

A defect diagnosis procedure is an important part of the yield improvement process. As defects become more complex, the output responses they produce differ to larger extents from the output responses of modeled faults, and they become more difficult to diagnose. Biases in the defect diagnosis procedure can also cause defects to be more difficult to diagnose. It is important to study and remove such biases in order to ensure that they do not affect the accuracy of the procedure. This paper undertakes a study of the biases of a defect diagnosis procedure and suggests a way to improve it. The study illustrates an approach by which biases in defect diagnosis procedures can be analyzed in general. [ABSTRACT FROM AUTHOR]

The use of formal models to describe early versions of the structure and the behavior of a system has become common practice in industry. UML and OCL are the de-facto specification languages for these tasks. They allow for capturing system properties and module behavior in an abstract but still formal fashion. At the same time, this enables designers to detect errors or inconsistencies in the initial phases of the design flow—even if the implementation has not already started. Corresponding tools for verification of formal models got established in the recent past. However, verification results are usually not reused in later design steps anymore. In fact, similar verification tasks are applied again, e.g., after the implementation has been completed. This is a waste of computational and human effort. In this paper, we address this problem by proposing a method which checks a given implementation of a system against its corresponding formal method. This allows for transferring verification results already obtained from the formal model to the implementation and, eventually, motivates a new design flow which addresses verification across abstraction levels. This paper describes the applied techniques as well as their orchestration. Afterwards, the applicability of the proposed methodology is demonstrated by means of examples as well as a case study from an industrial context. [ABSTRACT FROM AUTHOR]

In order to perform accurate parasitic extraction, foundries must provide the cross section profile of devices, and IP vendors must provide sufficient layout information. However, foundries and IP vendors are increasingly reluctant to reveal such sensitive information, especially for advanced devices. Therefore, the industry is faced with the following challenges: 1) foundries/IP vendors need to protect their trade secrets; 2) electronic design automation vendors need to integrate foundry data into extraction tools; and 3) IC designers need to have the accurate parasitic data. In this paper, we propose an innovative and practical solution to these challenges, by building a macro model around any region in 2-D/3-D on a circuit where foundries or IP vendors wish to hide information, yet the macro model allows accurate capacitance extraction inside and outside of the region. We first give algorithms to construct the macro model. Then, we describe how existing extraction algorithms can interface with the macro model to perform extraction for the entire circuit at the same accuracy as if complete information was given. The macro model can be used in finite difference method/finite element method and floating random walk, due to an equivalence theorem we proved. Finally, we propose the concept of equivalent profile and describe how to find one based on the macro model. Experimental results show the macro model can be efficiently constructed and used to produce accurate capacitance extraction. [ABSTRACT FROM AUTHOR]

The random telegraph noise (RTN) is becoming more serious in advanced technologies. Due to the unpredictability of the physical phenomenon, RTN is a good randomness source for true random number generators (TRNG). In this paper, we build fundamental randomness models for TRNGs based on single trap- and multiple traps-induced RTN. We theoretically derive the autocorrelation coefficient, bias, and bit rate for RTN-based TRNGs. Two representative RTN-based TRNG schemes are simulated to verify the proposed randomness models. An oscillator-based TRNG is also studied based on the theoretical randomness model of multiple traps-induced RTN. We also provide basic guidelines for designing RTN-based TRNGs. [ABSTRACT FROM PUBLISHER]

The support for local variables in SystemVerilog assertions significantly enhances its expressive power. Handling local variables in analog and mixed-signal (AMS) extensions of assertion languages is tricky due to the dense time interpretation of AMS assertions, and has not been adequately treated in existing literature. This paper presents an approach for interpreting local variables in AMS assertions during simulation and a tool flow that works with standard mixed-mode simulators. [ABSTRACT FROM AUTHOR]

With the continuous drive toward integrated circuits scaling, efficient performance modeling is becoming more crucial yet more challenging. In this paper, we propose a novel method of hierarchical performance modeling based on Bayesian co-learning. We exploit the hierarchical structure of a circuit to establish a Bayesian framework where unlabeled data samples are generated to improve modeling accuracy without running additional simulation. Consequently, our proposed method only requires a small number of labeled samples, along with a large number of unlabeled samples obtained at almost no-cost, to accurately learn a performance model. Our numerical experiments demonstrate that the proposed approach achieves up to ${3.6 \times }$ runtime speed-up over the state-of-the-art modeling technique without surrendering any accuracy. [ABSTRACT FROM AUTHOR]

In current practice a formal analysis of hybrid system models is assertion-based. The work presented here is based on features that look beyond functional correctness toward a quantitative evaluation of behavioral attributes. A feature defines a real-valued evaluation function over a specific set of traces. This paper describes an improved method for the interpretation of features over hybrid automata models. It further demonstrates how satisfiability modulo theory solvers can be used for extracting behavioral traces corresponding to corner cases of a feature. Results are demonstrated on examples from the control and circuit domains. [ABSTRACT FROM AUTHOR]

Constructing algebraic polynomials using computer algebra techniques is believed to be state-of-the-art in analyzing gate-level arithmetic circuits. However, the existing approach applies algebraic rewriting directly to the gate-level netlist, which has potential memory explosion problem. This paper introduces an algebraic rewriting technique based on the and-inverter graph (AIG) representation of gate-level designs. Using AIG-based cut-enumeration and truth table computation, an efficient order of algebraic rewriting is identified, resulting in dramatic simplifications of the polynomial under construction. An automatic approach, which further reduces the complexity of algebraic rewriting by handling redundant polynomials, is also proposed. [ABSTRACT FROM AUTHOR]

This paper proposes a technique, GALAXY, to speed up multicircuit simulation, where each circuit under simulation is identical in schematic but different in some parameters. GALAXY is based on the successive chord method, where the inverse Jacobian matrix ( J ^-1 ) is reused to simulate many circuits whose solutions are similar. GALAXY also speeds up single-circuit simulation by reusing J ^-1 between consecutive time steps. Compared with a traditional Newton–Raphson (NR) simulator, on average, GALAXY reduces runtime of single-circuit and multicircuit simulation by 44% and 71%, without loss of accuracy. The number of NR iterations is reduced by 78%. [ABSTRACT FROM PUBLISHER]

In this paper, we propose SVR-NoC, a network-on-chip (NoC) latency model using support vector regression (SVR). More specifically, based on the application communication information and the NoC routing algorithm, the channel and source queue waiting times are first estimated using an analytical queuing model with two equivalent queues. To improve the prediction accuracy, the queuing theory-based delay estimations are included as features in the learning process. We then propose a learning framework that relies on SVR to collect training data and predict the traffic flow latency. The proposed learning methods can be used to analyze various traffic scenarios for the target NoC platform. Experimental results on both synthetic and real-application traffic demonstrate on average less than 12% prediction error in network saturation load, as well as more than $100\times $ speedup compared to cycle-accurate simulations can be achieved. [ABSTRACT FROM PUBLISHER]

Compact modeling of phase-locked loop (PLL) frequency synthesizer is proposed to reduce transient phase noise and jitter simulation time. Conventional small-signal noise assumption based frequency-domain simulation approach produces inaccurate results for nonlinear PLLs. Accurate analysis of nonlinear PLL are possible through time-domain, or transient noise simulation but time-domain simulation is computation-intensive and time-consuming. This paper presents a practical solution for transient phase noise and jitter analysis using compact modeling techniques. It features an autoregressive moving average process modeled voltage-controlled oscillator with fractional calculus and wavelet transform for phase noise decomposition and reconstruction, thereby reducing the phase noise and jitter simulation time to 25.8% of the transistor-level simulation with 0.4 dB @ 1 MHz phase noise error and 0.3 ps long-term jitter error for a 2 GHz PLL frequency synthesizer in a 65 nm CMOS process. [ABSTRACT FROM PUBLISHER]

This paper presents a new Property-Driven Design (PDD) method that starts from an abstract system model and integrates formal property checking early into a top-down design methodology for register transfer level (RTL) hardware. In PDD the role of formal verification is not limited to “bug hunting” alone. Instead, the formal techniques are applied in such a way that a formal relationship is provided between the abstract system model and its concrete implementation at the RTL. In order to avoid the high efforts associated with verification by property checking the proposed PDD approach automatically generates abstract properties from a system-level description and later refines them along the design process. The advantage of this methodology is to obtain a formally verified design at lower costs when compared to conventional design flows with property checking. The main benefit of the proposed approach results from the fact that a formally sound system model is available together with the RTL design. Specifically, LTL properties proven on the abstract model also hold on the concrete implementation. This facilitates many complex analysis and verification tasks in today’s design flows and contributes to emancipating system-level models from prototypes to golden design models. Several open-source and industrial case studies are reported that demonstrate the high potential of a PDD-based design paradigm. [ABSTRACT FROM AUTHOR]

Observation points in the combinational logic of a circuit can aid in the diagnosis of logic defects by reducing the number of indistinguished fault pairs. This paper considers the use of observation points in the combinational logic for the diagnosis of scan chain defects under an approach to test application called transparent-scan. Tests that are used for the diagnosis of scan chain defects include functional capture cycles that propagate the effects of scan chain faults through the combinational logic. Scan chain faults can thus be distinguished based on the values that are propagated in their presence to an observation point in the combinational logic. The procedure for observation point insertion considers the following parameters with respect to scan chain faults: 1) the number of indistinguished fault pairs and 2) the distances, measured in numbers of scan cells, between the faults that cannot be distinguished. With lower distances, a set of candidates for a faulty scan chain is likely to contain faults in the same vicinity of the scan chain. This facilitates failure analysis. Experimental results demonstrate the effectiveness of observation points in the combinational logic for scan chain diagnosis under transparent-scan. [ABSTRACT FROM PUBLISHER]

In this paper, a compact SPICE model of flexible transition metal dichalcogenide field-effect transistors (TMDFETs) is developed with considering effects when scaling the transistor size down to the 10-nm technology node. The model supports different transistor design parameters such as width, length, oxide thickness, and various channel materials, as well as the applied strain, which enables the evaluation of transistor- and circuit-level behavior under process variation and different levels of bending. Extensive device-level simulations are performed using this model, and TMDFETs are compared with different Si- and graphene-based devices. We performed circuit-level simulations, and reported the delay, power, and EDP of the benchmark circuits. Effects from process variation are also evaluated. These cross-technology studies show that TMDFET’s power is comparable to the low-power multigate devices (about 0.4% lower). The delay and EDP are 60% and 2.3% higher than the graphene-based devices, respectively. The developed compact model would enable SPICE-level circuit simulation for early assessment, design, and evaluation of futuristic TMDFET-based flexible circuits targeting advanced technology nodes. [ABSTRACT FROM AUTHOR]

Resistive switching devices are nonlinear electrical components that have drawn great attention in the design of new technologies including memory devices and neuromorphic circuits. In this paper, an SPICE implementation of a novel compact model is presented and put under test by means of different circuit configurations. The model is based on two identical opposite-biased diodes in series with a resistor where the switching behavior is governed by the creation and rupture of multiple conductive channels. Results show that the model is stable under different input sources and amplitudes and, with special interest, in multielement circuits. The model is validated with experimental data available in the literature. Both the corresponding SPICE code and schematic are provided in order to facilitate the model use and assessment. [ABSTRACT FROM PUBLISHER]

This paper proposes the use of coupled electric and magnetic circuits in the schematic models of high frequency integrated circuits, as an effective method to model the global inductive effects and coupling. These pairs of coupled circuits, called magneto-electro-equivalent circuit (MEEC) models, are obtained by partitioning the computational domain into several subdomains, each having its own electromagnetic field regime. The model reduction method we propose can be used not only to derive the full coupled electric and magnetic circuit model of a device starting from its layout, but also to correct the electric schematic by adding inductive parasitic effects. The MEEC approach uses special boundary conditions—called magnetic/electric hooks—on the interfaces between the subparts in which the computational domain is partitioned. The success of the correct extraction of inductive effects rely on the terminal reduction, i.e., the correct placement of magnetic hooks on the interfaces. In order to find this placement, a heuristic approach based on IC layout analysis is proposed. In order to consider the parasitic inductive couplings, the electric schematic circuit graph is enhanced with geometric information from the layout (e.g., node coordinates). The MEEC-based approach is validated for a real example of a low noise amplifier. Its initial layout design proved to be wrong only after the fabrication and characterization of the first prototype. The use of the inductive parasitic extraction tool, based on the MEEC approach, would have prevented this. MEEC is an alternative approach to vector potential equivalent circuit, with respect to which advantages and disadvantages are discussed. [ABSTRACT FROM PUBLISHER]

Leakage power is becoming significant in new generation IC chips. As leakage power is nonlinearly related to temperature, it is challenging to manage the thermal behavior of today’s multicore systems, since thermal management becomes a nonlinear control problem. In this paper, a new predictive dynamic thermal management (DTM) method with neural network thermal model is proposed to naturally consider the inherent nonlinearity between leakage and temperature. We start with analyzing the problems of using recurrent neural network (RNN) to build the nonlinear thermal model, and point out that there is exploding gradient induced long-term dependencies problem, leading to large model prediction errors. Based on this analysis, we further propose to use echo state network (ESN), which is a special type of RNN, as the leakage-aware nonlinear thermal model. We theoretically and experimentally show that ESN achieves much higher accuracy by completely avoiding the long-term dependencies problem. On top of this nonlinear ESN thermal model, we propose a novel model predictive control (MPC) scheme called ESN MPC, which uses iterative steps to find the optimal future power recommendations for thermal management. Being able to consider the leakage-temperature nonlinear effects and equipped with advanced control technique, the new method achieves an overall high quality temperature management with smooth and accurate temperature tracking. The experimental results show the new method outperforms the state-of-the-art leakage-aware multicore DTM method in both temperature management quality and computing overhead. [ABSTRACT FROM AUTHOR]

Analog/RF built-in test (BIT) techniques are essential for reducing the very high costs of specification-based tests and for high-safety applications. The adoption of a BIT technique needs to be decided at the design stage, and this can be facilitated by estimating the test quality in terms of errors such as test escapes (${T_{E}}$) and yield loss (${Y_{L}}$). Test quality estimation at the design stage has been traditionally very difficult for analog/RF circuits due to the lack of fault models that properly cover parametric faulty behavior. In recent years, statistical simulation has been considered in combination with learning techniques for the estimation of parametric test metrics. Extreme value theory (EVT) has provided a rigorous tool for the computation of parametric test metrics. However, test metrics estimation has been limited to the use of a univariate model. In this paper, we extend this approach by using a multivariate extreme value model. We illustrate this for the evaluation of an RF LNA BIT technique using a bivariate model. [ABSTRACT FROM AUTHOR]

Formal methods are a promising alternative to simulation-based verification of mixed-signal systems. However, in practice, such methods fail to scale with heterogeneity and complexity of today’s analog/mixed-signal systems. Furthermore, it is unclear how they can be integrated into existing verification flows. This paper shows a path to overcome these obstacles. The idea is to use a hierarchical verification flow, in which components can be verified by formal methods or by multirun simulation. To transport verification results across hierarchies, we represent parameters and properties by affine arithmetic decision diagrams. We study to which extent this approach fulfills the needs of practical application by the verification of a phase-locked loop of an IEEE 802.15.4 transceiver system. [ABSTRACT FROM AUTHOR]

Current and future multicore architectures can significantly accelerate the performance of test automation procedures depending on the underlying architecture and the scalability of their algorithms. This paper proposes a new parallel methodology targeting the fault simulation problem, for shared memory multicore systems, that maintains scalability with the increase of the number of cores. The method is based on a simple single thread process that allows focusing on the optimization of the parallelization process in different dimensions. Additionally, a number of optimizations are incorporated in the approach to control fault dropping and to avoid unnecessary work. The reported experimental results, for both random and deterministic test sets, demonstrate the scalability of the method. As the number of cores increases, the reported speed-up increases proportionally, where comparable recent methods report saturation or even reduction of the obtained speed-up. [ABSTRACT FROM AUTHOR]

Active cell balancing improves the performance of a battery pack by transferring charge from one cell to another. Associated design questions require multiple simulations with 100 cells over several hours. Since the most efficient transfer methods switch between phases in the kilohertz range, these simulations require high computational effort or reduced accuracy. To enable detailed analysis on a large scale, this paper includes state-of-the-art electrical battery models in active balancing simulation while keeping the computation effort for one transfer in the low millisecond range. This is achieved in three steps. First, we model the dynamics of each transfer phase using standard equivalent circuit abstraction. Next, we find closed form equations for the so-defined phase dynamics, yielding an iterative approach that saves computation time by replacing the numerical solver. Finally, we employ error control techniques to aggregate phases in that iteration, systematically reducing the millions of phase evaluations that would be necessary otherwise. Our experiments show that the speedup from equivalent circuit dynamics to error-controlled aggregation almost reaches five orders of magnitude while introducing virtually no additional error. This enables simulations of realistic balancing scenarios in less than a second and is hence suitable for design space exploration. [ABSTRACT FROM PUBLISHER]

With ever increasing design complexities, traditional cycle-accurate or instruction-set simulations are often too slow or too inaccurate for system prototyping in early design stages. As an alternative, host-compiled or source-level software simulation has been proposed, but existing approaches have largely focused on timing simulation only. In this paper, we propose a novel source-level simulation infrastructure that provides a full range of performance, energy, reliability, power and thermal (PERPT) estimation. Using a fully automated, retargetable back-annotation framework, intermediate representation code is statically annotated with timing, energy and resource accesses information obtained from low-level references at basic block granularity. The annotated model is natively compiled and combined with a cache model and occupancy analyzer to provide target performance, energy, soft-error vulnerability and power estimations. Finally, generated power traces are fed into thermal models for further temperature estimation. Comprehensive evaluations of our source-level models for PERPT estimations are performed. We applied our approach to PowerPC targets running various industry benchmark suites. source-level simulations are evaluated for different PERPT metrics and with cache models at various levels of detail to explore the speed and accuracy tradeoffs. More than 90% accuracy can be achieved for timing, energy, reliability and power estimation, and an average error of 0.05 K exists in steady-state thermal estimation. Simulation speeds range from 180 to 5740 MIPS for different types of metrics at different abstraction levels. [ABSTRACT FROM AUTHOR]

With the reduced noise margin brought by relentless technology scaling, power integrity assurance has become more challenging than ever. On the other hand, traditional design methodologies typically focus on a single design layer without much cross-layer interaction, potentially introducing unnecessary guard-band and wasting significant design resources. Both issues imperatively call for a cross-layer framework for the co-exploration of power delivery (PD) and system architecture, especially in the early design stage with larger design and optimization freedom. Unfortunately, such a framework does not exist yet in the literature. As a step forward, this paper provides a run-time simulation framework of both PD and architecture and captures their interactions. Enabled by the proposed recursive run-time PD model, it can achieve smaller than 1% deviation from SPICE for an entire PD system simulation. Moreover, with seamless interactions among architecture, power and PD simulators, it can simulate actual benchmarks within reasonable time. The experimental results of running PARSEC suite have demonstrated the framework’s capability to discover the co-effect of PD and architecture for early stage design optimization. Moreover, it also shows multiple over-pessimism in traditional PD methodologies. Finally, the framework is able to investigate the impact of dynamic noise on system level oxide breakdown reliability and shows 31%–92% lifetime estimation deviations from typical static analysis. [ABSTRACT FROM AUTHOR]

Radiation-induced single event transients (SETs) are expected to evolve to single event multiple transients (SEMTs) due to the downscaling of transistor feature size, which also increases the difficulty of the vulnerability estimation for large-scale digital integrated circuits. In this paper, a novel layout-based soft error vulnerability estimation approach which is termed LBSEVEA is proposed to evaluate the impact of heavy ions on the vulnerability of combinational circuits. The physical process of interaction between particles and devices, especially nuclear reaction and scattering process are included in the LBSEVEA. In addition, ambipolar diffusion and bipolar amplification effect, which induce additional charge collection of the adjacent transistors and the hitting transistor, are also considered. A new method calculating the collected charge induced by the bipolar amplification effect is presented. By introducing the layout information of the target circuits into the identification of the adjacent cells, SEMTs effect can be considered in the vulnerability estimation. A fast SPICE simulation tool is adopted to conduct the fault injected netlist simulations, which can make a favorable compromise between the consumption of computer resources and simulation precision. Furthermore, induced soft error numbers, distributions of charge collected by the hitting nodes and the adjacent nodes, and SET pulse width distributions are presented. Besides, heatmaps of induced pulse widths for the layout of two benchmark circuits are provided. Finally, the constraints, the flexibility, and the scalability of the LBSEVEA are discussed. The ability to estimate the impact of process variations on the vulnerability is also presented. Compared with simulation and experimental results, the LBSEVEA can fairly estimate the vulnerability of combinational circuits. [ABSTRACT FROM AUTHOR]

Quantum computation is a promising emerging technology which, compared to conventional computation, allows for substantial speed-ups, e.g., for integer factorization or database search. However, since physical realizations of quantum computers are in their infancy, a significant amount of research in this domain still relies on simulations of quantum computations on conventional machines. This causes a significant complexity which current state-of-the-art simulators try to tackle with a rather straight forward array-based representation and by applying massive hardware power. There also exist solutions based on decision diagrams (i.e., graph-based approaches) that try to tackle the exponential complexity by exploiting redundancies in quantum states and operations. However, these existing approaches do not fully exploit redundancies that are actually present. In this paper, we revisit the basics of quantum computation, investigate how corresponding quantum states and quantum operations can be represented even more compactly, and, eventually, simulated in a more efficient fashion. This leads to a new graph-based simulation approach which outperforms state-of-the-art simulators (array-based as well as graph-based). Experimental evaluations show that the proposed solution is capable of simulating quantum computations for more qubits than before, and in significantly less run-time (several magnitudes faster compared to previously proposed simulators). An implementation of the proposed simulator is publicly available online at http://iic.jku.at/eda/research/quantum_simulation. [ABSTRACT FROM AUTHOR]

Recent developments in formal verification of arithmetic datapaths make efficient use of symbolic computer algebra algorithms. The circuit is modeled as an ideal in polynomial rings, and Gröbner basis (GB) reductions are performed over these polynomials to derive a canonical representation. As they model logic gates of the circuit, the ideals comprise largely of Boolean (or pseudo-Boolean) polynomials. This paper considers a logic synthesis analogue of GB reductions over Boolean polynomials, by interpreting symbolic algebra as the unate cube set algebra over characteristic sets. By representing Boolean polynomials as characteristic sets using zero-suppressed binary decision diagrams (ZDDs), implicit algorithms are efficiently designed for GB-reduction for datapath circuits. We show that the imposition of circuit-topology-based monomial orders exposes a special structure on the ZDD representation of the polynomials. The subexpressions employed in the GB-reduction are readily visible as subgraphs on the ZDDs, which are directly used to compose the result. Our division algorithms effectively cancel multiple monomials implicitly in one-step, simplify the search for divisors, and avoid intermediate size explosion. Experiments performed over various finite field arithmetic architectures demonstrate the efficiency of our algorithms and implementations; our approach is orders of magnitude faster as compared to conventional methods. [ABSTRACT FROM AUTHOR]

Current nanometer CMOS circuits show an increasing sensitivity to deviations in first-order parameters and suffer from process variations during manufacturing. To properly assess and support test validation of digital designs, low-level fault simulation approaches are utilized to accurately capture the behavior of CMOS cells under parametric faults and process variations as early as possible throughout the design phase. However, low-level simulation approaches exhibit a high computational complexity, especially when variation has to be taken into account. In this paper, a high-throughput parallel fault simulation at switch level is presented. First-order electrical parameters are utilized to capture CMOS-specific functional and timing behavior of complex cells allowing to model faults with transistor granularity and without the need of logic abstraction. Furthermore, variation modeling in cells and transistor devices enables broad and efficient variation analyses of faults over many circuit instances for the first time. The simulation approach utilizes massive parallelization on graphics processing units by exploiting parallelism from cells, stimuli, faults, and circuit instances. Despite the lower abstraction levels of the approach, it processes designs with millions of gates and outperforms conventional fault simulation at logic level in terms of speed and accuracy. [ABSTRACT FROM AUTHOR]

Energy optimization is one of the most critical objectives for the synthesis of multiprocessor system-on-chip (MPSoC). Besides, to ensure a long processor lifetime and to maintain a safe chip temperature are also important for multiprocessor manufactures under deep submicrometer process technologies. This paper presents a mixed integer linear programming (MILP) model to determine the mapping and scheduling of real-time applications onto embedded MPSoC platforms, such that the total energy consumption is minimized with the lifetime reliability constraint and the temperature threshold constraint satisfied. We develop a lightweight temperature model that can be integrated in the MILP model to predict the chip temperature accurately and efficiently. By exploiting the dynamic voltage and frequency scaling capability of modern processors, processor voltage/frequency assignment is also considered in our MILP model. Extensive performance evaluations on synthetic and real-world applications demonstrate the effectiveness of the proposed approach. Our MILP model achieves an average reduction of 19.09% and 28.53% total energy in comparison with two state-of-the-art techniques on the basis of guaranteeing the safe chip temperature and system lifetime reliability. [ABSTRACT FROM AUTHOR]

Recent advancements in the development of memristive devices has opened new opportunities for hardware implementation of new computing models. Researchers have shown the suitability of memristive devices for swarm intelligence algorithms to solve a maze in hardware. In this paper, we utilize swarm intelligence of memristive networks to perform image edge detection. First, we propose a hardware-friendly algorithm for image edge detection based on ant colony optimization. Second, we implement the image edge detection algorithm using memristive networks. Furthermore, we explain the impact of various parameters of the memristors on the efficacy of the implementation. Our results show 28% improvement in the energy compared to a low power CMOS hardware implementation based on stochastic circuits. Furthermore, our design occupies up to $5\boldsymbol \times $ less area. [ABSTRACT FROM AUTHOR]

Modern system-on-chip (SoC) designs comprise programmable cores, application-specific accelerators, and I/O devices. Accelerators are controlled by software/firmware and functionality is implemented by this combination of programmable cores, firmware, and accelerators. Verification of such SoCs is challenging, especially for system-level properties maintained by a combination of firmware and hardware. Attempting to formally verify the full SoC design with both firmware and hardware is not scalable, while separate verification can miss bugs. A general technique for scalable system-level verification is to construct an abstraction of SoC hardware and verify firmware/software using it. There are two challenges in applying this technique in practice. Constructing the abstraction to capture required details and interactions is error-prone and time-consuming. The second is ensuring abstraction correctness so that properties proven with it are valid. This paper introduces a methodology for SoC design and verification based on the synthesis of instruction-level abstractions (ILAs). The ILA is an abstraction of SoC hardware which models updates to firmware-visible state at the granularity of instructions. For hardware accelerators, the ILA is analogous to the instruction-set architecture definition for programmable processors and enables scalable verification of firmware interacting with hardware accelerators. To alleviate the disadvantages of manual construction of abstractions, we introduce two algorithms for synthesis of ILAs from partial description called templates. We then show how the ILA can be verified to be correct. We evaluate the methodology using a small SoC design consisting of the 8051 microcontroller and two cryptographic accelerators. The methodology uncovered 15 bugs. [ABSTRACT FROM AUTHOR]

Adiabatic logic is an energy-efficient technique, however, the time required in the design, validation, and debugging increases manifold for large-scale adiabatic system designs. In this endeavor, we present a hardware description language (HDL)-based modeling approach for 4-phase adiabatic logic design. The paper highlights the drawbacks of the existing approaches and proposes a new approach that captures the timing errors and detects the circuit’s invalid operation due to mutually exclusive inputs being violated. We develop a model library containing the function of the four periods used in the trapezoidal power-clock and the adiabatic logic gates. The validation and verification of the proposed approach were done on the ISO-14443 standard benchmark circuit, a 16-bit cyclic redundancy check (CRC) circuit. The system modeled using HDL shows the timing agreement with the transistor-level SPICE simulations. The novel use of the four periods of a power-clock improves the robustness and reliability for the design and verification of large adiabatic systems. [ABSTRACT FROM AUTHOR]

Although molecular electronics is in its infancy, many significant advances have been reported in this field and, at present, it is necessary to study different types of materials that are potentially useful in molecular electronics and its properties. Experimental and theoretical studies have shown that almost all nanoscale devices such as molecular devices usually exhibit hysteresis characteristic due to various phenomena such as electron energy discreteness, electron tunneling, Coulomb blockade effects, etc. Some efforts have been made for modeling molecular electronics; however, not all of them support the hysteresis behavior. To the best of the authors’ knowledge, this paper for the first time proposes a general model for modeling the hysteresis behavior in molecular electronics. The proposed model is a HSPICE compatible circuit model and one of its main features is the ability to model both dc and ac behaviors of molecular electronic materials. The model can accept all amplitudes in the definite range, is continuous in the whole range and its parameters have minimum complexity resulting in maximum simplicity in terms of parameter extraction. Correct operation of the proposed circuit model and its accuracy are investigated by applying it to some hysteresis graphs reported in the literature, and the results are shown in this paper. [ABSTRACT FROM PUBLISHER]

With the steady growth of chip complexity and shrinking feature size, multiple challenges are emerging for transistor level circuit simulation. Compact SPICE models are a fundamental part of circuit verification, serving as a bridge between the semiconductor design and foundry. It is also an integral part of SPICE simulators, which directly affects tool performance and therefore design schedule. While the advanced 3-D technology nodes deliver superior level of scalability, simulation cost is rapidly increasing due to the computational complexity introduced by device model equations and the number of iterations required for numerical methods. In this paper, an efficient solution is proposed to reduce the computational cost associated with UC Berkeley BSIM-CMG device model evaluation, by applying robust Verilog compiler and computer algebra techniques to the device model equations. As a result of this implementation, simulation time reduction is up to 72% for complex blocks of the latest generation processor design. [ABSTRACT FROM PUBLISHER]

To improve the efficiency of direct solution methods in SPICE-accurate integrated circuit (IC) simulations, preconditioned iterative solution techniques have been widely studied in the past decades. However, it is still an extremely challenging task to develop robust yet efficient general-purpose preconditioning methods that can deal with various types of large-scale IC problems. In this paper, based on recent graph sparsification research we propose circuit-oriented general-purpose support-circuit preconditioning (GPSCP) methods to dramatically improve the sparse matrix solution time and reduce the memory cost during SPICE-accurate IC simulations. By sparsifying the Laplacian matrix extracted from the original circuit network using graph sparsification techniques, general-purpose support circuits can be efficiently leveraged as preconditioners for solving large Jacobian matrices through Krylov-subspace iterations. Additionally, a performance model-guided graph sparsification framework is proposed to help automatically build nearly-optimal GPSCP solvers. Our experiment results for a variety of large-scale IC designs show that the proposed preconditioning techniques can achieve up to 18 \times runtime speedups and 7 \times memory reduction in DC and transient simulations when compared to state-of-the-art direct solution methods. [ABSTRACT FROM PUBLISHER]

Defects or traps in semiconductors and nano devices that randomly capture and emit charge carriers result in low-frequency noise, such as burst and $1/f$ noise, which are important concerns in the design of both analog and digital circuits. The capture and emission rates of these traps are functions of the time-varying voltages across the device, resulting in nonstationary noise characteristics. Modeling of low-frequency, nonstationary noise in circuit simulators is a long-standing open problem. It has been realized that the low-frequency noise models in circuit simulators were the culprits that produced erroneous noise performance results for circuits under strongly time-varying bias conditions. In this paper, we present two fully nonstationary models for traps, a fine-grained Markov chain model and a coarse-grained Langevin model based on similar models for ion channels in neurons. The nonstationary trap models we present subsume and unify all of the work that has been done recently in the device modeling and circuit design literature on modeling nonstationary trap noise. We provide a detailed explication of these models with regard to their stochastic properties and develop carefully crafted circuit simulation techniques that are stochastically correct. We have implemented the proposed techniques in a MATLAB-based circuit simulator, by expanding the industry standard compact MOSFET model PSP to include a nonstationary description of oxide traps. We present results obtained by this extended model and the proposed simulation techniques for the low-frequency noise characterization of a common source amplifier and the phase jitter of a ring oscillator. [ABSTRACT FROM PUBLISHER]

Design of distributed embedded systems is a challenging task and it requires raising the level of abstraction to overcome the complexity of the design. In particular, modeling languages and semantic specification are necessary to address network description at high level of abstraction. Starting from this abstraction view, model manipulation is needed to explore various design alternatives and code generation is required for their simulation. In this paper, we propose the use of unified modeling language diagrams combined with a formal computational model as a key solution to specify requirements, generate design alternatives, and code for simulation. This paper proposes a formal framework and supporting tools to represent the application requirements, the library of network components, the environment description, and the rules to compose them. The framework allows to generate code for design validation by simulation and provides back annotation mechanism of the simulation results to refine the original model. [ABSTRACT FROM PUBLISHER]