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A logic diagnosis procedure provides information about the defects that are present in a faulty unit as a set of candidate faults. To obtain smaller, and more accurate, sets of candidate faults, a diagnostic test generation procedure produces a test set that distinguishes fault pairs. This paper observes that large sets of candidate faults are obtained when multiple defects are present in a faulty unit, even if a diagnostic test set is used for logic diagnosis. This points to the possibility that fault pairs do not provide a complete set of targets for diagnostic test generation. This paper analyzes the conditions that cause a large set of candidate faults to be formed under a particular logic diagnosis procedure and suggests new targets for diagnostic test generation. The experimental results for benchmark circuits demonstrate that a diagnostic test set can be improved by adding diagnostic tests for the new targets. [ABSTRACT FROM AUTHOR]

Test generation procedures target a variety of fault models in order to produce test sets that are effective for defect detection. This paper considers the likely scenario where two-cycle skewed-load tests are generated to detect single transition faults, and the test set is complemented with tests for single stuck-at faults that are not detected by the transition fault test set. For this scenario, this paper makes several unique observations that can be utilized to produce a single compact test set that consists only of two-cycle skewed-load tests for both fault models. The first observation is that a single-cycle test for a stuck-at fault can be transformed into a skewed-load test that is guaranteed to detect the stuck-at fault without performing logic or fault simulation. The second observation is that skewed-load tests, which are transformed from single-cycle tests for stuck-at faults, sometimes detect more transition and stuck-at faults than tests that were generated for transition faults. The third observation is that a static test compaction procedure, which is based on the modification and removal of tests, is effective in this context because it allows tests for stuck-at faults to detect more transition faults and vice versa. This paper describes a test compaction procedure based on these observations and presents experimental results for benchmark circuits to demonstrate the effectiveness of the procedure. [ABSTRACT FROM AUTHOR]

Lithography simulation is one of the key steps in physical verification, enabled by the substantial optical and resist models. A resist model bridges the aerial image simulation to printed patterns. While the effectiveness of learning-based solutions for resist modeling has been demonstrated, they are considerably data-demanding. Meanwhile, a set of manufactured data for a specific lithography configuration is only valid for the training of one single model, indicating low data efficiency. Due to the complexity of the manufacturing process, obtaining enough data for acceptable accuracy becomes very expensive in terms of both time and cost, especially during the evolution of technology generations when the design space is intensively explored. In this paper, we propose a new resist modeling framework for contact layers, utilizing existing data from old technology nodes and active selection of data in a target technology node, to reduce the amount of data required from the target lithography configuration. Our framework based on transfer learning and active learning techniques is effective within a competitive range of accuracy, i.e., $3 \times -10 \times $ reduction on the amount of training data with comparable accuracy to the state-of-the-art learning approach. [ABSTRACT FROM AUTHOR]

In automotive embedded real-time systems, e.g., the engine control unit, tasks are activated whenever the engine arrives at a specific angular position. In consequence the frequency of activation changes with the speed of the engine. Additionally, the execution times and deadlines may also depend on the engine speed. In recently published works analytical methods for tasks with this rate-dependent behavior were introduced. Though those methods do not consider angular phases between tasks. For instance, in a typical engine control unit one event is displaced a certain angular position after an event of another task. This paper introduces a sufficient analysis, which considers such angular phases. A number of experimental results are reported to compare our method with existing analysis. These illustrate the improvement in terms of precision and runtime. [ABSTRACT FROM AUTHOR]

Analyzing the timing properties of asynchronous systems is essential for characterizing their performance and power. Previous work on timing showed that such systems under and-causality and fixed delay exhibit periodicity properties. We give a different graph-based rigorous proof of the exact timing behavior of more general classes of such systems, and conclude their exact periodicity property, where each of the signal transition will occur with the same period after finite occurrences. We established our results under weaker assumption about system connectivity/topology, and this paper provides the theoretical foundation, for the exact periodicity property to be applied and exploited in circuits containing a combination of synchronous and asynchronous components. We provide simulation-based results for several typical asynchronous circuit topologies to quantify this time period in practical circuits. We also provide an extension of our analysis and methods to the case of bounded delay systems. A key result that is a consequence of our analysis is that asynchronous circuits can be integrated with synchronous logic via a metastability-free interface, thereby eliminating the high-overhead synchronizers when an asynchronous circuit is fully surrounded by synchronous logic. [ABSTRACT FROM PUBLISHER]

Effective transient power grid simulators are needed during design processes because a designed power grid needs to be numerously analyzed. This paper builds an efficient and reliable incremental power grid transient simulator, which we name it InTraSim, by integrating macro modeling techniques, sparse recovery mechanisms, an innovated pseudo-node value estimation method, and an initiated adaptive error control scheme. InTraSim is able to deal with not only element-value alterations of designs but also topology modifications of designs. [ABSTRACT FROM PUBLISHER]

Two challenges are combined when compressed tests are computed for path delay faults: 1) path delay faults that are important to detect are associated with long paths, and many of these faults are undetectable and 2) it may not be possible to compress a given test for a path delay fault. This paper addresses these challenges in the context of test data compression methods that are based on a linear-feedback shift-register (LFSR). The basic approach that this paper uses modifies initially random seeds for the LFSR into seeds that produce tests for detecting target faults. This approach can find seeds even if the available tests cannot be compressed into seeds. In addition, the procedure described in this paper also selects detectable path delay faults to address the presence of undetectable path delay faults in the set of target faults. For this purpose it uses a metric that measures the similarity between target and detected path delay faults, and attempts to compute seeds that increase the values of this metric. Experimental results are presented to demonstrate the ability of the procedure to detect path delay faults in benchmark circuits. [ABSTRACT FROM AUTHOR]

A diagnostic test generation procedure targets fault pairs in a set of target faults with the goal of distinguishing all the fault pairs. When a fault pair cannot be distinguished, it prevents the diagnostic test set from providing information about the faults, and consequently, about defects whose diagnosis would have benefited from a diagnostic test for the indistinguishable fault pair. This is referred to in this paper as a diagnostic hole. This paper observes that it is possible to address diagnostic holes by targeting different but related fault pairs, possibly from a different fault model. As an example, this paper considers the case where diagnostic test generation is carried out for single stuck-at faults, and related bridging faults are used for addressing diagnostic holes. Considering fault detection, an undetectable single stuck-at fault implies that certain related bridging faults are undetectable. This paper observes that, even if a pair of single stuck-at faults is indistinguishable, a related pair of bridging faults may be distinguishable. Based on this observation, diagnostic tests for pairs of bridging faults are added to a diagnostic test set when the related single stuck-at faults are indistinguishable. Experimental results of defect diagnosis for defects that do not involve bridging faults demonstrate the importance of eliminating diagnostic holes. [ABSTRACT FROM AUTHOR]

A functional test sequence for a design may not be effective as a manufacturing test for a logic block in the design because it achieves a low gate-level fault coverage. This paper describes a procedure for selecting a clock sequence that increases the gate-level fault coverage of a functional test sequence when it is used for testing a subset of logic blocks. The procedure deactivates the clocks to the logic blocks in the subset when a primary input vector has a negative effect on their fault coverage. The procedure is different from earlier test generation and test compaction procedures in that it increases the fault coverage without modifying the functional test sequence. It thus preserves some of the functional characteristics and the test application process for the sequence. Experimental results for benchmark circuits are presented to demonstrate the effectiveness of the procedure. [ABSTRACT FROM AUTHOR]

It was shown earlier that certain primary input values have a negative effect on the fault coverage of a functional test sequence when they appear repeatedly in the sequence. A gate-level sequential test generation procedure based on this observation computed a primary input cube c with preferred values, and generated random functional test sequences that conformed to c with a high probability 0.5 \leq p < 1 . This procedure selected values for p out of a set of possible values, and assigned the same value of p to all the primary inputs. Motivated by the low computational complexity of this procedure, this paper addresses the selection of p and the possibility of using different values of p for different primary inputs. The goal is to increase the fault coverage and reduce the number of functional test sequences. The procedure described in this paper adjusts a functional test sequence to a circuit by complementing values that conflict with c . The procedure requires fewer functional test sequences to reach or exceed the fault coverage of the earlier procedure for benchmark circuits. The procedure can be applied to any functional test sequence or set of functional test sequences. [ABSTRACT FROM AUTHOR]

In deep submicron nodes, the final design patterning quality depends profoundly on the optical proximity correction (OPC) quality. The required pattern fidelity and CD uniformity can never be achieved without good OPC. However, OPC runtime-resource factor has been exponentially increasing every technology node reaching alarming levels, where the OPC cost in terms of resources and turn-around-time is becoming very expensive. In this paper, we present a novel approach for speeding up the OPC convergence process using our model-based initial bias methodology. Our proposed methodology is based on building generic compact bias-models that can predict the final OPC shapes with a good accuracy using the optical simulation parameters. As a result, the OPC initial condition is much closer to the final solution and more than half of the OPC iterations can be saved as a result. In this paper, we present the details of our methodology and our compact initial-bias model we are proposing. We also present our testing results on a 10 nm metal level, where almost 50% of the OPC iterations could be saved when we apply our methodology. [ABSTRACT FROM AUTHOR]

Efficient performance modeling of today’s analog and mixed-signal circuits is an important yet challenging task, due to the high-dimensional variation space and expensive circuit simulation. In this paper, we propose a novel performance modeling algorithm that is referred to as Bayesian model fusion (BMF) to address this challenge. The key idea of BMF is to borrow the information collected from an early stage (e.g., schematic level) to facilitate efficient performance modeling at a late stage (e.g., post layout). Such a goal is achieved by statistically modeling the performance correlation between early and late stages through Bayesian inference. Furthermore, to make the proposed BMF method of practical utility, four implementation issues, including: 1) prior mapping; 2) missing prior knowledge; 3) fast solver; and 4) prior and hyper-parameter selection, are carefully considered in this paper. Two circuit examples designed in a commercial 32 nm CMOS silicon on insulator process demonstrate that the proposed BMF method achieves up to $9\times $ runtime speed-up over the traditional modeling technique without surrendering any accuracy. [ABSTRACT FROM AUTHOR]

This paper addresses theoretical aspects of arithmetic circuit verification based on algebraic rewriting. Its goal is to advance the understanding of algebraic techniques for arithmetic circuit verification in the context of symbolic computer algebra. The paper offers a new insight into the arithmetic circuit verification problem, by viewing the computation performed by the circuit as the flow of digital data. In the proposed bit-flow model, the circuit is modeled as a network of logic components satisfying a bit-flow conservation law. We prove that the value of the flow of data in the circuit is invariant throughout the circuit and use this to prove soundness and completeness of the rewriting technique, independently from the computer algebra arguments. The efficiency of the method is illustrated with impressive results for large integer multipliers. The verification system and benchmarks are offered in an open source software environment. [ABSTRACT FROM AUTHOR]

Exact synthesis is a versatile logic synthesis technique with applications to logic optimization, technology mapping, synthesis for emerging technologies, and cryptography. In recent years, advances in SAT solving have led to a heightened research effort into SAT-based exact synthesis. Advantages of exact synthesis include the use of various constraints (e.g., synthesis of emerging technology circuits). However, although progress has been made, its runtime remains unpredictable. This paper identifies two key points as hurdles to further progress. First, there are open questions regarding the design and implementation of exact synthesis systems, due to the many degrees of freedom. For example, there are different CNF encodings, different symmetry breaks to choose from, and different encodings may be suitable for different domains. Second, SAT-based exact synthesis is difficult to parallelize. Indeed, this is a common drawback of logic synthesis algorithms. This paper proposes four ways to close some open questions and to reduce runtime: 1) quantifying differences between CNF encoding schemes and their impacts on runtime; 2) demonstrating impact of symmetry breaking constraints; 3) showing how directed acyclic graph topology information can be used to decrease runtime; and 4) showing how topology information can be used to leverage parallelism. [ABSTRACT FROM AUTHOR]

Energy management is a critical challenge in multicore processors due to continuous technology scaling. Previous methods have mostly focused on the energy minimization of the processor cores. However, energy overhead of the off-chip voltage regulator (VR) has recently shown to be a nontrivial part of the total energy consumption and has been previously overlooked. In this paper, we propose an overall energy optimization method for the system that minimizes both per-core energy consumption and VR energy consumption using dynamic voltage frequency scaling and VR phase scaling by solving a comprehensive convex model. In order to improve the accuracy of the task latency model, a new task model considering both computation and memory access of the task is also developed. Furthermore, for better scalability and lower online overhead, we decompose our proposed convex method into two stages: 1) an offline stage and 2) an online stage. During the offline stage, we explore the convex model by assuming different numbers of active phases of the VR, various workload pressures and workload characteristics to collect the optimal frequency assignments under different scenarios. During the online stage, the specific frequency assignment for cores and optimal active phase number of the VR are selected and applied based on the actual workload pressure and its characteristics running on the cores. Experiments on real benchmarks show that when compared with the state-of-the-art approaches, which are oblivious to VR overheads and exploit slack time to achieve energy minimization, our method can achieve a significant energy saving of up to 22.4% with negligible online overhead. [ABSTRACT FROM AUTHOR]

The design of embedded wireless and multimedia applications requires temporal analysis to verify if real-time constraints such as throughput and latency are met. This paper presents a design-time analytical approach to derive a conservative upper bound to the maximum end-to-end latency of a streaming application. Existing analytical approaches often assume static application models, which cannot cope with the data-dependent execution of dynamic streaming applications. Consequently, they give overly pessimistic upper bounds. In this paper, we use an expressively richer dataflow model of computation as an application model. The model supports adaptive applications that change their graph structure, execution times, and data rates, depending on their mode of operation, or scenario. We first formalize the latency analysis problem in the presence of dynamically switching scenarios. We characterize each scenario with a compact matrix in (max, +) algebra using a symbolic execution of one graph iteration. The resulting matrices are then composed to derive a bound to the end-to-end latency under a periodic source. Aperiodic sources such as sporadic streams can be analyzed by reduction to a periodic reference. We demonstrate the applicability of the technique with dataflow models from the wireless application domain. Moreover, the method is illustrated with a tradeoff analysis in resource reservation under a throughput constraint. The evaluation shows that the approach has a low runtime, which enables it to be effectively integrated in multiprocessor design flows of streaming applications. [ABSTRACT FROM AUTHOR]

This paper proposes a novel memristor-based multiplexer implemented by using NOT-material implication. The proposed design can be extended to arbitrary ${N}$ -bit inputs and the enable-port can be added to improve its structure. Furthermore, this structure can be applied in the cascade circuit and crossbar array. A novel peripheral read circuit is introduced to overcome the problem that it is difficult to read out the operation results stored in crossbar array with large scales. The feasibility and correctness of our design is verified by the HSPICE simulation results with voltage threshold adaptive memristor model. [ABSTRACT FROM AUTHOR]

Exploring the design space of computer architectures generally consists of a trial-and-error procedure where several architectural configurations are evaluated by using simulation techniques. The final goal of the multiobjective design space exploration (DSE) process is the identification of architectural configurations optimal for a set of target objective functions, typically power consumption, and performance. Simulations are computationally expensive making it rather hard to efficiently explore the design space to identify high-quality configurations in an acceptable exploration time when relying solely on a single-core machine to run simulations. To tackle this problem, engineers proposed solutions based on either: 1) the use of approximate analytic performance models to prune the suboptimal regions of the design space by reducing the number of simulations to run or 2) the use of parallel computing resources to run different simulations concurrently. In this paper we demonstrate that, to efficiently speedup the DSE process while fully exploiting the parallel computing infrastructure, we need to combine the two techniques together in a structured manner. In this paper, we investigate this issue and we propose a DSE solution that exploits approximate analytic prediction models to improve the simulation schedule on a parallel computing environment rather than to prune the number of simulations. Experimental results demonstrate that the proposed technique provides a speedup from 1.26\boldsymbol \times to 4\boldsymbol \times with respect to other parallel state-of-the art DSE techniques. [ABSTRACT FROM PUBLISHER]

3-D integrated circuits (3-D ICs) are expected to have shorter wirelength, better performance, and less power consumption than 2-D ICs. These benefits come from die stacking and use of through-silicon vias (TSVs) fabricated for interconnections across dies. However, the use of TSVs has several negative impacts such as area and capacitance overhead. To predict the quality of 3-D ICs more accurately, TSV-aware 3-D wirelength distribution models considering the negative impacts were developed. In this paper, we apply an optimal buffer insertion algorithm to the TSV-aware 3-D wirelength distribution models and present various prediction results on wirelength, delay, and power consumption of 3-D ICs. We also apply the framework to 2-D and 3-D ICs built with various combinations of process and TSV technologies and predict the quality of today and future 3-D ICs. [ABSTRACT FROM PUBLISHER]

Scalable compact models for passive elements are important in the Analog/RF circuit design and optimization. Traditional scalable modeling methods are mainly physical and manual based methods, which usually require deep physical insight and extensive human intervention. In this paper, an automatic scalable compact modeling method for generic passive elements is established. The proposed method is a unified parameter extraction and scalable modeling scheme with novel inner-loop correlated parameter extraction and outer-loop adaptive boundary compression techniques. Experimental results show that both accuracy and scalability have been achieved by the proposed method for industrial inductors and transformers with an acceptable computational cost. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a novel Verilog-A based memristor model for effective simulation and application. Our proposed model captures desired nonlinear characteristics using voltage-based state control. This model is flexible and accurate, it can exhibit all the behaviors of HP memristive device and a general class memristive device resistive random access memory which is important in logic and memory design. Furthermore, we can antiserially connect two proposed models to capture the ideal I – V characteristics of complementary resistive switch (CRS). We demonstrate that our proposed CRS model-based crossbar arrays can significantly reduce sneak path currents with high noise margin compared to traditional memristor-based architectures. [ABSTRACT FROM AUTHOR]

A defect diagnosis procedure is an important part of the yield improvement process. As defects become more complex, the output responses they produce differ to larger extents from the output responses of modeled faults, and they become more difficult to diagnose. Biases in the defect diagnosis procedure can also cause defects to be more difficult to diagnose. It is important to study and remove such biases in order to ensure that they do not affect the accuracy of the procedure. This paper undertakes a study of the biases of a defect diagnosis procedure and suggests a way to improve it. The study illustrates an approach by which biases in defect diagnosis procedures can be analyzed in general. [ABSTRACT FROM AUTHOR]

The use of formal models to describe early versions of the structure and the behavior of a system has become common practice in industry. UML and OCL are the de-facto specification languages for these tasks. They allow for capturing system properties and module behavior in an abstract but still formal fashion. At the same time, this enables designers to detect errors or inconsistencies in the initial phases of the design flow—even if the implementation has not already started. Corresponding tools for verification of formal models got established in the recent past. However, verification results are usually not reused in later design steps anymore. In fact, similar verification tasks are applied again, e.g., after the implementation has been completed. This is a waste of computational and human effort. In this paper, we address this problem by proposing a method which checks a given implementation of a system against its corresponding formal method. This allows for transferring verification results already obtained from the formal model to the implementation and, eventually, motivates a new design flow which addresses verification across abstraction levels. This paper describes the applied techniques as well as their orchestration. Afterwards, the applicability of the proposed methodology is demonstrated by means of examples as well as a case study from an industrial context. [ABSTRACT FROM AUTHOR]

In order to perform accurate parasitic extraction, foundries must provide the cross section profile of devices, and IP vendors must provide sufficient layout information. However, foundries and IP vendors are increasingly reluctant to reveal such sensitive information, especially for advanced devices. Therefore, the industry is faced with the following challenges: 1) foundries/IP vendors need to protect their trade secrets; 2) electronic design automation vendors need to integrate foundry data into extraction tools; and 3) IC designers need to have the accurate parasitic data. In this paper, we propose an innovative and practical solution to these challenges, by building a macro model around any region in 2-D/3-D on a circuit where foundries or IP vendors wish to hide information, yet the macro model allows accurate capacitance extraction inside and outside of the region. We first give algorithms to construct the macro model. Then, we describe how existing extraction algorithms can interface with the macro model to perform extraction for the entire circuit at the same accuracy as if complete information was given. The macro model can be used in finite difference method/finite element method and floating random walk, due to an equivalence theorem we proved. Finally, we propose the concept of equivalent profile and describe how to find one based on the macro model. Experimental results show the macro model can be efficiently constructed and used to produce accurate capacitance extraction. [ABSTRACT FROM AUTHOR]

The random telegraph noise (RTN) is becoming more serious in advanced technologies. Due to the unpredictability of the physical phenomenon, RTN is a good randomness source for true random number generators (TRNG). In this paper, we build fundamental randomness models for TRNGs based on single trap- and multiple traps-induced RTN. We theoretically derive the autocorrelation coefficient, bias, and bit rate for RTN-based TRNGs. Two representative RTN-based TRNG schemes are simulated to verify the proposed randomness models. An oscillator-based TRNG is also studied based on the theoretical randomness model of multiple traps-induced RTN. We also provide basic guidelines for designing RTN-based TRNGs. [ABSTRACT FROM PUBLISHER]

Translation validation is the process of proving that the target code is a correct translation of the source program being compiled. In this paper, we propose a translation validation method to verify code motion transformations involving loops applied during the scheduling phase of high-level synthesis (HLS). Our method is capable of ignoring false computations during translation validation. We have also identified a scenario involving code motion across loops where the state-of-the-art translation validation method gives false positive results. Our method can prove the nonequivalence of the concerned finite state machines with data paths in this scenario. We detected a bug in the HLS tool SPARK involving loop invariant code motion using our method. Experimental results demonstrate the usefulness of our method. [ABSTRACT FROM AUTHOR]

The support for local variables in SystemVerilog assertions significantly enhances its expressive power. Handling local variables in analog and mixed-signal (AMS) extensions of assertion languages is tricky due to the dense time interpretation of AMS assertions, and has not been adequately treated in existing literature. This paper presents an approach for interpreting local variables in AMS assertions during simulation and a tool flow that works with standard mixed-mode simulators. [ABSTRACT FROM AUTHOR]

With the continuous drive toward integrated circuits scaling, efficient performance modeling is becoming more crucial yet more challenging. In this paper, we propose a novel method of hierarchical performance modeling based on Bayesian co-learning. We exploit the hierarchical structure of a circuit to establish a Bayesian framework where unlabeled data samples are generated to improve modeling accuracy without running additional simulation. Consequently, our proposed method only requires a small number of labeled samples, along with a large number of unlabeled samples obtained at almost no-cost, to accurately learn a performance model. Our numerical experiments demonstrate that the proposed approach achieves up to ${3.6 \times }$ runtime speed-up over the state-of-the-art modeling technique without surrendering any accuracy. [ABSTRACT FROM AUTHOR]

This paper employs correct-by-construction control synthesis, in particular controlled invariant set computations, for falsification. Our hypothesis is that if it is possible to compute a “large enough” controlled invariant set either for the actual system model or some simplification of the system model, interesting corner cases for other control designs can be generated by sampling initial conditions from the boundary of this controlled invariant set. Moreover, if falsifying trajectories for a given control design can be found through such sampling, then the controlled invariant set can be used as a supervisor to ensure safe operation of the control design under consideration. In addition to interesting initial conditions, which are mostly related to safety violations in transients, we use solutions from a dual game, a reachability game for the safety specification, to find falsifying inputs. We also propose optimization-based heuristics for input generation for cases when the state is outside the winning set of the dual game. To demonstrate the proposed ideas, we consider case studies from basic autonomous driving functionality, in particular, adaptive cruise control and lane keeping. We show how the proposed technique can be used to find interesting falsifying trajectories for classical control designs like proportional controllers, proportional integral controllers and model predictive controllers, as well as an open source real-world autonomous driving package. [ABSTRACT FROM AUTHOR]

A significant amount of research has been conducted in the past on compositional real-time scheduling as it has become a useful foundational theory for real-time operating systems and hypervisors. However, compositional frameworks suffer from abstraction overhead in composing components. In this paper, we decompose the abstraction overhead into: 1) supply abstraction overhead associated with the supply from a resource provider and 2) demand abstraction overhead associated with the component workload. Then, we provide sufficient conditions for each abstraction overhead to be eliminated. In addition, this paper provides a heuristic technique that transforms a component to satisfy the sufficient conditions so that the abstraction overhead can be minimized. In experiments, we show that our technique outperforms two prior overhead-reducing techniques. The reduction in overhead is about 10% on average when compared to a technique that uses a single global period and about 8% on average when compared to a technique based on harmonicity. [ABSTRACT FROM AUTHOR]

In current practice a formal analysis of hybrid system models is assertion-based. The work presented here is based on features that look beyond functional correctness toward a quantitative evaluation of behavioral attributes. A feature defines a real-valued evaluation function over a specific set of traces. This paper describes an improved method for the interpretation of features over hybrid automata models. It further demonstrates how satisfiability modulo theory solvers can be used for extracting behavioral traces corresponding to corner cases of a feature. Results are demonstrated on examples from the control and circuit domains. [ABSTRACT FROM AUTHOR]

Constructing algebraic polynomials using computer algebra techniques is believed to be state-of-the-art in analyzing gate-level arithmetic circuits. However, the existing approach applies algebraic rewriting directly to the gate-level netlist, which has potential memory explosion problem. This paper introduces an algebraic rewriting technique based on the and-inverter graph (AIG) representation of gate-level designs. Using AIG-based cut-enumeration and truth table computation, an efficient order of algebraic rewriting is identified, resulting in dramatic simplifications of the polynomial under construction. An automatic approach, which further reduces the complexity of algebraic rewriting by handling redundant polynomials, is also proposed. [ABSTRACT FROM AUTHOR]

This paper proposes a technique, GALAXY, to speed up multicircuit simulation, where each circuit under simulation is identical in schematic but different in some parameters. GALAXY is based on the successive chord method, where the inverse Jacobian matrix ( J ^-1 ) is reused to simulate many circuits whose solutions are similar. GALAXY also speeds up single-circuit simulation by reusing J ^-1 between consecutive time steps. Compared with a traditional Newton–Raphson (NR) simulator, on average, GALAXY reduces runtime of single-circuit and multicircuit simulation by 44% and 71%, without loss of accuracy. The number of NR iterations is reduced by 78%. [ABSTRACT FROM PUBLISHER]

In this paper, we propose SVR-NoC, a network-on-chip (NoC) latency model using support vector regression (SVR). More specifically, based on the application communication information and the NoC routing algorithm, the channel and source queue waiting times are first estimated using an analytical queuing model with two equivalent queues. To improve the prediction accuracy, the queuing theory-based delay estimations are included as features in the learning process. We then propose a learning framework that relies on SVR to collect training data and predict the traffic flow latency. The proposed learning methods can be used to analyze various traffic scenarios for the target NoC platform. Experimental results on both synthetic and real-application traffic demonstrate on average less than 12% prediction error in network saturation load, as well as more than $100\times $ speedup compared to cycle-accurate simulations can be achieved. [ABSTRACT FROM PUBLISHER]

Compact modeling of phase-locked loop (PLL) frequency synthesizer is proposed to reduce transient phase noise and jitter simulation time. Conventional small-signal noise assumption based frequency-domain simulation approach produces inaccurate results for nonlinear PLLs. Accurate analysis of nonlinear PLL are possible through time-domain, or transient noise simulation but time-domain simulation is computation-intensive and time-consuming. This paper presents a practical solution for transient phase noise and jitter analysis using compact modeling techniques. It features an autoregressive moving average process modeled voltage-controlled oscillator with fractional calculus and wavelet transform for phase noise decomposition and reconstruction, thereby reducing the phase noise and jitter simulation time to 25.8% of the transistor-level simulation with 0.4 dB @ 1 MHz phase noise error and 0.3 ps long-term jitter error for a 2 GHz PLL frequency synthesizer in a 65 nm CMOS process. [ABSTRACT FROM PUBLISHER]

This paper describes a procedure that computes seeds for linear-feedback shift register-based diagnostic test generation. A conventional process first computes test cubes, and then computes seeds that produce them by solving sets of linear equations. With this process, a seed may not exists for a given test cube. To address this issue, the procedure described in this paper produces seeds directly. Staring from a seed for fault detection, it modifies the seed such that the test it produces will distinguish a pair of faults. The procedure is applied in two modes. The first mode does not require diagnostic test cubes. In this mode, the procedure attempts to modify a seed for fault detection so as to lose the detection of one of the faults on one of the outputs where the faults are detected. The procedure thus uses the concept of test elimination that was used earlier for diagnostic test generation. The second mode is guided by a diagnostic test cube for a fault pair that needs to be distinguished. The procedure modifies a seed so as to reduce the distance between the test that the seed produces and the test cube. Without the requirement to match all the specified values of the test cube, the procedure can produce a seed for distinguishing the pair of faults even when a seed for the given test cube does not exist. Experimental results are presented to demonstrate the effectiveness of the procedure. [ABSTRACT FROM PUBLISHER]

This paper presents a new Property-Driven Design (PDD) method that starts from an abstract system model and integrates formal property checking early into a top-down design methodology for register transfer level (RTL) hardware. In PDD the role of formal verification is not limited to “bug hunting” alone. Instead, the formal techniques are applied in such a way that a formal relationship is provided between the abstract system model and its concrete implementation at the RTL. In order to avoid the high efforts associated with verification by property checking the proposed PDD approach automatically generates abstract properties from a system-level description and later refines them along the design process. The advantage of this methodology is to obtain a formally verified design at lower costs when compared to conventional design flows with property checking. The main benefit of the proposed approach results from the fact that a formally sound system model is available together with the RTL design. Specifically, LTL properties proven on the abstract model also hold on the concrete implementation. This facilitates many complex analysis and verification tasks in today’s design flows and contributes to emancipating system-level models from prototypes to golden design models. Several open-source and industrial case studies are reported that demonstrate the high potential of a PDD-based design paradigm. [ABSTRACT FROM AUTHOR]

Observation points in the combinational logic of a circuit can aid in the diagnosis of logic defects by reducing the number of indistinguished fault pairs. This paper considers the use of observation points in the combinational logic for the diagnosis of scan chain defects under an approach to test application called transparent-scan. Tests that are used for the diagnosis of scan chain defects include functional capture cycles that propagate the effects of scan chain faults through the combinational logic. Scan chain faults can thus be distinguished based on the values that are propagated in their presence to an observation point in the combinational logic. The procedure for observation point insertion considers the following parameters with respect to scan chain faults: 1) the number of indistinguished fault pairs and 2) the distances, measured in numbers of scan cells, between the faults that cannot be distinguished. With lower distances, a set of candidates for a faulty scan chain is likely to contain faults in the same vicinity of the scan chain. This facilitates failure analysis. Experimental results demonstrate the effectiveness of observation points in the combinational logic for scan chain diagnosis under transparent-scan. [ABSTRACT FROM PUBLISHER]

In this paper, a compact SPICE model of flexible transition metal dichalcogenide field-effect transistors (TMDFETs) is developed with considering effects when scaling the transistor size down to the 10-nm technology node. The model supports different transistor design parameters such as width, length, oxide thickness, and various channel materials, as well as the applied strain, which enables the evaluation of transistor- and circuit-level behavior under process variation and different levels of bending. Extensive device-level simulations are performed using this model, and TMDFETs are compared with different Si- and graphene-based devices. We performed circuit-level simulations, and reported the delay, power, and EDP of the benchmark circuits. Effects from process variation are also evaluated. These cross-technology studies show that TMDFET’s power is comparable to the low-power multigate devices (about 0.4% lower). The delay and EDP are 60% and 2.3% higher than the graphene-based devices, respectively. The developed compact model would enable SPICE-level circuit simulation for early assessment, design, and evaluation of futuristic TMDFET-based flexible circuits targeting advanced technology nodes. [ABSTRACT FROM AUTHOR]

Resistive switching devices are nonlinear electrical components that have drawn great attention in the design of new technologies including memory devices and neuromorphic circuits. In this paper, an SPICE implementation of a novel compact model is presented and put under test by means of different circuit configurations. The model is based on two identical opposite-biased diodes in series with a resistor where the switching behavior is governed by the creation and rupture of multiple conductive channels. Results show that the model is stable under different input sources and amplitudes and, with special interest, in multielement circuits. The model is validated with experimental data available in the literature. Both the corresponding SPICE code and schematic are provided in order to facilitate the model use and assessment. [ABSTRACT FROM PUBLISHER]

Machine-learning algorithms have shown outstanding image recognition/classification performance for computer vision applications. However, the compute and energy requirement for implementing such classifier models for large-scale problems is quite high. In this paper, we propose feature driven selective classification (FALCON) inspired by the biological visual attention mechanism in the brain to optimize the energy-efficiency of machine-learning classifiers. We use the consensus in the characteristic features (color/texture) across images in a dataset to decompose the original classification problem and construct a tree of classifiers (nodes) with a generic-to-specific transition in the classification hierarchy. The initial nodes of the tree separate the instances based on feature information and selectively enable the latter nodes to perform object specific classification. The proposed methodology allows selective activation of only those branches and nodes of the classification tree that are relevant to the input while keeping the remaining nodes idle. Additionally, we propose a programmable and scalable neuromorphic engine (NeuE) that utilizes arrays of specialized neural computational elements to execute the FALCON-based classifier models for diverse datasets. The structure of FALCON facilitates the reuse of nodes while scaling up from small classification problems to larger ones thus allowing us to construct classifier implementations that are significantly more efficient. We evaluate our approach for a 12-object classification task on the Caltech101 dataset and ten-object task on CIFAR-10 dataset by constructing FALCON models on the NeuE platform in 45-nm technology. Our results demonstrate up to $3.66\boldsymbol \times $ improvement in energy-efficiency for no loss in output quality, and even higher improvements of up to $5.91\boldsymbol \times $ with 3.9% accuracy loss compared to an optimized baseline network. In addition, FALCON shows an improvement in training time of up to $1.96\boldsymbol \times $ as compared to the traditional classification approach. [ABSTRACT FROM AUTHOR]

This paper proposes the use of coupled electric and magnetic circuits in the schematic models of high frequency integrated circuits, as an effective method to model the global inductive effects and coupling. These pairs of coupled circuits, called magneto-electro-equivalent circuit (MEEC) models, are obtained by partitioning the computational domain into several subdomains, each having its own electromagnetic field regime. The model reduction method we propose can be used not only to derive the full coupled electric and magnetic circuit model of a device starting from its layout, but also to correct the electric schematic by adding inductive parasitic effects. The MEEC approach uses special boundary conditions—called magnetic/electric hooks—on the interfaces between the subparts in which the computational domain is partitioned. The success of the correct extraction of inductive effects rely on the terminal reduction, i.e., the correct placement of magnetic hooks on the interfaces. In order to find this placement, a heuristic approach based on IC layout analysis is proposed. In order to consider the parasitic inductive couplings, the electric schematic circuit graph is enhanced with geometric information from the layout (e.g., node coordinates). The MEEC-based approach is validated for a real example of a low noise amplifier. Its initial layout design proved to be wrong only after the fabrication and characterization of the first prototype. The use of the inductive parasitic extraction tool, based on the MEEC approach, would have prevented this. MEEC is an alternative approach to vector potential equivalent circuit, with respect to which advantages and disadvantages are discussed. [ABSTRACT FROM PUBLISHER]

The manufacturing yield of chip multiprocessors (CMPs) has become a significant problem as more transistors are integrated onto a single die and the defect rate keeps increasing for “end-of-Moore” nano-scale CMOS technologies. Since such CMP designs usually have significant structural symmetry, adding spare copies to these should be an effective method for increasing yield per area, as is the case for memories. However, a systematic approach to add spare copies to optimize CMP yield per area has never been developed, primarily due to the lack of: 1) a general model of CMP architectures and 2) a practically-useable model for computing areas of chip versions with different configurations of spare copies. This paper develops such models and, in conjunction with a systematic approach for enumerating a wide range of spare configurations, uses these to compute the area overhead and yield for each configuration. In particular, this paper proposes a general spare cores sharing technique to maximize yield per area of any CMP by efficiently traversing the design space for adding spare cores. Experimental results show that the advantage of the proposed approach over traditional approaches increases with continued technology scaling. Specifically, the proposed approach achieves \(2\times \) yields per area over previous approaches for 32 nm and 22 nm technologies. Also, the obtained yield per area values provided by our approach are around 70% of that obtained for the ideal scenario where defect density is zero and no redundancy is added. [ABSTRACT FROM PUBLISHER]

Leakage power is becoming significant in new generation IC chips. As leakage power is nonlinearly related to temperature, it is challenging to manage the thermal behavior of today’s multicore systems, since thermal management becomes a nonlinear control problem. In this paper, a new predictive dynamic thermal management (DTM) method with neural network thermal model is proposed to naturally consider the inherent nonlinearity between leakage and temperature. We start with analyzing the problems of using recurrent neural network (RNN) to build the nonlinear thermal model, and point out that there is exploding gradient induced long-term dependencies problem, leading to large model prediction errors. Based on this analysis, we further propose to use echo state network (ESN), which is a special type of RNN, as the leakage-aware nonlinear thermal model. We theoretically and experimentally show that ESN achieves much higher accuracy by completely avoiding the long-term dependencies problem. On top of this nonlinear ESN thermal model, we propose a novel model predictive control (MPC) scheme called ESN MPC, which uses iterative steps to find the optimal future power recommendations for thermal management. Being able to consider the leakage-temperature nonlinear effects and equipped with advanced control technique, the new method achieves an overall high quality temperature management with smooth and accurate temperature tracking. The experimental results show the new method outperforms the state-of-the-art leakage-aware multicore DTM method in both temperature management quality and computing overhead. [ABSTRACT FROM AUTHOR]

Accurate delay analysis with distributed RC delay can be computationally expensive, and can contribute the majority of the total runtime for gate sizers. Recent works have shown that Lagrangian relaxation (LR)-based gate sizers have produced designs with the lowest power on average. But they are also very slow due to a large number of expensive timing updates spread across several tens of iterations. In this paper, we develop an LR-based discrete gate sizer for fast timing and power reduction. Our gate sizer is multithreaded and is equipped with parallelization enabling techniques, namely mutual exclusion edge (MEE) assignment and directed acyclic graph (DAG)-based netlist traversal (DNT). MEEs are dummy edges assigned to improve load sharing among different threads. DNT facilitates simultaneous resizing of gates belonging to different topological levels. Our Lagrange multiplier update strategy enables rapid convergence of our timing and power recovery algorithms. To reduce the runtime of timing updates, we propose a simple and fast-to-compute effective capacitance model. We further propose mechanisms to calibrate timing models to improve their accuracy. By calibrating the internal timing models only twice, our proposed gate sizing flow facilitates extremely fast design optimization. We benchmark our gate sizer using the ISPD 2012 and 2013 gate sizing contest benchmark suites. Compared to the state-of-the-art gate sizer, our proposed gate sizer is on average $15\times $ faster and the optimized designs have 2.5% higher leakage power. Since we tradeoff timing accuracy for larger runtime speedup, our optimized designs have small timing violations. [ABSTRACT FROM AUTHOR]

Analog/RF built-in test (BIT) techniques are essential for reducing the very high costs of specification-based tests and for high-safety applications. The adoption of a BIT technique needs to be decided at the design stage, and this can be facilitated by estimating the test quality in terms of errors such as test escapes (${T_{E}}$) and yield loss (${Y_{L}}$). Test quality estimation at the design stage has been traditionally very difficult for analog/RF circuits due to the lack of fault models that properly cover parametric faulty behavior. In recent years, statistical simulation has been considered in combination with learning techniques for the estimation of parametric test metrics. Extreme value theory (EVT) has provided a rigorous tool for the computation of parametric test metrics. However, test metrics estimation has been limited to the use of a univariate model. In this paper, we extend this approach by using a multivariate extreme value model. We illustrate this for the evaluation of an RF LNA BIT technique using a bivariate model. [ABSTRACT FROM AUTHOR]

Formal methods are a promising alternative to simulation-based verification of mixed-signal systems. However, in practice, such methods fail to scale with heterogeneity and complexity of today’s analog/mixed-signal systems. Furthermore, it is unclear how they can be integrated into existing verification flows. This paper shows a path to overcome these obstacles. The idea is to use a hierarchical verification flow, in which components can be verified by formal methods or by multirun simulation. To transport verification results across hierarchies, we represent parameters and properties by affine arithmetic decision diagrams. We study to which extent this approach fulfills the needs of practical application by the verification of a phase-locked loop of an IEEE 802.15.4 transceiver system. [ABSTRACT FROM AUTHOR]

As field-programmable gate arrays (FPGAs) become prevalent in critical application domains, their power consumption is of high concern. In this paper, we present and evaluate a power monitoring scheme capable of accurately estimating the runtime dynamic power of FPGAs in a fine-grained timescale, in order to support emerging power management techniques. In particular, we describe a novel and specialized ensemble model which can be decomposed into multiple customized decision-tree-based base learners. To aid in model synthesis, a generic computer-aided design flow is proposed to generate samples, select features, tune hyperparameters, and train the ensemble estimator. Besides this, a hardware realization of the trained ensemble estimator is presented for on-chip real-time power estimation. In the experiments, we first show that a single decision tree model can achieve prediction error within 4.51% of a commercial gate-level power estimation tool, which is $2.41\times$ – $6.07 \times $ lower than provided by the commonly used linear model. More importantly, we study the extra gains in inference accuracy using the proposed ensemble model. Experimental results reveal that the ensemble monitoring method can further improve the accuracy of power predictions to within a maximum error of 1.90%. Moreover, the lookup table overhead of the ensemble monitoring hardware employing up to 64 base learners is within 1.22% of the target FPGA, indicating its light-weight and scalable characteristics. [ABSTRACT FROM AUTHOR]

Current and future multicore architectures can significantly accelerate the performance of test automation procedures depending on the underlying architecture and the scalability of their algorithms. This paper proposes a new parallel methodology targeting the fault simulation problem, for shared memory multicore systems, that maintains scalability with the increase of the number of cores. The method is based on a simple single thread process that allows focusing on the optimization of the parallelization process in different dimensions. Additionally, a number of optimizations are incorporated in the approach to control fault dropping and to avoid unnecessary work. The reported experimental results, for both random and deterministic test sets, demonstrate the scalability of the method. As the number of cores increases, the reported speed-up increases proportionally, where comparable recent methods report saturation or even reduction of the obtained speed-up. [ABSTRACT FROM AUTHOR]

In this paper, a graph-constrained sparse performance modeling method is proposed for analog circuit optimization. It builds sparse polynomial models constrained by an acyclic graph. These models can be used to solve analog optimization problems within local design spaces by using convex semidefinite programming relaxation both efficiently and robustly. Our numerical examples demonstrate that the proposed modeling and optimization method can quickly and accurately converge to a superior solution for analog circuits while the conventional method fails to work. [ABSTRACT FROM AUTHOR]