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The low cost, simplicity, and ease of use of paper microfluidic devices have made them valuable medical diagnostics for applications from pregnancy testing to COVID-19 screening. Meanwhile, the increasing complexity of paper-based microfluidic devices is driving the need to produce new tools and methodologies that enable more robust biological diagnostics and potential therapeutic applications. A new design framework is being used to facilitate both research and fabrication of paper-based microfluidic biological devices to accelerate the investigative process and reduce material utilization and manpower. In this work we present a methodology for this framework to dynamically place and route microfluidic components in a nondiscrete design space where fluid volume usage, surface area utilization, and the timing required to perform specified biological assays are accounted for and optimized while also accelerating the development of potentially lifesaving new devices. [ABSTRACT FROM AUTHOR]

Due to the increasing size of integrated circuits (ICs), their design and optimization phases (i.e., computer-aided design, CAD) grow increasingly complex. At design time, a large design space needs to be explored to find an implementation that fulfills all specifications and then optimizes metrics like energy, area, delay, reliability, etc. At run time, a large configuration space needs to be searched to find the best set of parameters (e.g., voltage/frequency) to further optimize the system. Both spaces are infeasible for exhaustive search typically leading to heuristic optimization algorithms that find some tradeoff between design quality and computational overhead. Machine learning (ML) can build powerful models that have successfully been employed in related domains. In this survey, we categorize how ML may be used and is used for design-time and run-time optimization and exploration strategies of ICs. A metastudy of published techniques unveils areas in CAD that are well explored and underexplored with ML, as well as trends in the employed ML algorithms. We present a comprehensive categorization and summary of the state of the art on ML for CAD. Finally, we summarize the remaining challenges and promising open research directions. [ABSTRACT FROM AUTHOR]

Paper-based digital microfluidic biochips (P-DMFBs) have recently emerged as a promising low-cost and fast-responsive platform for biochemical assays. In P-DMFBs, electrodes and control lines are printed on a piece of photograph paper using an inkjet printer and carbon nanotubes (CNTs) conductive ink. Compared with traditional digital microfluidic biochips (DMFBs), P-DMFBs enjoy significant advantages, such as faster in-place fabrication with printer and ink, lower costs, and better disposability. Since electrodes and CNT control lines are printed on the same side of this paper, a critical design challenge for P-DMFB is to prevent control interference between moving droplets and the voltages on CNT control lines. Control interference may result in unexpected droplet movements and thus incorrect assay outputs. To address this design challenge, a control-fluidic codesign methodology is proposed in this paper, along with two demonstrative design flows integrating both fluidic design and control design, i.e., the droplet-oriented codesign flow and the electrode-oriented codesign flow. The droplet-oriented flow is suitable for designing biochips with sparse electrodes and relatively larger number of droplets, whereas the electrode-oriented flow is suitable for biochips with dense electrodes and smaller number of droplets. The computational simulation results of real-life bioassays demonstrate the effectiveness of the proposed codesign flows. [ABSTRACT FROM AUTHOR]

The interaction between technology and healthcare has a long history. However, recent years have witnessed the rapid growth and adoption of the Internet of Things (IoT) paradigm, the advent of miniature wearable biosensors, and research advances in big data techniques for effective manipulation of large, multiscale, multimodal, distributed, and heterogeneous data sets. These advances have generated new opportunities for personalized precision eHealth and mHealth services. IoT heralds a paradigm shift in the healthcare horizon by providing many advantages, including availability and accessibility, ability to personalize and tailor content, and cost-effective delivery. Although IoT eHealth has vastly expanded the possibilities to fulfill a number of existing healthcare needs, many challenges must still be addressed in order to develop consistent, suitable, safe, flexible, and power-efficient systems that are suitable fit for medical needs. To enable this transformation, it is necessary for a large number of significant technological advancements in the hardware and software communities to come together. This keynote paper addresses all these important aspects of novel IoT technologies for smart healthcare-wearable sensors, body area sensors, advanced pervasive healthcare systems, and big data analytics. It identifies new perspectives and highlights compelling research issues and challenges, such as scalability, interoperability, device-network-human interfaces, and security, with various case studies. In addition, with the help of examples, we show how knowledge from CAD areas, such as large scale analysis and optimization techniques can be applied to the important problems of eHealth. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Functional test sequences can detect defects that are not detected by scan-based tests, but overall, achieve a lower gate-level fault coverage than scan-based tests. Design-for-testability (DFT) approaches for functional test sequences cause the sequences to deviate from functional operation conditions in arbitrary ways over the entire design. This paper introduces the concept of invisible-DFT as a DFT approach for functional test sequences, where the effects of activating the DFT logic are confined to selected logic blocks. This paper develops an invisible-scan approach. Considering a single logic block, the procedure described in this paper inserts scan shift cycles into a functional test sequence while maintaining the same primary input and output sequences for the logic block. This makes the activation of the DFT logic invisible to other logic blocks. The procedure allows a limited number of primary output vectors to be corrected for this purpose. Experimental results are presented to demonstrate the increase in fault coverage that can be achieved by invisible-scan. [ABSTRACT FROM AUTHOR]

Alternating-aperture phase shift masking (AAPSM), a form of strong resolution enhancement technology, will be used to image critical features on the polysilicon layer at smaller technology nodes. This technology imposes additional constraints on the layouts beyond traditional design rules. Of particular note is the requirement that all critical features be flanked by opposite-phase shifters while the shifters obey minimum width and spacing requirements. A layout is called phase assignable if it satisfies this requirement. Phase conflicts have to be removed to enable the use of AAPSM for layouts that are not phase assignable. Previous work has sought to detect a suitable set of phase conflicts to be removed as well as correct them. This paper has two key contributions: 1) a new computationally efficient approach to detect a minimal set of phase conflicts, which when corrected will produce a phase-assignable layout, and 2) a novel layout modification scheme for correcting these phase conflicts with small layout area increase. Unlike previous formulations of this problem, the proposed solution for the conflict detection problem does not frame it as a graph bipartization problem. Instead, a simpler and more computationally efficient reduction is proposed. This simplification greatly improves the runtime while maintaining the same improvements in the quality of results obtained in Chiang et al. (Proc. DATE, 2005, p. 908). An average runtime speedup of 5.9× is achieved using the new flow. A new layout modification scheme suited for correcting phase conflicts in large standard-cell blocks is also proposed. The experiments show that the percentage area increase for making standard-cell blocks phase assignable ranges from 1.7% to 9.1%. [ABSTRACT FROM AUTHOR]

This paper describes a test compaction procedure that combines the advantages of using multicycle tests for test compaction with the advantages of using both broadside and skewed-load tests for increasing the fault coverage and achieving test compaction. The procedure is the first to combine these two concepts in a single procedure. The combination is made possible by a definition of a multicycle skewed-load test that is suggested in this paper, and complements the definition of a multicycle broadside test. Experimental results demonstrate the effectiveness of multicycle broadside and skewed-load tests in achieving test compaction for benchmark circuits. [ABSTRACT FROM AUTHOR]

This large volume of special issue includes all regular papers presented at Embedded Systems Week (ESWEEK) 2018 that brings together three leading conferences (CASES, CODES+ISSS, and EMSOFT) in the embedded systems area. ESWEEK is a unique premier event that covers all aspects of embedded systems design and hardware/software architectures. ESWEEK presents a wide range of topics unveiling state-of-the-art techniques as can be found in this special issue. Following the journal-integrated publication model started last year, the three conferences conducted the journal-like two-stage peer-reviewed process before final decision. Acceptance rates have been about 25.5% for all conferences with a total number of 270 submissions to the journal track. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM PUBLISHER]

Intellectual property (IP) cores used in consumer electronics devices mandate protection against reverse engineering (RE) attacks. Functional obfuscation protects the design functionality by enhancing the complexity of RE attacks. This paper proposes a novel low cost (based on power-delay tradeoff) functional obfuscation methodology through employment of robust IP locking technique. In the proposed obfuscation methodology, several strong multipairwise secure IP locking block designs are presented that can only be actuated through application of valid serial key bits. As demonstration, this paper also shows a practical example of a functional obfuscated netlist structure of FIR filter. Proposed obfuscation on comparison with a recent approach for several DSP cores yielded a power reduction of ~10%, design cost reduction ~ 6.5% and security enhancement (strength of obfuscation) of $>\,\,4.29\,\,{e+9}$ times. [ABSTRACT FROM AUTHOR]

The article presents guidelines for authors for electronic submission of manuscripts in the journal including length of paper, word abstracts, and style of papers.

The article presents several instructions for the authors for electronic submission of manuscripts to the journal including paper length, word abstract, and style for papers.

A logic diagnosis procedure provides information about the defects that are present in a faulty unit as a set of candidate faults. To obtain smaller, and more accurate, sets of candidate faults, a diagnostic test generation procedure produces a test set that distinguishes fault pairs. This paper observes that large sets of candidate faults are obtained when multiple defects are present in a faulty unit, even if a diagnostic test set is used for logic diagnosis. This points to the possibility that fault pairs do not provide a complete set of targets for diagnostic test generation. This paper analyzes the conditions that cause a large set of candidate faults to be formed under a particular logic diagnosis procedure and suggests new targets for diagnostic test generation. The experimental results for benchmark circuits demonstrate that a diagnostic test set can be improved by adding diagnostic tests for the new targets. [ABSTRACT FROM AUTHOR]

This retrospective paper describes the RowHammer problem in dynamic random access memory (DRAM), which was initially introduced by Kim et al. at the ISCA 2014 Conference. RowHammer is a prime (and perhaps the first) example of how a circuit-level failure mechanism can cause a practical and widespread system security vulnerability. It is the phenomenon that repeatedly accessing a row in a modern DRAM chip causes bit flips in physically adjacent rows at consistently predictable bit locations. RowHammer is caused by a hardware failure mechanism called DRAM disturbance errors, which is a manifestation of circuit-level cell-to-cell interference in a scaled memory technology. Researchers from Google Project Zero demonstrated in 2015 that this hardware failure mechanism can be effectively exploited by user-level programs to gain kernel privileges on real systems. Many other follow-up works demonstrated other practical attacks exploiting RowHammer. In this paper, we comprehensively survey the scientific literature on RowHammer-based attacks as well as mitigation techniques to prevent RowHammer. We also discuss what other related vulnerabilities may be lurking in DRAM and other types of memories, e.g., NAND flash memory or phase change memory, that can potentially threaten the foundations of secure systems, as the memory technologies scale to higher densities. We conclude by describing and advocating a principled approach to memory reliability and security research that can enable us to better anticipate and prevent such vulnerabilities. [ABSTRACT FROM AUTHOR]

We address the problem of reducing the size of Craig’s interpolants (ITPs) used in SAT-based model checking. Whereas it is well known that ITPs are highly redundant, their compaction is typically tackled by reducing the proof graph and/or by exploiting standard logic synthesis techniques. Furthermore, strengthening and weakening have been studied as options to control ITP quality. In this paper, we propose an SAT-based ITP weakening/strengthening technique, for ITP compaction, where the UNSAT core extracted from an additional SAT query is used to obtain a gate-level abstraction of the ITP. The abstraction introduces fresh new variables at gate cuts that must be quantified out in order to obtain a valid ITP. We show how to efficiently quantify them out, by working on a negation normal form representation of the circuit. This paper includes an experimental evaluation, showing the benefits of the proposed approach, on a set of benchmark ITPs arising from hardware model checking problems. 1 Some of the techniques here described were presented in a preliminary version at FMCAD’16. [ABSTRACT FROM AUTHOR]

This paper defines a new type of a low-power broadside test, called a reverse low-power broadside test, whose application requires design-for-testability logic. The unique feature of a reverse low-power broadside test is that it duplicates the switching activity during the second functional capture cycle of a given low-power broadside test, except that signal-transitions are reversed. Thus, the switching activity of a reverse low-power broadside test duplicates that of a low-power broadside test in every subcircuit and on every line individually. In addition, the reversed test detects different faults, and can thus increase the fault coverage of a low-power broadside test set. This paper studies the ability of reverse low-power broadside tests to increase the transition fault coverage in benchmark circuits considering functional broadside tests as well as low-power broadside tests that are not functional. [ABSTRACT FROM AUTHOR]

This paper focused on nonlinear distortion modeling and characterization of AlGaN/GaN HEMT on SiC substrate using a two-tone intermodulation measurement. The variation of Taylor series coefficients with temperature: linear terms (${G}_{ {m}}$ and ${G}_{ {ds}}$), nonlinear terms (${G}_{ {m2}}$ , ${G}_{ {m3}}$ , ${G}_{ {ds2}}$ , and ${G}_{ {ds3}}$), and the cross terms (${G}_{ {md}}$ , ${G}_{ {md2}}$ , and ${G}_{ {m2d}}$) are reported. Furthermore, in the saturation region, the magnitude of ${G}_{ {ds}}$ related linear, nonlinear, and cross terms (${G}_{ {ds}}$ , ${G}_{ {ds2}}$ , ${ G}_{ {ds3}}$ , ${G}_{ {md}}$ , ${ G}_{ {md2}}$ , and ${G}_{ {m2d}}$) are found to be minimal. This implies that the nonlinear distortion behavior of the device is transconductance-dependent. A temperature-dependent current-based empirical model taking into account bias, input power, and frequency for the nonlinearity of the device has been developed based on two-tone measurements. The modeled data are consistent with the two-tone measurements, providing an effective means for analyzing these devices. [ABSTRACT FROM AUTHOR]

Vertical interconnects used in monolithic 3-D integrated circuits (3-D ICs), so-called monolithic interlayer vias (MIVs), are as small as local vias. Thus, redesigning an existing 2-D IC layout in a monolithic 3-D IC generally results in shorter wire length than the 2-D IC layout. In addition, MIVs have almost negligible resistance and capacitance, so their impact on signal delay is very small. Thus, redesigning a 2-D IC layout in a monolithic 3-D IC is expected to improve its performance significantly. Some researchers designed several monolithic 3-D IC layouts and showed their timing benefits in the literature. In this paper, we present analytical models for performance (timing) benefits of multitier gate-level monolithic 3-D ICs. The analytical models we develop in this paper can be used to quickly estimate the performance benefits multitier gate-level monolithic 3-D integration provides without physically redesigning 2-D IC layouts in 3-D. [ABSTRACT FROM AUTHOR]

The memristor-based memory cell design is getting renewed attention in recent years due to its high speed and low power consumption. This paper aims at designing a novel hybrid memory cell incorporating a minimum number of transistors for a rapid bidirectional write operation. The read stability is one of the key elements for high efficiency and superior performance in memory. The memory cell in this paper was designed undertaking adequate measures for maintaining the stability in successive reads without any refresh operation. Extensive simulation experiments were conducted using 32-nm predictive technology model transistors and the results demonstrate superb performance and sound stability of the proposed memory cell in terms of read/write time as well as switching power consumptions. [ABSTRACT FROM PUBLISHER]

Test generation procedures target a variety of fault models in order to produce test sets that are effective for defect detection. This paper considers the likely scenario where two-cycle skewed-load tests are generated to detect single transition faults, and the test set is complemented with tests for single stuck-at faults that are not detected by the transition fault test set. For this scenario, this paper makes several unique observations that can be utilized to produce a single compact test set that consists only of two-cycle skewed-load tests for both fault models. The first observation is that a single-cycle test for a stuck-at fault can be transformed into a skewed-load test that is guaranteed to detect the stuck-at fault without performing logic or fault simulation. The second observation is that skewed-load tests, which are transformed from single-cycle tests for stuck-at faults, sometimes detect more transition and stuck-at faults than tests that were generated for transition faults. The third observation is that a static test compaction procedure, which is based on the modification and removal of tests, is effective in this context because it allows tests for stuck-at faults to detect more transition faults and vice versa. This paper describes a test compaction procedure based on these observations and presents experimental results for benchmark circuits to demonstrate the effectiveness of the procedure. [ABSTRACT FROM AUTHOR]

Lithography simulation is one of the key steps in physical verification, enabled by the substantial optical and resist models. A resist model bridges the aerial image simulation to printed patterns. While the effectiveness of learning-based solutions for resist modeling has been demonstrated, they are considerably data-demanding. Meanwhile, a set of manufactured data for a specific lithography configuration is only valid for the training of one single model, indicating low data efficiency. Due to the complexity of the manufacturing process, obtaining enough data for acceptable accuracy becomes very expensive in terms of both time and cost, especially during the evolution of technology generations when the design space is intensively explored. In this paper, we propose a new resist modeling framework for contact layers, utilizing existing data from old technology nodes and active selection of data in a target technology node, to reduce the amount of data required from the target lithography configuration. Our framework based on transfer learning and active learning techniques is effective within a competitive range of accuracy, i.e., $3 \times -10 \times $ reduction on the amount of training data with comparable accuracy to the state-of-the-art learning approach. [ABSTRACT FROM AUTHOR]

Accelerator-based chip multiprocessors (ACMPs), which combine application-specific HW accelerators (ACCs) with host processor core(s), are promising architectures for high-performance and power-efficient computing. However, ACMPs with many ACCs have scalability limitations. The ACCs’ performance benefits can be overshadowed by bottlenecks on shared resources of processor core(s), communication fabric/DMA, and on-chip memory. Primarily, this is rooted in the ACCs’ data access and the orchestration dependency. Due to very loosely defined ACC communication semantics, and relying on general architectures, the resources bottlenecks hamper performance. This paper explores and alleviates the scalability limitations of ACMPs. To this end, this paper first proposes ACMPerf, an analytical model to capture the impact of the resources bottlenecks on the achievable ACCs’ benefits. Then, this paper identifies and formalizes ACC communication semantics which paves the path toward a more scalable integration of ACCs. The semantics describe four primary aspects: 1) data access; 2) data granularity; 3) data marshalling; and 4) synchronization. Finally, this paper proposes a novel architecture of transparent self-synchronizing accelerators (TSS). TSS efficiently realizes our identified communication semantics of direct ACC-to-ACC connections often occurring in streaming applications. TSS delivers more of the ACCs’ benefits than conventional ACMP architectures. Given the same set of ACCs, TSS has up to $130 \times $ higher throughput and $78 \times $ lower energy consumption, mainly due to reducing the load on shared architectural resources by $78.3 \times $. [ABSTRACT FROM AUTHOR]

This paper presents two main contributions toward efficient very large scale integration circuits mapped with simple cells: 1) a complete synthesis flow to provide good-quality circuits mapped only with simple cells; and 2) an area-oriented, level-aware buffering algorithm based on inverter trees to fix cell fanout violations. An effective pattern-based algorithm to identify XORs/XNORs on and-inverter graphs is also presented. We show that efficient implementations in terms of inverter count, transistor count, area, power, and delay can be generated from circuits with a reduced number of both simple cells and inverters, combined with XOR/XNOR-based optimizations. The proposed buffering algorithm can handle all unfeasible fanout occurrences, while: 1) optimizing the number of added inverters and 2) assigning cells to the inverter tree based on their level criticality. When comparing with academic and commercial approaches, we are able to simultaneously reduce the average number of inverters, transistors, area, power dissipation, and delay up to 48%, 4%, 8%, 14%, and 16%, respectively. [ABSTRACT FROM AUTHOR]

This paper is the first known composition to demonstrate the application of quintic splines in the development of a dual-gate MOSFET model based on the well-known drift-diffusion system of differential equations used in semiconductor analysis. The techniques and methodologies presented advance the current state of the art in this particular area by implementing improved 2-D numerical techniques and avoiding the use of common accuracy reducing assumptions to decrease semiconductor equation complexity and execution time. This results in a model that is valid in all regions of operation, includes Non-Quasi static transient behavior, accounts for short channel effects, and allows researchers to predict the real world manufacturing effects of gate oxide thickness imperfections and applied gate voltage disparities. Model validation was accomplished by comparing simulation results to previously published experimental data for long and short channel devices as well as data generated using an established commercial product. In addition, a subsequent paper submission is planned to demonstrate the application of this modeling method in determining frequency response for simple CMOS circuits. [ABSTRACT FROM AUTHOR]

We address the problem of reducing the size of Craig’s interpolants used in SAT-based model checking. Craig’s interpolants are AND-OR circuits, generated by post-processing refutation proofs of SAT solvers. Being highly redundant, their compaction is typically tackled by reducing the proof graph and/or by exploiting standard logic synthesis techniques. In this paper, we propose a set of ad-hoc logic synthesis functions that, revisiting known logic synthesis approaches, specifically address speed and scalability. Though general and not restricted to interpolants, these techniques target the main sources of redundancy in combinational circuits. This paper includes an experimental evaluation, showing the benefits of the proposed techniques, on a set of benchmark interpolants arising from hardware model checking problems. [ABSTRACT FROM AUTHOR]

Double-gate devices, like independent-gate (IG) FinFET, have introduced new possibilities and challenges in synthesis of transistor networks. Existing factorization methods and graph-based optimizations are not actually the most effective way to generate optimized IG FinFET based networks because only reducing the number of literals in a given Boolean expression does not guarantee the minimum transistor count. This paper presents two novel methods aiming the minimization of the number of devices in logic networks. The first contribution is a method for defactoring Boolean expressions able to apply the conventional factorization algorithms together with IG FinFET particularities, so improving it. The second contribution is a novel graph-based method that improves even more transistor arrangements by exploiting enhanced nonseries-parallel associations. Experimental results shown a significant reduction in the size of transistor networks delivered by the proposed methods. [ABSTRACT FROM AUTHOR]

The article presents copyright and consent form to be followed for submission of papers in the journal.

This paper presents a two-stage approach to handle fixed-outline floorplanning for mixed size modules, named F-FM. F-FM combines the advantages of the analytical approach and the slicing tree representation. Thus, it is not only suitable for handling fixed-outline floorplanning but also can be extended to handle other important issues in floorplanning such as routability or thermal effect in addition to wirelength. Recently, low power has become big challenges in very large-scale integration designs, which makes voltage-island driven floorplanning more important than ever. Although the problem has been discussed by previous works, no paper considers signal wirelength, powerplanning, and voltage drop at the same time under the fixed-outline constraint. Thus, this paper extends F-FM to handle this problem and consider these issues by properly dividing modules in a voltage domain into several islands. The experimental results show our approach obtains the best results in these problems. [ABSTRACT FROM AUTHOR]

A novel test pattern generation method for multiple dc and ac faults is presented. The fault models considered include line stuck-at, bridging, transition, and transistor stuck-open faults. All faults are transformed into stuck-at faults with some constraints in the proposed two-timeframe circuit model such that all considered faults can be represented utilizing the user-defined fault model supported currently by most commercial ATPG tools. This makes it possible to generate a compact set of patterns for both dc and ac faults in one ATPG run without needing to modify the ATPG tool. Both launch-on-capture and launch-on-shift test methods are supported. The experimental results on ISCAS’89 and ITC’99 benchmark circuits show the effectiveness of the proposed method (PM) compared to earlier PMs. [ABSTRACT FROM AUTHOR]

Detailed routing is one of the most challenging aspects of the physical design process. Many of the violations that occur during the detailed routing stage stem from the placement of the cells. In this paper, we propose a deep learning framework to identify short violations that can occur during detailed routing from a placed netlist. One of the advantages of our technique is that by using the proposed deep learning-based predictor, global routing is no longer required as frequently and hence the total runtime for place and route can be significantly reduced. In this paper, we discuss the proposed framework and the methodology for analyzing the extracted features. The experimental results show that the average sensitivity, specificity, and accuracy of Eh?Predictor is above 90%. In addition, we show that Eh?Predictor is up to 14 times faster than NCTUgr for smaller designs and up to 96 times faster for larger designs. [ABSTRACT FROM AUTHOR]

Using high-level synthesis techniques, this paper proposes an adaptable high-performance streaming dataflow engine for sparse matrix dense vector multiplication (SpMV) suitable for embedded FPGAs. As the SpMV is a memory-bound algorithm, this engine combines the three concepts of loop pipelining, dataflow graph, and data streaming to utilize most of the memory bandwidth available to the FPGA. The main goal of this paper is to show that FPGAs can provide comparable performance for memory-bound applications to that of the corresponding CPUs and GPUs but with significantly less energy consumption. The experimental results indicate that the FPGA provides higher performance compared to that of embedded GPUs for small and medium-size matrices by an average factor of 3.25 whereas the embedded GPU is faster for larger size matrices by an average factor of 1.58. In addition, the FPGA implementation is more energy efficient for the range of considered matrices by an average factor of 8.9 compared to the embedded CPU and GPU. A case study based on adapting the proposed SpMV optimization to accelerate the support vector machine (SVM) algorithm, one of the successful classification techniques in the machine learning literature, justifies the benefits of utilizing the proposed FPGA-based SpMV compared to that of the embedded CPU and GPU. The experimental results show that the FPGA is faster by an average factor of 1.7 and consumes less energy by an average factor of 6.8 compared to the GPU. [ABSTRACT FROM AUTHOR]

This paper presents a memristive device model capable of accurately matching a wide range of characterization data collected from a tantalum oxide memristor. Memristor models commonly use a set of equations and fitting parameters to match the complex dynamic conductivity pattern observed in these devices. Along with the proposed model, a procedure is also described that can be used to optimize each fitting parameter in the model relative to an I–V curve. Therefore, model parameters are self-updated based on this procedure when a new cyclic I–V sweep is provided for model optimization. This model will automatically provide the best possible match to the characterization data without any additional optimization from the user. In this paper, multiple cyclic I–V characterizations are modeled from ten different tantalum oxide devices (on the same wafer). Additionally, studies were completed to demonstrate the amount of variation present between devices on a wafer, as well as the amount of variation present within a single device. Methods for modeling this variation are then proposed, resulting in an accurate and complete, automated, memristor modeling approach. [ABSTRACT FROM AUTHOR]

For practical testing and detection of electromigration (EM) induced failures in dual damascene copper interconnects, one critical issue is creating stressing conditions to induce the chip to fail exclusively under EM in a very short period of time so that EM sign-off and validation can be carried out efficiently. Existing acceleration techniques, which rely on increasing temperature and current densities beyond the known limits, also accelerate other reliability effects making it very difficult, if not impossible, to test EM in isolation. In this paper, we propose novel EM wear-out acceleration techniques to address the aforementioned issue. First, we show that multisegment interconnects with reservoir and sink structures can be exploited to significantly speedup the EM wear-out process. Based on this observation, we propose three strategies to accelerate EM induced failure: 1) reservoir-enhanced acceleration; 2) sink-enhanced acceleration; and 3) a hybrid method that combines both reservoir and sink structures. We then propose several configurable interconnect structures that exploit atomic reservoirs and sinks for accelerated EM testing. Such configurable interconnect structures are very flexible and can be used to achieve significant lifetime reductions at the cost of some routing resources. Using the proposed technique, EM testing can be carried out at nominal current densities, and at a much lower temperature compared to traditional testing methods. This is the most significant contribution of this paper since, to our knowledge, this is the only method that allows EM testing to be performed in a controlled environment without the risk of invoking other reliability effects that are also accelerated by elevated temperature and current density. The simulation results show that using the proposed method, we can reduce the EM lifetime of a chip from ten years down to a few hours (about ${10^{5}} \times $ acceleration) under the 150 °C temperature limit, which is sufficient for practical EM testing of typical nanometer CMOS ICs. [ABSTRACT FROM AUTHOR]

Excessive switching activity in the fault-free circuit can cause a fault-free circuit to fail because of increased delays. For the same reason, excessive switching activity in a faulty circuit can cause a delay fault to escape detection. This paper observes that the switching activity is higher in the presence of multiple delay faults with higher multiplicities (larger numbers of single faults that are present in the circuit together). The challenge in addressing multiple faults is related to their large number. This paper addresses this challenge by an iterative procedure that is applied to transition faults under a low-power broadside test set, and has two subprocedures: 1) the first subprocedure finds multiple transition faults with excessive faulty switching activity and 2) the second subprocedure modifies the test set so as to avoid excessive faulty switching activity for the faults found by the first subprocedure. With every additional iteration there are fewer multiple transition faults that exhibit excessive faulty switching activity. The experimental results for benchmark circuits demonstrate the levels of excessive faulty switching activity in the presence of multiple transition faults, and the possibility of reducing or even eliminating it after a small number of iterations. [ABSTRACT FROM AUTHOR]

This paper presents a multidimensional computational method to predict the spatial variation data inside and across multiple dies of a wafer. This technique is based on tensor computation. A tensor is a high-dimensional generalization of a matrix or a vector. By exploiting the hidden low-rank property of a high-dimensional data array, the large amount of unknown variation testing data may be predicted from a few random measurement samples. The tensor rank, which decides the complexity of a tensor representation, is decided by an available variational Bayesian approach. Our approach is validated by a practical chip testing data set, and it can be easily generalized to characterize the process variations of multiple wafers. Our approach is more efficient than the previous virtual probe techniques in terms of memory and computational cost when handling high-dimensional chip testing data. [ABSTRACT FROM AUTHOR]

Heterogeneous multiprocessor systems on a chips (MPSoCs) consisting of cores with different performance/power characteristics are widely used in many real-time embedded systems, where both soft-error reliability and lifetime reliability are key concerns. Although existing efforts have investigated related problems, they either focus on one of the two reliability concerns or propose time-consuming scheduling algorithms that cannot adequately address runtime workload and environmental variations. This paper introduces an online framework which is adaptive to runtime variations and maximizes soft-error reliability while satisfying the lifetime reliability constraint for soft real-time systems executing on MPSoCs that are composed of high-performance cores and low-power (LP) cores. Based on each core’s executing frequency and utilization, the framework performs workload migration between high-performance cores and LP cores to reduce power consumption and improve soft-error reliability. Experimental results based on different hardware platforms show that the proposed approach reduces the probability of failures due to soft errors by at least 17% and 50% on average compared to a number of representative existing approaches that satisfy the same lifetime reliability constraints. [ABSTRACT FROM AUTHOR]

In high-throughput drug screening applications, as manual drug sample delivery is time-consuming and error-prone, there is an urgent need for accurate and efficient drug sample delivery biochip for large-scale microwell arrays. This paper proposes a new microfluidic biochip architecture, where drugs are automatically prepared with different concentration values, and then delivered into multiple microwells. For large-scale drug sample delivery biochips, the routing of drug sample delivery channels is a very challenging task without effective routing solutions. This paper proposes an ultrafast rule-based escape routing method, called URBER, to address the large-scale routing of drug sample delivery channels, which scales well in both runtime and memory even for a very large problem size. URBER runs very fast because it routes channels based on a set of predefined rules, which avoids runtime consumed in solution space exploration. All benchmarks for 30 ${\le }~{N}$ , ${M} {\le }~100$ have been tested, where ${N}$ and ${M}$ are the number of columns and rows of the terminal array. Among these benchmarks, about ~91.9% are routed with optimal solutions, and the runtime is order of magnitudes faster than optimal min-cost flow-based methods (speedup is from ~600 to ~340 k). Specifically, for all benchmarks with (${M}/{N}$) ${\in }$ ((3/4), (4/3)), optimal routing solutions are always obtained. URBER also shows promise of routing large-scale designs with up to 500 k terminals efficiently. [ABSTRACT FROM AUTHOR]

Reliably and power efficiently securing integrated systems against advanced power analysis attacks (PAAs) is a significant design challenge in modern integrated circuits. Power masking and hiding are typical countermeasures for increasing system resilience for power attacks at the expense of the overall system performance and power efficiency. These method are, however, not able to alert the user or trigger additional protective actions in case of the attack. In this paper, a method for detecting power attacks in real-time is proposed. The proposed approach exploits statistical methods to analyze the on-chip voltage variations across an on-chip power grid and detect the attacker probe connected to the system. The problem of the full security coverage of the power grid is formulated and solved in this paper. Adjusting the density of the on-chip sensors and exploiting sparse analysis techniques is considered to simultaneously enhance the accuracy and power efficiency of the proposed solution. The proposed attack detection system is designed, simulated, and evaluated in Simulink based on IBM microprocessor benchmark data. Machine learning (ML) models are trained in Python and with scikit-learn ML library. The proposed system has been demonstrated to efficiently detect PAA within a period of time that is orders of magnitude shorter than a typical attack duration length. The system is expected to exhibit high detection accuracy and power efficiency across a wide spectrum of integrated systems. [ABSTRACT FROM AUTHOR]

We present an algorithm for passivity verification and enforcement of multivariate macromodels whose state-space matrices depend in closed form on a set of external or design parameters. Uniform passivity throughout the parameter space is a fundamental requirement of parameterized macromodels of physically passive structures, that must be guaranteed during model generation. Otherwise, numerical instabilities may occur, due to the ability of nonpassive models to generate energy. In this paper, we propose the first available algorithm that, starting from a generic parameter-dependent state-space model, identifies the regions in the frequency-parameter space where the model behaves locally as a nonpassive system. The approach we pursue is based on an adaptive sampling scheme in the parameter space, which iteratively constructs and perturbs the eigenvalue spectrum of suitable skew-Hamiltonian/Hamiltonian pencils, with the objective of identifying the regions where some of these eigenvalues become purely imaginary, thus pinpointing local passivity violations. The proposed scheme is able to detect all relevant violations. An outer iterative perturbation method is then applied to the model coefficients in order to remove such violations and achieve uniform passivity. Although a formal proof of global convergence is not available, the effectiveness of the proposed implementation of the passivity verification and enforcement schemes is demonstrated on several examples. [ABSTRACT FROM AUTHOR]

The demand for multitasking GPUs increases whenever the GPU may be shared by multiple applications, either spatially or temporally. This requires that GPUs can be preempted and switch context to a new application while already executing one. Unlike CPUs, context switching in GPUs is prohibitively expensive due to the large context states to swap out. There have been a number of efforts on reducing the overhead of preemption, through reducing the context sizes or overlapping context switching with execution. All those techniques are reactive approaches, meaning that context switching occurs when the preemption request arrives. In this paper, we propose a dynamic and proactive mechanism to reduce the latency of preemption. We observe that kernel execution is almost always preceded by known commands in both CUDA and OpenCL implementations. Hence, a preemption can be anticipated before the actual request arrives. We study such lead time and develop a prediction scheme to perform an early state saving. When the actual preemption is invoked, an incremental update relative to the previous saved state is performed, much like the conventional checkpointing mechanism. Our design can also choose to drain or checkpointing dynamically and accurately according to the feature of kernels in the runtime. This design effectively reduces the stall time of the preempting kernel due to context switching by 58.6%. Moreover, through careful handling of the saved state, we can also reduce the overall size of saved state by an average of 23.3%, compared with a full context switching. [ABSTRACT FROM AUTHOR]

Decomposition is a technology-independent process, in which a large complex function is broken into smaller, less complex functions. The costs of two-level or factored-form representations (cubes and literals) are used in most decomposition methods, as they have a high correlation with the area of cell-based designs. However, this correlation is weaker for field-programmable gate arrays (FPGAs) based on look-up tables. Furthermore, local optimizations have limited power due to the structural bias of the circuit descriptions. This paper tries to reduce the structural biasing by remapping the look-up table network and decomposing the derived functions using the support as cost function. The proposed method improves the FPGA mapping results of a commercial tool for the 20 largest MCNC benchmarks, with gains of 28% in delay plus 18% in area when targeting delay, and a reduction of 28% in area plus 14% in delay with area as cost function. Results with 23% less area and 6% less delay are obtained after physical synthesis (post place-and-route). Moreover, 12 of the best known results for delay (and 3 for area) of the EPFL benchmarks are improved. [ABSTRACT FROM AUTHOR]

In automotive embedded real-time systems, e.g., the engine control unit, tasks are activated whenever the engine arrives at a specific angular position. In consequence the frequency of activation changes with the speed of the engine. Additionally, the execution times and deadlines may also depend on the engine speed. In recently published works analytical methods for tasks with this rate-dependent behavior were introduced. Though those methods do not consider angular phases between tasks. For instance, in a typical engine control unit one event is displaced a certain angular position after an event of another task. This paper introduces a sufficient analysis, which considers such angular phases. A number of experimental results are reported to compare our method with existing analysis. These illustrate the improvement in terms of precision and runtime. [ABSTRACT FROM AUTHOR]

This paper presents InnovA, a cognitive architecture for creative problem solving in analog circuit design, e.g., topology creation (synthesis), incremental topology modification, and design knowledge identification and reuse. The architectural modules attempt to replicate cognitive human activities, like concept formation, comparison, and concept combination. The architecture uses multiple knowledge representations organized using topological similarity and causality information. Solutions are clustered, so that each cluster represents a specific set of performance tradeoffs, thus a fragment of the Pareto front in the solution space. New structural features are created through variation of existing features. New solutions are created by combining features from the same cluster, distinct clusters, and features that originate a new cluster. The related algorithms are discussed in this paper too. The architecture also incorporates modules mimicking the using of human emotions in memory formation and decision making, but these modules are still under development and are a main direction for our future work. This paper presents a number of examples to illustrate its using in various analog circuit design activities that are hard to be realized with traditional computational methods. [ABSTRACT FROM AUTHOR]

This paper defines a new type of multicycle tests called autonomous multicycle tests. Similar to multicycle scan-based tests, autonomous multicycle tests include several consecutive functional capture cycles to enhance defect detection and achieve test compaction. Unlike multicycle scan-based tests, an autonomous multicycle test set uses the same initial state for all the tests. During the functional capture cycles of a test, the primary inputs are driven by primary outputs, and the circuit operates autonomously. A test uses a scan-in operation only for the initial primary input vector, and to determine the connection between the primary inputs and outputs. It uses a scan-out operation only for the final primary output vector. This results in reduced overheads related to storage requirements and test application time compared with scan-based tests, and several unique properties that are discussed in this paper. This paper describes a test generation procedure for autonomous multicycle tests that avoids sequential test generation, and presents experimental results to demonstrate the ability of the tests to detect target faults. [ABSTRACT FROM AUTHOR]

The vertical interlayer communication channel plays a critical role in defining the performance of a 3-D network-on-chip (NoC). In this paper, an arbitration-free design for the shared vertical channels is proposed. The proposed vertical arbitration-free 3-D NoC is compared with other 3-D NoC architectures using traditional synthetic traffic patterns and Rentian traffic emulating applications for chip multiprocessors. The results of the analysis show comparable performance in throughput, energy, and latency compared to a symmetric 3-D NoC with savings up to $\approx { 20\%}$ in area. The proposed NoC is superior in performance to a 3-D NoC utilizing vertical arbitration with a similar area footprint. [ABSTRACT FROM AUTHOR]

In this paper, we propose a training framework for an inverter-based memristive neuromorphic hardware. The framework, which is called PHAX, is a physical characteristics aware one relying on an ex-situ training approach. The considered neuromorphic circuit is highly energy efficient hybrid CMOS-memristive implementation of neuromorphic circuits. To solve the problem of high sensitivity of the training to the mismatches between the high-level mathematical modeling of the neurons and the corresponding physical characteristics, an approach for analytical yet accurate modeling of the memristive crossbar and neuron circuits is suggested. The approach, which is based on SPICE simulations, models the inverter-based neurons using a hyperbolic tangent function. To increase the training efficacy, the backpropagation training algorithm is modified by considering some constraints based on the physical characteristics of the memristive circuit. This modification along with the accurate back-annotation of the physical characteristics considerably improve the effectiveness of the ex-situ training method of the neuromorphic circuit. The results of this paper show an average reduction of $1805{\times }$ in the training runtime compared to that of the in-situ training approach. Furthermore, the results of applying the approach on the kernels of some applications such as image recognition, image processing, and financial analysis reveal that the designed neuromorphic circuits provide an average power saving (speed up) of $1478{\times }$ ( $5.2{\times }$ ) over the ASIC implementation in a 90-nm CMOS technology. [ABSTRACT FROM AUTHOR]

Analyzing the timing properties of asynchronous systems is essential for characterizing their performance and power. Previous work on timing showed that such systems under and-causality and fixed delay exhibit periodicity properties. We give a different graph-based rigorous proof of the exact timing behavior of more general classes of such systems, and conclude their exact periodicity property, where each of the signal transition will occur with the same period after finite occurrences. We established our results under weaker assumption about system connectivity/topology, and this paper provides the theoretical foundation, for the exact periodicity property to be applied and exploited in circuits containing a combination of synchronous and asynchronous components. We provide simulation-based results for several typical asynchronous circuit topologies to quantify this time period in practical circuits. We also provide an extension of our analysis and methods to the case of bounded delay systems. A key result that is a consequence of our analysis is that asynchronous circuits can be integrated with synchronous logic via a metastability-free interface, thereby eliminating the high-overhead synchronizers when an asynchronous circuit is fully surrounded by synchronous logic. [ABSTRACT FROM PUBLISHER]