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This paper proposes a new method to improve re performance of intra-field interpolation which is the mos~ important element of deinterlacing method. Traditional edge- based methods were poor at determining accurate edge iirection which decides interpolation performance. The 7roposed method decides the direction and slope of edge based on locally adaptive-thresholded binary image to mprove efficiency and accuracy, and it also increased the ~orizontal size of search window to 15 for better direction ietermination at gentle slope. Compared to traditional edge- based methods, interpolation based on binary image, which is ,`enerated using the proposed method, leads to great erformance improvement. With computer simulations for a ~`ariety of images, this paper shows the new approach is much ~etter than traditional methods.. [ABSTRACT FROM AUTHOR]

This paper presents an implementation of an ~daptive beamformer in a hands-free unit. The proposec~ ~daptive beamformer suppresses stationary noise an~ nterference sound. The adaptive beamformer and acoustic `cho canceller were implemented in a compact hands-free mit with a low-cost DSP. Experimental results demonstrate he noise reduction performance of the hands-free unit'. [ABSTRACT FROM AUTHOR]

Smartphones dominate the consumer electronics market. Heterogeneous multicore processors are nowadays often integrated into smartphones. The power and performance evaluation of mobile multicore processors is a key issue in their design. This paper is the first to address the issue of improving the power and performance in modern, multicore smartphones by revisiting existing benchmarks used for evaluating these devices. Unlike earlier computers, modern consumer devices execute workloads that are characterized by heterogeneous concurrently running processes, which are launched at different times. Yet, modern smartphones architecture designs are still being evaluated using representative benchmark suites comprised of individual programs. This method of evaluation can be very misleading, as it does not represent the way these devices are actually being used. This paper first proposes a novel learning framework that identifies representative usage patterns of various real workloads, where each representative pattern represents a single class in a heterogeneous collection of actual usage patterns. We then use these representative patterns to optimize the power and performance of common multicore computer architectures integrated into smartphones. Our experiments show that using our representative patterns for optimization results in,on average, 11.5% and 16.7% power and performance improvements, respectively, compared to the state-of-art optimization methods. [ABSTRACT FROM AUTHOR]

A display wall, one of the multiple display environments (MDEs), has been widely adopted in various fields including consumer electronics. Conventional display walls are constructed by utilizing cluster-based systems where multiple displays are connected via multiple cluster nodes. However, cluster-based systems have suffered from communication overheads among the cluster nodes when they provide interaction features and run diverse applications. This paper proposes a software-based single-node multi-GPU system for interactive display walls. The proposed system allows multiple GPUs in a single-node system to connect multiple displays, by providing an individual compositor for each GPU in the system. This paper also analyzes memory management models of multi-GPU systems and compositing overheads for multiple displays. Experimental results show that the FPS (frames per second) of the proposed system outperforms that of the conventional system by up to 1.36x, reducing copy overheads among the GPUs by efficient memory management and distributing compositing overheads to multiple GPUs. [ABSTRACT FROM PUBLISHER]

Standby power refers to the electric power consumed by electronic appliances while they are in a standby mode. As the electronic appliance have become smarter, they consume more standby power. To reduce wasted electricity, techniques to save standby power have been developed in conjunction with network and communication technologies. Automatic standby power saving systems have been developed, but the proposed systems do not consider the cost reduction, user satisfaction, and personalized environment. Furthermore, to provide automation, an intelligent system for collected information is required, which increases the cost of system integration. Therefore, this paper proposes cloud based ondemand standby power management using consumer pattern racking to address these problems to deal with these issues. The proposed system offers rule based management services with three usage types determined by user preferences and living patterns. The total power consumption is measured to verify the performance of the system. The proposed system reduces the power consumption up to 9.3%1. [ABSTRACT FROM PUBLISHER]

This paper proposes an efficient hardware architecture to accelerate adaptive deblocking filter of H.264/AVC video coding. Compact data access unit, Line-of- Pixel (LOP) is defined in this paper. Line-of-Pixel and build- in data buffer are employed to simplify data exchange between deblocking filter and outside data memory. Edge filter, which is designed to process each group of pixels on both sides of one edge, is kernel of deblocking filter. It is implemented in multiple parallel pipelines to increase efficiency. By carefully design, the proposed deblocking filter can be embedded in general-purpose processor or DSP to support special instructions for acceleration of software codec. This filter also can be used to full hardware H.264/AVC codec. [ABSTRACT FROM AUTHOR]

This paper proposes general software optimization techniques for embedded systems based on processors, which mainly include general optimization methods in high language and software & hardware co-optimization in assembly language. Then these techniques are applied to optimize our MP3 decoder, which is based on RISC32, a RISC core compatible with MIPSI instruction set The last optimization decoder requires 48 MIPS and 49Kbytes memory space to decode 128Kbps, 44.1KHz joint stereo MP3 in real time with CPI 1.15, and we have achieved performance increase of 46.7% and memory space decrease of 38.8% over the original decoding software. [ABSTRACT FROM AUTHOR]

In recent years, the advances in wireless communication and electronics have accelerated to develop many wireless network solutions to replace existing wired networks. A wireless network solution can support mobility and flexibility of nodes in a network. Especially in sensor networks, it has many advantages to replace cables with wireless logical links. On the other hand, Bluetooth is generally considered as a promising short-range wireless technology because of its inexpensive cost, low power and small size, and thus Bluetooth has been gaining increasing interest from various industries. For the above reasons, we adopt Bluetooth technology for a wireless sensor network which is designed for security systems. Since Bluetooth will continue to be a feature found in many devices, it is worthwhile to investigate its use in wireless sensor networks. In this paper, we describe a Bluetooth wireless sensor network for security systems, which includes the implementation issues about system architecture, power management, self- configuration of network, and routing. We think that the methods or algorithms described in this paper can be easily applied to other embedded Bluetooth applications for wireless networks. [ABSTRACT FROM AUTHOR]

We have been seeing use of word “smart” before almost anything that we can think of in our day-to-day life: smart phone, smart TV, and smart appliance. At a bigger scale smart cities, smart villages, smart healthcare, and smart agriculture, are used to describe new generation of these physical entities. So, an obvious question: What is smart? From dictionary, smart means: “(of a person) clean, tidy, and well dressed” and “(of a device) programmed so as to be capable of some independent action.” Thus, smart and intelligence is the “ability to take decisions based on the data, circumstances, situations.” [ABSTRACT FROM AUTHOR]

Histogram computation is a fundamental task often encountered in image processing systems. This plays an important role in various applications like image registration, show-through correction method in scanned image of duplex mode printed document, etc. Mutual information (MI) is one of the best metric for intensity-based multimodality image registration. Similarity measurement between the images consumes significant amount of the execution time in image registration. Computation of MI requires to obtain individual and joint histogram of two images. Typical joint histogram sizes range between 322 and 2562. The demand of hardware resource for computation of histogram increases substantially with increasing of histogram size. The array-based method may not be a suitable candidate in this application, because of large histogram size. Computation of histogram is inherently sequential in nature. But a parallel computation of histogram would reduce the processing time, which is going to help various imaging systems. In this paper, a memory-based parallel algorithm for histogram computation and its possible VLSI architecture have been presented. The architecture is mapped in field programmable gate array. The proposed architecture utilizes 99.66% less of the hardware compared to latest available architecture in the literature and consumes 8.78 mW power. [ABSTRACT FROM AUTHOR]

High Efficiency Video Coding (HEVC) intra mode decision algorithm has very high computational complexity. Therefore, in this paper, a computation and energy reduction technique is proposed for reducing the amount of computations performed by Sum of Absolute Transformed Difference (SATD) calculations in HEVC intra mode decision, and therefore reducing the energy consumption of HEVC SATD calculation hardware without any PSNR loss and bit rate increase. The proposed technique reduced the energy consumption of HEVC SATD calculation hardware up to 64.6%. Therefore, it can be used in portable consumer electronics products that require a real-time HEVC encoder. [ABSTRACT FROM PUBLISHER]

The use of NAND flash memory is increasing in consumer electronics. Because an out-of-place update scheme is used to address the erase-before-write hardware constraint in NAND flash memory, a garbage collection algorithm should be designed into the flash translation layer (FTL) or the flashspecific file system to reclaim garbage pages and obtain free space. In this paper, an efficient file-aware garbage collection algorithm, called FaGC, is proposed for NAND flash memory systems in consumer electronics. The purpose of the proposed algorithm is to reduce garbage collection overhead and improve wear leveling in NAND flash memory systems. The experimental results show that the proposed algorithm outperforms existing garbage collection algorithms in terms of the number of copy operations, the number of erase operations, and the degree of wear leveling. Additionally, with limited cost, a desired degree of wear leveling can be achieved using a predesignated value, which is advantageous for NAND flash memory systems in consumer electronic devices. [ABSTRACT FROM PUBLISHER]

In this paper, we present a unified architecture that can perform Discrete Cosine Transform (DCT), Inverse Discrete Cosine Transform (IDCT), DCT domain motion estimation and compensation (DCT-ME/MC). Our proposed architecture is a Wavefront Array-based Processor with a highly modular structure consisting of 8×8 Processing Elements (PEs). By utilizing statistical properties and arithmetic operations, it can be used as a high performance hardware accelerator for video transcoding applications. We show how different core algorithms can be mapped onto the same hardware fabric and can be executed through the pre-defined PEs. In addition to the simplified design process of the proposed architecture and savings of the hardware resources, we also demonstrate that high throughput rate can be achieved for IDCT and DCT-MC by fully utilizing the sparseness property of DCT coefficient matrix. [ABSTRACT FROM AUTHOR]

NAND flash memory has been widely used for storage in embedded systems and recently in enterprise computing environment, owing to its shock-resistance, non- volatile, low energy consumption, and high I/O speed. In addition, flash memory has the characteristics of not-in-place update and asymmetric I/O costs among read, write, and erase operations, in which the cost of write/erase operations is much higher than that of read operation. Hence, the buffer replacement algorithms in flash-based systems should take the asymmetric I/O costs into account. Previous solutions to this issue, such as CFLRU and LRU-WSR, used a clean-first scheme to first evict clean pages from the buffer. Although they outperform the traditional LRU policy in performance, they do not consider the access frequency of clean page, which will consequently result in poor I/O performance. In order to solve this problem, we present a new buffering algorithm in this paper, called CCF-LRU, which enhances the previous CFLRU and LRU-WSR methods by differentiating clean pages into cold and hot ones, and evicting cold clean pages first and delaying the eviction of hot clean pages. We conduct a trace-driven experiment on a flash memory simulation environment, and use six types of synthesized traces as well as a real OLTP trace. The results show that the CCF-LRU algorithm outperforms LRU, CFLRU and LRU-WSR in write count and runtime in all experiments. In particular, it provides more than 20% improvement over its competitors both in write count and runtime, when running the real OLTP trace. [ABSTRACT FROM AUTHOR]

This paper presents the novel development of an embedded system that aims at digital TV content recommendation based on descriptive metadata collected from versatile sources. The described system comprises a user profiling subsystem identifying user preferences and a user agent subsystem performing content rating. TV content items are ranked using a combined multimodal approach integrating classification-based and keyword-based similarity predictions so that a user is presented with a limited subset of relevant content. Observable user behaviors are discussed as instrumental in user profiling and a formula is provided for implicitly estimating the degree of user appreciation of content. A new relation-based similarity measure is suggested to improve categorized content rating precision. Experimental results show that our system can recommend desired content to users with significant amount of accuracy. [ABSTRACT FROM AUTHOR]

The use of NAND flash memory for building permanent storage has been increasing in many embedded systems due to idiosyncrasies such as non-volatility and low energy consumption. The persistent requirements for high storage capacity have given rise to the increase of bit density per cell as in multi-level cells but this has come at the expense of performance and has resulted in degradation of durability. in this paper, we introduce a complementary approach to boost the performance and durability of MLC-based storage systems by employing a non-volatile buffer that temporarily holds the data heading to MLCs. We also propose algorithms to efficiently eliminate unnecessary write and erase operations in MLCs by performing a pre-merge in the buffer. Our experiments show that the proposed approach can decrease average response time by up to 4 times and increase durability by 4 times by adding only a small hardware cost. [ABSTRACT FROM AUTHOR]

This paper presents an efficient architecture for computing the eight-point ]-D scaled DCT (Discrete Cosine Transform) with a new algorithm based on a selected Loeffier DCT scheme whose multiplications are placed in the last stage. The proposed DCT architecture does not require any scaling compensation in the computation. Furthermore, a multiplication approximation method is developed, which is more efficient than traditional CORDIC (Coordinate Rotation Digital Computer) -based algorithms. Compared to the latest work [8], the proposed approach can save 14% addition operations for the same precision requirement and the path delay can be significantly reduced as well. [ABSTRACT FROM AUTHOR]

AVS-P7 is the recent mobile video coding standard of China. Currently, ARM cores are widely used in mobile applications because of their low power consumption. In this paper a scheme of the AVS-P7decoder real-time implementation on 32 bit MCU RISC processor ARM920T (S3C2440) is presented. The algorithm, redundancy, structure and memorp optimization methods to implement AVS-P7 real-time are discussed in detail. The experiment results demonstrate the success of our optimization techniques and the real-time implementation. The ADS, MCPS, PSNR and simulation results show that the proposed AVS-P7 decoder can decode the QVGA image sequence in real-time with high image quality and has low complexity and less memory requirement. AVS conformance test result confirms the proposed AVS-P7 decoder full compliance with AVS. The proposed AVS-P 7 decoder can be applied in many real-time applications like Mobile phone and IPTV in the third generation communication. [ABSTRACT FROM AUTHOR]

Rich requirements from High Definition Television (HDTV) decoder argue the supports of complex architecture and Operating System (OS). As an embedded system, mult-processor System-on-a-Chip (MPSoC) is an ideal implementation of the decoder. Open source OS has many advantages to be ported to embedded fields. This paper describes the detailed process of its porting, including building environment, kernel modification, and debug. The porting specifications are constrained by the resources on the HDTV SoC platform, development period, debug efforts, and system robustness, etc. As an application of the open source OS, our work shows the joint of industry practice and theory research. [ABSTRACT FROM AUTHOR]

In this paper we present a pipelined hardware implementation of In-loop Deblocking Filter in H.264/AVC. A pipelined datapath has been adopted to boost the speed of the deblocking filter process. The processing order of the filter is rearranged to facilitate the deblocking of the pixels in a pipelined fashion. A suitable buffer mechanism has also been proposed that reduces the size of the on-chip SRAM and redundant external memory accesses. The hardware implementation, under TSMC 0.13 µm standard cell library, consumes only 7.5 K gates at a clock frequency of 200MHz. Our architecture supports real-time deblocking of high resolution (2048×1024) video applications at 30 fps over three channels. [ABSTRACT FROM AUTHOR]

This paper presents new embedded system architecture (ESA) for improving the voice quality in a WLAN/Cellular dual-mode mobile phone. The proposed architecture is based on a dual-core scheme and its main functional blocks are composed of VoIP Remote Procedure Call (VRPC), an audio bridging scheme, and a Server-Assisted Call Management (SACM) algorithm. In order to illustrate the aims of the proposed approach, prototype systems are implemented, and evaluated by measuring average Mean Opinion Score (MOS), and Mouth-To-Ear (M2E) delay. The experimental results show that the proposed approach results in greatly improved voice quality. [ABSTRACT FROM AUTHOR]

This paper proposes a noise-reduction method to improve the channel-estimation performance in Digital Video Broadcasting-Terrestrial (DVB-T) receivers. In DVB-T, the channel estimation is carried out through two processes of pilot signal estimation and channel coefficient interpolation and thus the performance of the channel estimation is seriously affected by the accuracy of the interpolation. Since the accuracy of the interpolation depends on signal-to-noise ratio, it is important to reduce noise existing at the reference coefficients for the interpolation. To achieve the reduction of noise, we use pilot-insertion type approximation in four consecutive OFDM symbols, which construct one block with the same channel coefficients at the same pilot positions. Considering the fade rate of channels, we average the estimated reference channel coefficients corresponding to the same subcarriers in two or more blocks. Computer simulation shows that the proposed method improves the estimation performance by more than 1 dB in terms of the symbol error rate obtained after equalization. [ABSTRACT FROM AUTHOR]

This investigation presents an embedded analog spatial filter, EASF, in a current-mode CMOS image sensor. The EASF successfully identifies the output value of the pixel in B/W so as to benefit specific real world applications. Over the last few years, image quality has been improved by better progress in CMOS process technology, however, low cost issue regarding the integration of backend circuit still is an important competition point in imager design. Embedding an analog mask filter in a CMOS image sensor not only reduces cost, but also improves speed and simplicity of design integration with the backend image processing circuit In this paper, a 66 × 66 embedded sensor array has been implemented in TSMC 0. 35 μm CMOS process. Each pixel occupies a 13.8 μm × 9.8 μm area with afill factor of 31.2%. The power consumption is 71.14mW when the sensor operates at 32 frames/sec. [ABSTRACT FROM AUTHOR]

This paper deals with fast computation of some operations included in the digital video (DV) coding standard. The proposed solution converts floating-point arithmetic operations into integer arithmetic operations, replacing highly computational demanding blocks such as discrete cosine transform (DCT), weighting (W) and quantization (Q) by fast integer calculations using only shifts and additions. The overall computational complexity was reduced by 73% in comparison to a floating-point implementation. Our solution is suitable to be programmed into any fixed-point arithmetic processor decreasing the consumer equipment cost. This solution is still compatible with the standard in terms of the DCT precision requirements. [ABSTRACT FROM AUTHOR]

This paper addresses the problem of abnormal acoustic event detection in indoor surveillance systems related to safety and security. The proposed concept event detector determines if the acoustic state is either normal or abnormal from accumulated series of acoustic signals using MFCC and deltas coefficients as acoustic feature vectors and a multiclass Adaboost based acoustic context classifier. A novel concept of adopting an exponential criterion and weighted least square solution to boost binary weak classifiers is proposed here for performance and speed improvements over the conventional and prominent GMM based classifiers. [ABSTRACT FROM PUBLISHER]

It can be observed that a rootkit may be used to conceal the digital rights management (DRM) software, which is aptly installed in consumers' computers to prevent unauthorized copying. In order to prevent unauthorized users from deleting the digital right management software by employing anti-rootkit tools to remove the rootkit, we develop a new driver-hidden rootkit to strengthen digital right management in this paper. The proposed driver-hidden rootkit is constructed using the technique of DKOM (Direct Kernel Object Manipulation), and have verified that it can successfully avoid a variety of well-known rootkit detectors. Our contributions are twofold. First, we can use the proposed new rootkit technology to extend the protection of the DRM software. Second, the stealth tricks of the proposed sophisticated driver-hidden rootkit can be a great inspiration to defenders who need to effectively strengthen the legitimate uses. [ABSTRACT FROM PUBLISHER]

In a recent paper [1] in this journal, an enhanced novel access control protocol (ENACP) over wireless sensor networks was given for the problem of preventing malicious nodes from joining the sensor network based on elliptic curve cryptography (ECC) and hash chain. We show that the presented ENACP has a fatal weakness such that it is insecure to the active attack. [ABSTRACT FROM PUBLISHER]

In this paper, we present a new framework for sensory games using motion estimation and collision responses. In this framework, only one Web camera is used, and the additional marker is not necessary. User's actions are extracted by analyzing consecutive frame differences. Collisions between the virtual objects and the user are detected by colliding ratio and distance, and the objects respond by the estimation of the collision response in which the collision plane is constructed by analyzing collision regions. Collision of the objects with other objects or boundaries (planes) responds by using the classical methods. Using the proposed framework, we implemented three games: two educational games and one sports game. These games are processed fast enough for real-time implementation, and can be played excitingly with simple environments. In addition, various applications may be easily developed using our framework. [ABSTRACT FROM PUBLISHER]

HomePlug AV is a recent version of the popular HomePlug powerline networking standard. An inhome HomePlug AV network was sampled between 1 and 6 Megabits per second (Mbps) with and without added noise and analyzed with respect to packet losses. Our experimental results indicate that the distribution of the number of consecutive error bursts is a combination of the classic Gilbert-Elliot model and a long-tailed distribution caused by ambient electrical noise. [ABSTRACT FROM AUTHOR]

The Universal Serial Bus (USB) has become the most popular interface standard for hardware connection, and there has been an explosion in the number of USB peripheral devices. External USB storage devices, in particular, are finding widespread application. Unfortunately, because USB affords high transmission speeds and is extremely convenient, many workplaces and businesses have prohibited the use of USB devices to prevent confidential data from being extracted from computer systems via USB ports. However, this compromises the convenience of the USB connection and demonstrates a lack of flexibility in management. Therefore, finding a way to take the considerations of both convenience and management into account has become a significant issue. This study proposes a secure control protocol which provides mutual authentication and key agreement between client and server to solve this problem1. [ABSTRACT FROM AUTHOR]

Since personal computers (PCs) radiate radio noise in a wide frequency range, wireless devices added to PCs may be subjected to interference from PC noise. Investigations were carried out on what impact clock harmonics radiating from a PC had on the bit error rate (BER) of multiband OFDM (MB-OFDM) UWB devices. The results indicated that clock harmonics cause considerable BER degradation in UWB devices especially those operated in high-bitrate communication modes. It was also found that the frequency modulation of a PC clock signal, i.e., so-called spread spectrum clocking (SSC), had no effect on mitigating BER degradation, even though SSC techniques are commonly used in PCs for reducing the power spectral density of radiated noise. Discussions were further made on a possible scheme of mitigating interference by using Viterbi decoding with channel state information (CSI) that is obtained by estimating the instantaneous frequency of clock signal directly provided by the PC to the UWB device. [ABSTRACT FROM AUTHOR]

Recent advances in wireless communication have raised possibility of creating new sets of richer multimedia applications in wireless networks; on the other hand, despite the rapid evolution and growing popularity of mobile handheld devices such as PDAs and smart phones, they are still significantly computationally constrained by limited resources for some kind of applications (e.g. computer graphics). The main contribution of this work is the design of a closed-loop controller in the context of image/video streaming systems with interactivity constraints to automatically adapt streaming parameters to bandwidth fluctuations. The proposed technique is general and acts as a sort of Quality of Service (QoS) mechanism at the application level and can be applied to any kind of client, but in this context we point out at common handheld devices, such as PDAs and smart phones, as a target. Experiments were carried out using different encoding standards (M-JPEG and MPEG-4 Part 2) and different network access (802.11g and HSDPA). [ABSTRACT FROM AUTHOR]

A system for converting broadcast soccer video into 3D cartoon animation is proposed. The system can provide viewers with a new experience that can not be acquired from the original soccer video, by taking advantage of computer vision and computer graphics techniques. Firstly, computer vision techniques are employed to estimate the 3D positions of players and the ball. Then, players, the ball and the playfield are modeled by computer graphics techniques. Finally, 3D cartoon animation is generated based on the extracted 3D information and the pre-constructed player motion database. The system allows users to watch the game at arbitrary viewpoint using a virtual camera. On the other hand, content service providers can distribute the generated cartoon animation on their web portals or to mobile devices, for consumers to better enjoy the game. [ABSTRACT FROM AUTHOR]

This study utilizes thread-level parallel techniques to significantly reduce the dynamic instruction count performance metric of the MPEG-2, MPEG-4 and H.264 video encoders. Such solutions are particularly applicable in portable devices as workload distribution among a number of parallel-executing processors decreases the individual processing requirements and allows for the real time video encoding. Due to the use of multiple processing engines in a consumer SoC the required clock frequency for real-time encoding, and hence power consumption, is likely to be considerably less than that of a single high-speed processor solution. The results presented demonstrate that reductions in dynamic instruction count in the range of 84% to 96% can be achieved for each of the encoders investigated. [ABSTRACT FROM AUTHOR]

We present a concept for information equipment called information-accessing furniture. We have developed an embedded module to be assembled into tables, mirrors, and walls. It can be easily assembled into furniture or other interior components because it is a package of information processing units, input/output units, and other optional units. This concept enables building information equipment designed to match a surrounding environment, and offers an intuitive interface to users, thus helping them to obtain information easily while doing routine activities. We developed several different prototypes with embedded modules and studied their applications. Some comments we received during interviews with end-users and interior designers are also presented. [ABSTRACT FROM AUTHOR]

With the integration of computer technology, consumer products, and communication facilities, the software in an embedded system now accounts for as much as 70% of total system functionalities. In this work, we propose a complete methodology called ESSP (Embedded Software Synthesis and Prototyping) for the automatic design of embedded software. Several issues are solved, including software synthesis, software verification, code generation, and system emulation. To avoid design errors, a formal approach is adopted because glitches in embedded software are intolerable and very expensive or even impossible to fix. Complex-choice Petri nets are used to model embedded software, which are then synthesized using an extended quasi static scheduling algorithm. The final generated C code is prototyped on an emulation platform, which consists of an 89C51 microcontroller for executing the software, an FPGA chip for programming the hardware for different applications, and some input/output devices. Two application examples are used to illustrate the feasibility of the ESSP methodology. [ABSTRACT FROM AUTHOR]

An optimal frame memory and data transfer scheme is proposed for MPEG-4 shape coding in embedded systems. The proposed alpha frame buffer scheme contains two approaches. First, a distributed tile-based memory organization is used to efficiently support the time-varying size of alpha plane. Second, a compression scheme is used to reduce the number of memory access to and the size of the alpha frame memory. Under the criteria of MPEG-4 standard, the size of alpha frame memory can be reduced to 50% by introducing a small index table (2.73%-S. 08% of the original frame memory size). A coarse assessment shows that the number of memory reference can be reduced to 56.25%. On the other hand, the proposed data transfer scheme combines the run length coding and addressing mode to reduce average data transfer time to 9.39%. Therefore, the shared system bus can be kept as free as possible, which in turn leads to increasing the potentialities of improvement on system performance. Furthermore, this data transfer scheme also helps in accelerating the processing of shape coding. [ABSTRACT FROM AUTHOR]

Though biometrics to authenticate a person is a convenient tool, typical authentication algorithms by using biometrics may not be executable on the memory-constrained devices such as smart cards. We present a solution of a face authentication algorithm for the open issue. Our achievement is two-fold. One is to present a face authentication algorithm with low memory requirement, which uses support vector machines (SVM) with the feature set extracted by genetic algorithms (GA). The other contribution is to suggest a method to reduce further, if needed, the amount of memory required in the authentication at the expense of verification rate by changing a controllable system parameter for a feature set size. Given a pre-defined amount of memory, this capability is quite effective to mount our algorithm on memory-constrained devices. Our experimental results show that the proposed method provides good performance in terms of accuracy and memory requirement. [ABSTRACT FROM AUTHOR]

Focuses on performance improvement techniques for complementary code keying (CCK)-orthogonal frequency division multiplexing (OFDM) wireless local area network modem. Equivalence between CCK codeword and coset of the first order Reed-Muller (RM) code with variables of three; Details on RM code as a complementary sequence; Peak-to-average power ratio reduction of OFDM.

Focuses on the development of a secure remote access system using a secure flash card for mobile workforce. Purpose of a tamper resistant module in the flash card solution; Description of the design and structure of the secured access system; Security functions handled by the flash card.

Proposes a seamless coordinator switching scheme for wireless personal area network. Overview of medium access control protocol for wireless personal area network; Simulation results for the proposed scheme.

Presents a study which measured the radiation levels emitted by standard personal computer monitors and television receivers, operating either alone or in computer rooms with large number of monitors. Experimental measurements; Results and discussion; Statistical analysis of measurements; Conclusions.

Contrast enhancement is important and useful for consumer electronics. One widely accepted contrast enhancement method is global histogram equalization (GHE), which achieves comparatively better performance on almost all types of image but sometimes causes excessive visual deterioration. We propose a new extension of bi-histogram equalization called Bi-Histogram Equalization with Neighborhood Metric (BHENM). BHENM consists of two stages. First, large histogram bins that cause washout artifacts are divided into sub-bins using neighborhood metrics; the same intensities of the original image are arranged by neighboring information. In the second stage, the histogram of the original image is separated into two subhistograms based on the mean of the histogram of the original image; the sub-histograms are equalized independently using refined histogram equalization, which produces flatter histograms. In an experimental trial, BHENM simultaneously preserved the brightness and enhanced the local contrast of the original image1. [ABSTRACT FROM AUTHOR]