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The p-n junction is the fundamental building block for electronics and photonics applications. In a conventional p-n junction, the performance parameters cannot be tuned due to the fixed doping level after ion implantation. In this paper, reconfigurable p-n or n-p junctions were built based on the ambipolar black phosphorus (BP) and other 2-D materials, namely, graphene and hexagonal boron nitride (h-BN). High-quality graphene/h-BN/BP/h-BN sandwich device was created by the dry transfer method in an inert environment. Graphene serves as the local back gate, which can tune BP partially into either n-type or p-type material. The rest of the BP channel can be controlled by the back gate. The BP encapsulated device can enable the high performance of the ideality factor down to 1.08 (p-n junction) and 1.18 (n-p junction). The device developed in this paper has a more balanced ideality factor than previously reported reconfigurable WSe2 and BP devices. By tuning the back gate and graphene gate, the BP device can be tuned into four operational quadrants, namely, n-n, n-p, p-n, and p-p junctions. Moreover, the hole mobility of BP is up to 404 cm2/ $\text {V}\cdot \text {s}$ at room temperature. Our work shows that the BP heterostructure is very promising for high-speed reconfigurable logic functions and circuits. [ABSTRACT FROM AUTHOR]

In this paper, the impact of charge transfer doping on the variability of multiwalled carbon nanotube (MWCNT) local interconnects is studied by experiments and simulations. We calculate the number of conducting channels of both metallic and semiconducting carbon nanotubes as a function of Fermi level shift due to doping based on the calculation of transmission coefficients. By using the MWCNT compact model proposed in Part I of this paper, we study the charge transfer doping of MWCNTs employing Fermi level shift to reduce the performance variability due to changes in diameter, chirality, defects, and contact resistance. Simulation results show that charge transfer doping can significantly improve MWCNT interconnect performance and variability by increasing the number of conducting channels of shells and degenerating semiconducting shells to metallic shells. As a case study on an MWCNT of 11 nm outer diameter, when the Fermi level shifts to 0.1 eV, up to ~80% of performance and standard deviation improvements are observed. Furthermore, a good match between experimental data and simulation results is observed, demonstrating the effectiveness of doping, the validity of the MWCNT compact model and proposed simulation methodology. [ABSTRACT FROM AUTHOR]

The effect of back-bombardment (BB) electrons is considered one of the main obstacles for extensive use of thermionic RF guns (T-RF). The 10 hexaboride materials named (Ca, Sr, Ba, La, Ce, Pr, Nd, Sm, Eu, and Gd) B6 are investigated in this paper to survey the effect of the cathode material on reducing BB electrons and compare them with LaB6 (which is widely used as a thermionic cathode). A numerical model was used to conduct this paper. Besides the numerical calculations, an experiment has been performed to determine the work functions of CeB6 and LaB6. The results from the numerical calculations revealed that (Ba, Ca, and Nd) B6 are less affected by BB electrons: 42%, 50%, and 59%, respectively, compared with LaB6, for low beam current applications. In contrast, for high beam current duties, (Nd, Ce, and Sm) B6 have minimum influence by BB electrons compared with other hexaborides. The study concluded that BB electrons are strongly affected by the properties of the cathode material, especially thermionic emission and material density. Moreover, the study suggests that it is worthwhile to prepare BaB6, CaB6, NdB6, and SmB6 as cathode materials, then to subject them to a real experimental test using T-RF gun to compare their performance and BB effect against LaB6. [ABSTRACT FROM AUTHOR]

In this paper, for the first time, we demonstrate the improvement in power capability and safe operating area of silicon-on-insulator laterally double-diffused MOS (SOI-LDMOS) transistors for power amplifier applications by the introduction of a partial n+ buried layer (PNBL). The power capability of a transistor can be evaluated by ${P}_{\text {max}}/A$ , which is the maximum power per unit area that can be delivered by the transistor and is an important parameter for power amplifiers. ${P}_{\text {max}}$ is dependent on the snapback voltage (${V}_{\text {sb,QS}}$), OFF-state breakdown voltage (${V}_{\text {bd}, \mathrm{\scriptscriptstyle OFF}}$), and maximum current (${I}_{\text {max}}$) in the quasi-saturation regime of an LDMOS transistor. Increase of ${P}_{\text {max}}/A$ by the introduction of a PNBL in the SOI-LDMOS transistors is reported in this paper. The effects of variation of the length, thickness, and doping concentration of the PNBL on ${V}_{\text {sb,QS}}$ and ${P}_{\text {max}}/A$ are analyzed in detail. It is shown that by optimizing the doping and length of the PNBL layer, the maximum power output from the transistor can be made significantly higher than that of a conventional device without PNBL. A procedure to design the optimized structure is also presented. [ABSTRACT FROM AUTHOR]

This paper analyzes the performance of mosaic nonimaging passive infrared (PIR) sensors fabricated by the CMOS–SOI–MEMS technology. The elementary sensor, forming a subpixel, is a thermally isolated nanomachined CMOS transistor, dubbed TMOS, operating at subthreshold. The mosaic uncooled PIR sensors are composed of several TMOS subpixels, which are electrically connected, either in parallel or in series as well as a combination of both options. These mosaic sensors, which are manufactured by nanofabrication methods, exhibit enhanced performance and robust manufacturing on wafer level. The overall figures of merit of these sensors, which are modeled in this paper, indicate why they are most suitable for consumer electronics, including smart homes, wearables, Internet of Things as well as mobile applications. [ABSTRACT FROM AUTHOR]

Esaki diodes based on interband tunneling have the characteristics of negative differential resistance (NDR) and ultrafast transient time, which lead to broad applications including oscillators, multivalue memories, and terahertz detectors. In this paper, we present the first demonstration of Esaki diodes based on 2-D/3-D heterojunctions—more specifically, chemical vapor deposition MoS2 on degenerately doped silicon. As compared to traditional 3-D heterostructures, these 2-D/3-D heterostructures have the following advantages: dislocation-free 2-D crystals even when the lattices are mismatched, dangling bond-free surface, and capability for large-scale synthesis at low cost. In this paper, monolayer, bilayer, and trilayer MoS2 are synthesized directly on degenerated Si substrate, forming the ultraclean heterostructures without surface contamination from tape and resist. Based on these pristine heterostructures, we are able to observe prominent NDR effect at room temperature. This NDR effect is attributed to the degenerately p-type doping in silicon and the natural n-type doping in MoS2. We also found that the peak voltage corresponding to the local maximum tunneling current depends on the MoS2 thickness. While MoS2 is changing from the monolayer (0.7 nm) to bulk (9.5 nm), the peak voltage increases from 0.8 to 1.6 V. This phenomenon can be explained by the energy-level differences between the monolayer and bulk MoS2. This paper provides the experimental groundwork for the synthesis of transition metal dichalcogenides on degenerately doped Si substrates and opens up new and exciting opportunities for electronic applications of 2-D/3-D heterostructures. [ABSTRACT FROM AUTHOR]

In-memory computing architecture is an emerging revolutionary computing paradigm that can break the von Neumann bottleneck. Computing methodology and circuit codesign using the CMOS compatible 1T1R resistive random access memory (RRAM) integration structure is presented in this paper. Functionally complete Boolean logic and arithmetic functions are experimentally demonstrated. With a single 40-nm CMOS process 1T1R unit, each of the 16 binary logics can be realized in two logic steps with an additional readout step for cascading, which shows functional reconfiguration and low computational complexity. Up to 107 cycles of NAND and XOR logic operations are performed to validate the correctness and reliability. Moreover, several fundamental adder circuits are designed and experimentally demonstrated in 1T1R devices as the proof of concept of the 1T1R computing architecture. The adders proposed in this paper include a ripple-carry adder and its optimized design and a carry-select adder, which all show promising advantages in nonvolatility, computation speed, and circuit area. This paper reports the most complex yet efficient RRAM-based 8-bit addition function experimentally so far and lays a solid foundation for constructing the future in-memory computing architecture. [ABSTRACT FROM AUTHOR]

In this paper, we report on the assessment of self-amplified silicon–oxide–nitride–oxide–silicon (SONOS) memory device architecture for sub-50-nm gate length (${L}_{g}$) through calibrated simulations. Self-amplification (SA) effect in tunnel field-effect transistor-based SONOS (T-SONOS) memory device has been analyzed. Results show that memory window ($\Delta {W}$) in T-SONOS cell increases as buried oxide thickness increases due to capacitive coupling between the front and back gates. Although the enhanced $\Delta {W}$ can also be achieved in inversion-mode SONOS (I-SONOS) device, its performance is deteriorated when the gate length is scaled down. We have compared the performance of I-SONOS and T-SONOS memory devices for ${L}_{g}$ varying from 100 to 25 nm. Results highlight that I-SONOS device cannot be programmed at ${L}_{g} ={25}$ nm and thus deteriorate the memory operation. However, SA T-SONOS at ${L}_{g} = {25}$ nm achieves ${W} \sim {6}$ V. In addition, the effect of underlap on the performance of T-SONOS cell has been analyzed, and it is shown that memory operation of 25-nm T-SONOS device can further improved with a drain side underlap of 20 nm. This paper provides new opportunities to design SA T-SONOS memory device for the next-generation nonvolatile memories. [ABSTRACT FROM AUTHOR]

The introduction of metal nanocrystals (NCs) has been confirmed to improve electrical uniformity of oxide-based resistive random access memory (RRAM) devices significantly; however, the current reports do not systematically elucidate the relationship between the size/distribution of NCs and the electrical uniformity of RRAM devices. In this paper, we focused on the impact of metal NCs size and areal density on the resistive switching (RS) performances of oxide RRAM by atomic layer deposition (ALD) based on the experimental results and theoretical calculation. The dependence of ALD cycles of 50–130 during Pt or CoPtx NCs growth on the RS parameters of Al2O3 or HfO2 memory units has been evaluated systematically. The RRAM embedded Pt or CoPtx NCs shows the trends: with increasing ALD cycles, the forming voltage, set/reset voltage, the resistance in off and on state, and ${R}_{ \mathrm{\scriptscriptstyle OFF}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$ ratio entirely first decrease, then flatten, and increase later with a minimum value at about 100 cycles. Although all metal NCs with various sizes enhance the electric field strength compared to at the planar region, only metal NCs with proper NCs size and areal density (9 nm/6– $10\times 10^{\textsf {11}}$ /cm2 in this paper) can effectively produce stronger localized electric field at the tip of metal NCs, leading to optimal RS behavior. [ABSTRACT FROM AUTHOR]

The application of capacitive deep trench isolation (CDTI) as a shared vertical transfer gate (VTG) in a back-side-illuminated CMOS image sensor pixel is investigated using 3-D device-level simulations. The parasitic capacitance existence between CDTI and deeply buried pinned photodiode (BPD), and also between CDTI and floating diffusion (FD) region, makes the charge transfer process more difficult. In order to design a lag-free pixel and obtain complete charge transfer from BPD to FD, various considerations regarding the device-level design should be taken into account which is discussed in this paper. A CDTI neighboring two pixels can be functionalized as a shared VTG. Using CDTI as shared VTG facilitates pixel miniaturization and can result in more circuit integration at the pixel surface. This paper proposes a ${2}\,\,\mu \text{m} \times {2}\,\,\mu \text{m}$ pixel with CDTI as shared VTG, an equilibrium full-well capacity of 4605 e−, and a complete charge transfer from BPD to FD. [ABSTRACT FROM AUTHOR]

It is well known that there is a critical Sn content for a GeSn alloy, at which the conduction band edges at ${L}$ and $\Gamma$ symmetry points are aligned in energy. For GeSn tunnel FET (TFET) simulations, with a given donor concentration, this paper reveals that simulations neglecting the multivalley and nonparabolic band structure would incorrectly predict the subthreshold slope (SS) and the off-currents. We highlight the indispensability of the consideration of the multivalley band structure of GeSn for TFET simulations. This paper provides the required parameters, which may be useful for numerical simulations of other optoelectronic and electronic GeSn devices. [ABSTRACT FROM AUTHOR]

This paper demonstrates a novel nanofabrication technology for producing high-density gated molybdenum (Mo) field-emitter array (FEA) based on modified nanosphere lithography (NSL). The arc-shaped side wall of gate apertures introduced by the conventional NSL process put obstacles in the formation of sharp cone-type emitters. In this paper, a two-method solution was employed to facilitate the realization of gate apertures with sharper cutting side wall which are beneficial for the formation of sharper gated Mo emitters. One method was softening nanosphere to enlarge the contact area between nanosphere and substrate. The other was optimizing gate film deposition conditions to dramatically reduce the diffraction effects. Due to the improvements in the geometrical shape of gated Mo emitters, a low-voltage working high-density gated Mo FEA was demonstrated in this paper. This is the first observation of remarkable electron emission from high-density gated Mo FEA fabricated using such as low-cost, high-throughput, and high-efficiency technique which is expected to substantially overcome the challenges in the traditional fabrication process and promotes the low-cost and large-area application of high-density gated field-emitter devices. In addition, the novel nanofabricating method is expected to offer a simple and scalable route which allows fabrication of many gated field-emission devices. [ABSTRACT FROM AUTHOR]

Stacks of 2-D materials, known as van der Waals (vdW) heterostructures, have gained vast attention due to their interesting electrical and optoelectronic properties. This paper presents an intuitive circuit model for the out-of-plane electrostatics of a vdW heterostructure composed of an arbitrary number of layers of 2-D semiconductors, graphene, or metal. We explain the mapping between the out-of-plane energy band diagram and the elements of the equivalent circuit. Although the direct solution of the circuit model for an n-layer structure is not possible due to the variable, nonlinear quantum capacitance of each layer, this paper uses the intuition gained from the energy band picture to provide an efficient solution in terms of a single variable. Our method employs Fermi–Dirac statistics while properly modeling the finite density of states (DOS) of 2-D semiconductors and graphene. The approach circumvents difficulties that arise in commercial TCAD tools, such as the proper handling of the 2-D DOS and the simulation boundary conditions when the structure terminates with a nonmetallic material. Based on this methodology, we have developed 2dmatstacks, an open-source tool freely available on nanohub.org. Overall, this paper equips researchers to analyze, understand, and predict experimental results in complicated vdW stacks. [ABSTRACT FROM AUTHOR]

In this paper, the pinning process of pinned photodiodes (PPDs) is described by a new analytical model, assuming the PPD to be composed of inner and junction regions. There are two definitions of the pinning potential: maximum conduction band potential variation ($\Delta \varphi _{M}$) and maximum electron quasi-fermi level potential variation ($\Delta $ FP $_{M}$). The output of the previous pinning potential models is only an approximation of $\Delta \varphi _{M}$. In this paper, a comprehensive model is proposed in which both aforementioned definitions of pinning potential can be achieved analytically. The proposed model is a system of equations relating PPD’s main characteristics such as $\Delta \varphi _{M}$ and equilibrium full-well capacity to other main PPD parameters such as PPD spatial dimensions, impurity dopant concentrations, maximum inner region potential, and remnant carrier population at $\Delta \varphi _{M}$. The proposed model is verified by two previously reported experiment-based data. [ABSTRACT FROM AUTHOR]

In 2-D van der Waals heterostructures, interactions between atomic layers dramatically change the vibrational properties of the hybrid system and demonstrate several interesting phenomena that are absent in individual materials. In this paper, we have investigated the vibrational properties of the heterostructure between transition metal dichalcogenide (TMD) and hexagonal boron nitride (hBN) on gold film at low- and high-frequency ranges by Raman spectroscopy. Nineteen Raman modes have been observed from the sample, including a new interlayer coupling mode at 28.8 cm−1. Compared to reported experimental results of tungsten disulfide (WS2) on SiO2/Si substrates, the Raman spectrum for WS2 on hBN/Au emerges a blue shift of about 8 cm−1. Furthermore, a remarkable enhancement of Raman intensity can be obtained when tuning hBN thickness in the heterostructure. Through systematic first-principles calculations, numerical simulations, and analytical calculations, we find that the 28.8 cm−1 mode originates from the shearing motion between monolayer TMD and hBN layers. In addition, the gold substrate and hBN layers form an optical cavity and the cavity interference effects enhance the obtained Raman intensity. This paper demonstrates the novel vibrational modes of 2-D van der Waals heterostructure as an effective tool to characterize a variety of such heterostructures and reveals a new method to enhance the Raman response of 2-D materials. [ABSTRACT FROM AUTHOR]

This paper demonstrates a high-performance black phosphorus nanoribbons field-effect transistor (BPNR-FET) and systematically investigates methods for enhancing its anisotropic carrier transport. The BPNR-FET shows a strong dependence on crystal orientation in which the best mobility performance is achieved in armchair-oriented nanoribbons. A downscaling of nanoribbon width is shown to improve the short-channel effect owing to a better electrostatic gate control. Furthermore, hydrogenation is employed to effectively passivate the dangling bonds and heal the nanoribbon edge defects, leading to nearly hysteresis-free transfer properties. By virtue of bandgap and contact-metal workfunction engineering, n-type BPNR-FET is successfully demonstrated, which enables complementary inverter circuits to be simultaneously realized. This paper unravels the superior performance underscores a conceptually new BPNR-FET, paving the way toward the development of non-planar devices and integrated circuits based on 2-D materials platform. [ABSTRACT FROM AUTHOR]

Part II of this paper discusses the transient characteristics of the electrically driven insulator–metal transition (E-IMT) material-based device. To model the full transient characteristics, we modify the electrothermal model developed in Part I to capture extrinsic capacitance and 2-D heat transport effects. In order to test the model against the experiment, we fabricated and tested scaled E-IMT devices with a necked-down design to minimize nonhomogeneity. We show excellent agreement of the predictions of the model with the experimental data, and we find that the IMT device goes through three stages before a steady state is established. These three stages are identified as the times required for the incubation of the IMT transition, positive feedback, and width expansion of the IMT zone within the device. The impact of capacitance and 2-D heat transport is discussed. Furthermore, we show an inverse relation arises between the incubation time and the applied voltage. This paper satisfactorily explains the turn-on transient in a nanoscale E-IMT device within the framework of our electrothermal (Joule heating) model. [ABSTRACT FROM AUTHOR]

Many methods have been proposed for the experimental determination of the collector resistance in bipolar junction transistors and HBTs. In this paper, the most widely used methods are reviewed and applied to SiGe HBTs with a large variety of device sizes fabricated in different technologies and generations, including high-speed and high-voltage transistors. First, the accuracy of those methods, which are based on an extraction from single-transistor characteristics, is evaluated from simulated data using a sophisticated compact model and, where applicable, also device simulation. This approach allows the origin of observed inaccuracies or failures of certain methods to be identified. Second, the test structure-based methods are reviewed, and third, all methods were applied to experimental data. This paper and its results provide insight into each method’s accuracy; its application limits with respect to a technology, a device size, and an operating range as well as its requirements in terms of equipment and extraction effort. [ABSTRACT FROM AUTHOR]

This paper presents a new method for modeling the nonideal conductance response (CR) of synaptic devices. Unlike previous studies, which utilize physical device properties for modeling, this paper only uses the measured CR data. This allows the proposed modeling method to be easily applied to various types of synaptic devices without considering the unique physical properties of each device. An efficient piecewise linear approximation method which offers a tradeoff between computational complexity and simulation accuracy of neural networks is also presented to generate a linear device model out of nonlinear CR data. In addition, model parameters, which reflect the nonideal characteristics of the CR such as abrupt and asymmetric conductance changes, conductance variation, and limited conductance dynamic range, are introduced to evaluate the network performances in the presence of the nonidealities. By adjusting the model parameters, the desired CR satisfying the network performance requirements can be derived for device development. A three-layer neural network employing the device model has been designed and trained for the MNIST data set in order to demonstrate the application of the model to system-level simulations and verify the effectiveness of the modeling method. [ABSTRACT FROM AUTHOR]

This paper proposes a semianalytical model to estimate short-channel effects for independent gate operation in double-gate (DG) junctionless (JL) MOSFET incorporating gate-to-source/drain underlap, through the solution of Poisson’s equations in the subthreshold regime. The model also accounts for the asymmetry in device operation through variation in gate oxide thicknesses, gate work functions, and underlap lengths. Subthreshold drain current, threshold voltage, and subthreshold swing, evaluated from the channel potential, show reasonable agreement with simulation data. Results suggest the use of negative back gate bias and longer underlap length to reduce off-current. This paper highlights the role of doping, underlap length, and back gate bias in tuning the threshold voltage. This model serves as a generic formulation (within limits) with different asymmetries to estimate, design, and optimize self-aligned DG JL transistors for subthreshold logic applications. [ABSTRACT FROM AUTHOR]

In this paper, we report a hierarchical simulation study of the electromigration (EM) problem in Cu-carbon nanotube (CNT) composite interconnects. This paper is based on the investigation of the activation energy and self-heating temperature using a multiscale electrothermal simulation framework. We first investigate the electrical and thermal properties of Cu-CNT composites, including contact resistances, using the density functional theory and reactive force field approaches, respectively. The corresponding results are employed in macroscopic electrothermal simulations taking into account the self-heating phenomenon. Our simulations show that although Cu atoms have similar activation energies in both bulk Cu and Cu-CNT composites, Cu-CNT composite interconnects are more resistant to EM thanks to the large Lorenz number of the CNTs. Moreover, we found that a large and homogenous conductivity along the transport direction in interconnects is one of the most important design rules to minimize the EM. [ABSTRACT FROM AUTHOR]

4H-silicon carbide (SiC) is a suitable candidate for high-temperature and radiation prone applications, due to its superior electrical and material properties. Several researchers have demonstrated small-scale logic circuits, entirely in 4H-SiC; however, to build a complete electronic module in 4H-SiC, a memory component is yet to be developed. This paper presents for the first time the design, optimization, and performance analysis of a 4H-SiC-based bipolar memory column including a static random access memory cell and peripherals, designed for voltages as low as 5 V. The memory column has average noise margins of 2 V and delays in the range of few nanoseconds at room temperature. The proposed memory architecture also demonstrates robust operation across a wide range of temperatures (27 °C–500 °C) with stable noise margins and speeds. This paper validates the potential of developing memory architectures in 4H-SiC, which operates reliably for varying conditions, paving the way to build complete electronic systems entirely based on 4H-SiC. [ABSTRACT FROM AUTHOR]

Performance limitations of superjunction (SJ) devices due to charge imbalance (CI) are analyzed in this paper. It is demonstrated that in the presence of CI, the specific on-resistance has a quadratic dependence on blocking voltage, similar to a conventional drift region. We also show that by designing the SJ structure with an optimally modified pillar doping, we can achieve better performance under conditions of CI. The design guidelines presented in this paper are applicable to any semiconductor, although all calculations are based on silicon carbide. [ABSTRACT FROM AUTHOR]

In this paper, a n-type junctionless FET (JLFET) with a p-type fin body (FB) is investigated using a 3-D numerical simulator. We show that the proposed device (FB-JLFET) with a p+ FB can control the electrostatic potential of the channel more efficiently for multi- ${V} _{\text{TH}}$ (threshold voltage) and dynamic threshold (DT) operation. Moreover, body bias application is implemented in FB-JLFET and a large body factor ($\gamma $) is predicted for wide range ${V} _{\text{TH}}$ modulation. Thanks to the stronger potential coupling between the channel and FB, the proposed device exhibits $\gamma $ improvement compared to the conventional JL bulk FinFETs under the same electrostatic control. In addition, DT operation is studied in the form of a JLFET for the first time and it exhibits 37% improvement of the on-state drive current and better subthreshold swing (S.S.) compared to FB-JLFET without DT. This paper provides the feasibility of multi- ${V} _{\text{TH}}$ operation with body bias mode for high performance or low-power applications and DT operation for high-speed circuits with low power consumption. [ABSTRACT FROM AUTHOR]

Most thin-film transistor (TFT) gate drivers integrated on the display panel use the carry signals between the stages. In our previous works, we found that these carry-type gate drivers are subject to the reliability problem in a flexible display, since the errors of the stressed stages are accumulated through the carry signals. This problem possibly leads to the failure of image refresh of the display device. Therefore, the carry-free gate driver can resolve the error accumulation problem since it does not use the carry signals and instead, each unit stage operates independently. In this paper, we propose an advanced carry-free gate driver circuit to remove the drawbacks of the previous version, while keeping the advantages. More importantly, this paper is the first report to experimentally show that the error accumulation phenomenon of the carry-type gate driver and the problem is removed in the carry-free gate driver. The proposed carry-free gate driver and the carry-type gate driver are fabricated with amorphous indium-gallium-zinc-oxide TFTs on a flexible substrate for comparison purpose. The proposed gate driver shows a very high reliability since no voltage fluctuation occurs at the outputs after 10 000 cycles bending test with 2-mm bending radius. [ABSTRACT FROM AUTHOR]

In this paper of thermoelectric generators, metals are used as the prospective thermoelectric materials or thermoelements on flexible copper (Cu)-clad polyimide substrate. The fabricated thick film generators have planar and lateral structures with lateral heat flow and lateral thermopile layout. Hereby, two prototypes of thermoelectric generators are made, the first employing Cu and nickel (Ni) and the second Cu and cobalt (Co) as their positive and negative thermoelements, respectively. This paper also investigates the roles of geometrical structures such as the thermoleg’s length and width and the generator’s size in promoting elevated thermoelectric power generation. Consequently, the highest performing thermoleg designs (length: 5–20 mm; width: 100– $1000~\mu \text{m}$) for the two prototypes are identified as having a length, width, and thickness of 5 mm, $1000~\mu \text{m}$ , and $31~\mu \text{m}$ , respectively, with generator dimensions of 1.1 cm length and 4.3 cm width. Collectively, this design has an accumulated average temperature difference, output power density, and thermoelectric efficiency factor of 60 K, $0.59~\mu $ Wcm−2, and $1.64\times 10^{-\textsf {4}}\,\,\mu $ Wcm−2K−2, respectively, for the Cu–Ni generator, while the corresponding values for the Cu–Co generator are 64 K, $1.15~\mu $ Wcm−2, and $2.81\times 10^{-\textsf {4}}\,\,\mu $ Wcm−2K−2. An improvement factor of 1.71 is realized by the Cu–Co generator compared to the Cu–Ni one due to its larger Seebeck coefficient and figure of merit. This highlights the Cu–Co metallic couple as an encouraging thermoelement in thermoelectricity. Promisingly, the thick film and lateral device structures are more compatible and favorable for metal-based thermoelectric generators. [ABSTRACT FROM AUTHOR]

This paper investigates the temperature dependence of random telegraph noise (RTN) in 3-D NAND Flash technologies. Experimental results on memory arrays reveal an increase of RTN when temperature is reduced, which is mainly attributed to the growth of the amplitude of the fluctuations arising from RTN traps. A direct proof of this growth is provided by directly monitoring some RTN waveforms arising from single traps in cells out of either memory arrays or test elements. In order to explain this evidence, the TCAD model for polysilicon NAND strings presented in Part I of this paper is adopted and extended to address the amplitude of the threshold-voltage shift coming from the trapping of a single electron at different positions in cell channel. Numerical results successfully reproduce the experimental trends with temperature and allow to explain them in terms of stronger nonuniformities in polysilicon inversion when temperature decreases. In particular, the reduction of temperature makes the string currentmore controlledby the polysilicon grain boundaries, increasing, in turn, the amplitude of the RTN fluctuations arising from traps placed on or close to them. [ABSTRACT FROM AUTHOR]

This paper presents characterization and modeling results exploring the temperature dependence of the electrical characteristics of 3-D NAND Flash strings. Experimental data over a wide temperature range are used to calibrate a Technology Computer-Aided Design model for current transport through the polysilicon channel of the strings, which is then used to investigate the role of grain boundaries on string conduction. Results reveal that the variability in the grain configuration in the strings introduces a nonnegligible statistical spread in the temperature dependence of the threshold voltage (${V}_{T}$) of the memory cells, which acts as a broadening contribution to the array ${V}_{T}$ distribution when temperature is changed. The experimental and modeling activities will be extended in Part II of this paper to explore the temperature dependence of the ${V}_{T}$ instability caused by random telegraph noise. [ABSTRACT FROM AUTHOR]

The IEEE International Integrated Reliability Workshop (IIRW) focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems. Submit your two-page abstract by 12 July 2013 to be part of this unique event. For further information visit http://www.iirw.org or contact the TPC chair. [ABSTRACT FROM AUTHOR]

The SISC is a workshop-style conference that provides a forum for device engineers, solid state physicists, and materials scientists to discuss topics of common interest, formally through invited and contributed presentations, and informally during various events including a poster presentation session. The SISC is sponsored by the IEEE Electron Devices Society, and will be held immediately prior to the IEEE IEDM. The program includes talks (theory and experiment) from all areas of MOS science and technology. A Best Student Presentation Award will be given in memory of E.H. Nicollian. Deadline for Receipt of Extended Abstracts: July 22, 2013 Abstract submission, previous technical programs, contact information, etc.: http://www.ieeesisc.org. Key Bridge Marriott Hotel, Arlington, VA (near downtown Washington, DC) December 5-7,2013 (Tutorial: December 4). [ABSTRACT FROM AUTHOR]

This paper investigates the degradation of GaN-based HEMTs with p-type gate submitted to positive gate bias stress. Based on combined electrical and optical testing, we demonstrate the existence of different degradation processes, depending on the applied stress voltage ${V}_{\textsf {Gstress}}$ : 1) for ${V}_{\textsf {Gstress}}< \textsf {7}$ V, no significant degradation is observed, thus demonstrating a good stability of the analyzed technology; 2) for 7 V $< {V}_{\textsf {Gstress}} <\textsf {11.5}$ V, a negative shift in threshold voltage (${V}_{\textsf {th}}$) is observed, well correlated with a decrease in the gate leakage current and of the luminescence signal associated with hole injection. The negative ${V}_{\textsf {th}}$ shift is ascribed to the trapping of holes in the AlGaN and/or p-GaN/AlGaN interface; and 3) for ${V}_{\textsf {Gstress}} \ge \textsf {12}$ V, threshold voltage recovers its initial value. This is ascribed to a net-negative charge, generated either by the trapping of electrons injected from the 2-D electron gas to the AlGaN or to the de-trapping of the holes injected in 2). The results described within this paper provide relevant information for understanding the degradation dynamics of normally off GaN transistors submitted to extremely high gate voltage levels far beyond maximum use. [ABSTRACT FROM AUTHOR]

In this paper, we report on the influence of surface (donor and acceptor) states and interface charges on the formation of 2-D electron gas (2DEG) in MgZnO/ZnO heterostructure grown by sputtering. Donor and acceptor states alone cannot yield an order of magnitude higher value of 2DEG as observed by sputtering growth as compared to epitaxial techniques. While surface donor states are reported to govern the formation of 2DEG in epitaxially grown heterostructures, our simulations suggest a non-negligible contribution of surface acceptor states in the 2DEG density. In addition, the existence of interface charges due to high defect density along with appropriate values of donor and acceptor states is essential to accurately predict an order of magnitude higher 2DEG density grown by sputtering. This paper analyzes the distinct roles of donor and acceptor states along with interface charges in 2DEG formation and achieved values. [ABSTRACT FROM AUTHOR]

This paper presents an extensive investigation of the impact of the resistivity of the silicon substrate on the vertical leakage and charge trapping in 200 V GaN-on-Si enhancement-mode high-electron mobility transistors. Three wafers having different substrate resistivities were submitted to combined DC characterization, step-stress experiments, and electroluminescence (EL) analysis. The results described within this paper demonstrate that: 1) the use of a highly resistive silicon substrate can increase the vertical breakdown voltage of the transistors, due to the fact that the voltage drop on the GaN buffer is mitigated by the partial depletion of the substrate (this latter causes a plateau region in the drain to substrate I–V characteristic) and 2) highly resistive substrate results in stronger trapping effects, due to the capacitance of the depleted substrate and the resulting backgating effects. The results described within this paper indicate that the choice of the resistivity of the substrate is the result of a tradeoff between high breakdown voltage (that could be in principle achieved through a highly resistive substrate) and the minimization of trapping processes (which can be hardly obtained with a resistive substrate). [ABSTRACT FROM AUTHOR]

A systematic analytical investigation of the charge distribution and gate control of the normally-off GaN double-channel MOS-HEMT (DC-MOS-HEMT) is presented in this paper. Compared to conventional GaN MOS-HEMT, the DC-MOS-HEMT features a thin AlN insertion layer (AlN-ISL) below the original two dimensional electron gas (2DEG) channel, thus forming a second channel at the interface between AlN-ISL and the underlying GaN. This paper reveals the impact of the AlN-ISL on the 2DEG distribution and the gate control of the channels. The sensitivity of ${V}_{\text {th}}$ against the recess depth is also analytically studied and is found to be nearly independent of the recess depth as long as the recess is terminated in the upper channel layer. The analytical results are well supported by numerical device simulations, and the physical mechanisms behind these findings are explained along with the analytical investigations. [ABSTRACT FROM AUTHOR]

In this paper, we present a comprehensive study of multisection, velocity-tapered slow wave structures (SWSs) for highly efficient backward-wave oscillators (BWOs). The SWS velocity variation profiles are characterized by mathematical functions. Using particle-in-cell (PIC) simulations, the efficiencies of these SWSs are obtained along with their oscillation frequency response to variations in beam voltage. This paper is aimed at determining the optimum SWS profiles for high-efficiency BWO operation along with the corresponding tunability. The profile with the highest possible efficiency is fabricated and cold tested to experimentally determine and validate the underlying efficiency enhancement mechanisms. This resulting cold test experiment demonstrates higher order dispersion in the form of multiple secondary inflection points. PIC simulations using this SWS design predict an output power of 8.25 MW at 2.62 GHz corresponding to a peak power conversion efficiency of 70%. [ABSTRACT FROM AUTHOR]

Quantum dots (QDs) show a great potential for light-emitting diodes (LEDs) packaging, which still face great challenges compared with the matured phosphor downconversion materials. These are probably caused by the unique scattering and absorption properties of QDs, which are extremely different to the traditional phosphor due to their several nanometers size, while their effect on QDs-converted LEDs (QCLEDs) is barely studied. In this paper, we have experimentally and theoretically investigated the effect of scattering and absorption of CdSe/ZnS QDs on the optical performance for QCLEDs by comparing with the traditional yttrium aluminum garnet phosphor. Results indicate that the strong absorption (reabsorption) of QDs causes low radiant efficacy and stability for QCLEDs; their weak scattering also leads to a low color uniformity. It demonstrates that their unique scattering and absorption properties are key factors leading to low optical performance of QCLEDs compared with the traditional phosphor-converted LEDs. For purpose of gaining the white LED with high efficiency and stability, it is highly suggested to use a low QD concentration to reduce the reabsorption loss and the total internal reflection loss. We believe that this paper can provide a better understanding of improving the optical performance for QCLEDs from the prospective of scattering and absorption. In the future, it is important to use low QD concentration to gain high-performance white LEDs with high downconversion efficiency by optimizing packaging structures. [ABSTRACT FROM AUTHOR]

With technology node scaling down to 5 nm, the narrow device geometry confines the material thermal conductivity and further aggravates the self-heating effect in gate-all-around (GAA) transistors. In this paper, we investigate the self-heating of horizontally stacked three-layer GAA nanosheet transistors by 3-D finite-element modeling (FEM) simulation. The anisotropic thermal conductivity of nanosheets with the dependence of silicon thickness and temperature is implemented in the FEM simulator to evaluate thermal behavior accurately. The impact of layout design on thermal properties is investigated comprehensively from single device to device arrays with implication on electrical performance. The results indicate that the width of nanosheet is the key parameter to make the tradeoffs between self-heating and electrical characteristic. Meanwhile, the optimizations of layout design are given to suppress the thermal effects, including self-heating, nonuniformity of temperature, and thermal crosstalk at device level. This paper will provide guidelines for layout design, thermal management, device performance, and thermal-aware reliability prediction in the GAA-stacked structure. [ABSTRACT FROM AUTHOR]

In this paper, we explored the characteristic fluctuations induced by various random discrete dopants (RDDs) on gate-all-around silicon nanowire metal–oxide semiconductor field-effect transistors. A 3-D quantum-mechanically corrected transport model was employed to analyze the simulated devices. The statistical results indicate that the variation of threshold voltage ( ${V}_{\text {th}}$ ) not only can be reduced from 28.6% to 10.7% without channel doping and penetration from the source/drain into the channel, but also the variation of 3-dB frequency can be reduced from 8% to 2.7% due to the reduction of the variation of ${V}_{\text {th}}$. We reported that the high-frequency characteristic fluctuations (voltage gain and cutoff frequency) were dominated by electron mobility. This caused by RDDs from the drain extension exhibited less variability than that caused by RDDs from the source extension due to a reduced injection velocity near the S side and a negligible difference in the electron saturation velocity near the D side. This paper provides pertinent information on the design of high-frequency amplifier circuits in relation to devices with RDDs induced by variations in the semiconductor process. [ABSTRACT FROM AUTHOR]

The need for information transmission at ever increasing data rates is moving satellites to the millimeter-wave (MMW) bands. The efficient transmission of information requires linear systems. For satellites transmission linear, high-power amplifiers (HPAs) are essential in both orbit and on the ground. This paper describes linearizers that have been developed for the use with TWTAs at Q (43.5–45.5 GHz) and the new V (47–52 GHz) satellite bands. This paper will also discuss linearizer work for even higher bands that will be needed in the near future. Today’s TWTA linearizers can provide all the frontend functions needed by an HPA including upconversion, gain, commandable attenuation, commandable predistortion, and the RF power for direct drive. The use of linearization at MMW is discussed and measured characteristics of the linearizers such as power transfer and carrier to intermodulation (IM) ratio (C/I) shared. Linearized MMW TWTAs are shown to achieve an AM/PM of <2°/dB, and at 3-dB output power backoff with a 16QAM signal, an adjacent channel power ratio of >30 dB with an error vector magnitude of <2%. [ABSTRACT FROM AUTHOR]

Single-stage depressed collector systems are widely used in high-power gyrotrons in order to increase the overall efficiency. The position where the deceleration of the beam takes place influences the collector efficiency. In this paper, several deceleration schemes are numerically investigated for the short-pulse prototype of the 170-GHz, 1-MW European gyrotron for International Thermonuclear Experimental Reactor. The results of this paper are in a qualitative agreement with the results of dedicated experiments. A simple idea is also proposed for the significant increase of the overall gyrotron efficiency without an important technological modification. [ABSTRACT FROM AUTHOR]

A high-harmonic traveling-wave tube (HHTWT) is designed, developed, and tested in this paper. This device is configured as a multiplier–amplifier with Q-band input signals and its third harmonic, i.e., D-band output power. The tested result demonstrates that 280 mW at 133.5 GHz is obtained as a result of 200 mW at 44.5-GHz input signal. The simulation and experiment validate that the high-harmonic radiation can be generated and amplified in the HHTWT. The approach described in this paper could find application in exploring high power, wideband tunable terahertz source. This paper is expanded from a conference paper on IVEC 2017. The detail design produce and tested result are added in this paper. The explanation of the simulation and tested results is also presented. [ABSTRACT FROM AUTHOR]

String read current ( ${I}_{\textsf {read}}$ ) reduction with rising mold height and grain boundary traps is one of the major hurdle in the development of 3-D NAND flash memory. In this paper, we have investigated ${I}_{\textsf {read}}$ with variation in polysilicon channel grain size (GS), grain boundary trap density, and channel thickness ( ${T}_{\textsf {Si}}$ ), using TCAD. We find that under a critical value of GS, ${I}_{\textsf {read}}$ decreases with increase in ${T}_{\textsf {Si}}$. This is attributed to the fact that with smaller GS, the total number of grain boundaries and associated traps are significantly higher. Moreover, there exists a typical value of GS for which ${I}_{\textsf {read}}$ is independent of ${T}_{\textsf {Si}}$ , which is desirable to minimize the deviations in ${I}_{\textsf {read}}$ arising from ${T}_{\textsf {Si}}$ variations. The resulting tradeoff in the design of more efficient 3-D NAND flash is demonstrated and discussed. Further, it is found that ${I}_{\textsf {read}}$ increases significantly by limiting the polysilicon channel grain boundary trap concentration under 1012 cm−2. The results presented in this paper are crucial for optimizing ${I}_{\textsf {read}}$ and program/erase threshold voltage ( ${V}_{T}$ ) window, and serve as key guidelines in the design of 3-D NAND flash memory with better performance. [ABSTRACT FROM AUTHOR]

In negative capacitance field-effect transistors (NCFETs), drain current may decrease with increasing ${V}_{\mathrm {ds}}$ in the saturation region, leading to negative differential resistance (NDR). While NDR is useful for oscillator design, it is undesirable for most analog circuits. On the other hand, the tendency toward NDR may be used to reduce the normally positive output conductance ( ${g}_{ \mathrm {ds}}$ ) of a short-channel transistor to a nearly zero positive value to achieve higher voltage gain. In this paper, we analyze the NDR effect for NCFET in the static limit and demonstrate that it can be engineered to reduce ${g}_{\mathrm {ds}}$ degradation in short-channel devices. Small and positive $g_{\mathrm{ ds}}$ is achieved without compromising the subthreshold gain, which is crucial for analog applications. The 7-nm ITRS 2.0 FinFET with 0.7 V ${V}_{\mathrm {dd}}$ is used as the baseline device in this paper. [ABSTRACT FROM AUTHOR]

This paper presents experimental and simulation analysis of an $\Omega $ -shaped silicon junctionless nanowire field-effect transistor (JL-NWT) with gate lengths of 150 nm and diameter of the Si channel of 8 nm. Our experimental measurements reveal that the ON-currents up to 1.15 mA/ $\mu \text{m}$ for 1.0 V and 2.52 mA/ $\mu \text{m}$ for the 1.8-V gate overdrive with an OFF-current set at 100 nA/ $\mu \text{m}$. Also, the experiment data reveal more than eight orders of magnitude ON-current to OFF-current ratios and an excellent subthreshold slope of 66 mV/dec recorded at room temperature. The obtained experimental current–voltage characteristics are used as a reference point to calibrate the simulations models used in this paper. Our simulation data show good agreement with the experimental results. All simulations are based on drift-diffusion formalism with activated density gradient quantum corrections. Once the simulations methodology is established, the simulations are calibrated to the experimental data. After this, we have performed statistical numerical experiments of a set of 500 different JL-NWTs. Each device has a unique random distribution of the discrete dopants within the silicon body. From those statistical simulations, we extracted important figures of merit, such as OFF-current and ON-current, subthreshold slope, and voltage threshold. The performed statistical analysis, on samples of those 500 JL-NWTs, shows that the mean ${I}_{D} - {V}_{\text {Gs}}$ characteristic is in excellent agreement with the experimental measurements. Moreover, the mean ${I}_{D} - {V}_{\text {Gs}}$ characteristic reproduces better the subthreshold slope data obtained from the experiment in comparison to the continuous model simulation. Finally, performance predictions for the JL transistor with shorter gate lengths and thinner oxide regions are carried out. Among the simulated JL transistors, the configuration with 25-nm gate length and 2-nm oxide thickness shows the most promising characteristics offering scalable designs. [ABSTRACT FROM AUTHOR]

Energy efficiency has become the main concern of IC technology. Tunnel FET (TFET) is recognized to possess the superiority of energy efficiency over MOSFET at ultralow voltage, while variability might limit the voltage reduction and thus the energy saving. Recently, device source doping gradient (SDG) is found to be the dominant variation source in TFET. In this paper, for the first time, with the awareness of SDG variation, the energy efficiency of TFET-based circuits with different activity factors ( $\alpha $ ) is comprehensively reassessed and the device optimization strategy is provided. It is found that the superiority of energy efficiency of TFET will significantly decrease especially for the more active circuit due to the inherent tradeoff between SDG variation and nominal SDG. Based on the quantitative relationship between SDG variation and nominal SDG extracted from the experimental devices, the optimal design of tunnel junction abruptness to maximize the circuit energy efficiency is obtained, leading to significant energy efficiency improvements of TFET-based circuit over MOSFET even for circuit with high $\alpha $. This paper provides helpful device design guidelines for TFET with device variability awareness from the perspective of circuit energy efficiency. [ABSTRACT FROM AUTHOR]

In this paper, a ZnO-based semiconductor thin film memristor (300 nm in thickness) device is fabricated using metallic top and bottom electrodes by direct-current reactive magnetron sputter. The memristive characteristics of the device were completed by time-dependent current--voltage (I--V-t) measurements, and the typical pinched hysteresis I--V loops of the memristor were observed. This paper is continued with the designing memristor emulator circuit, which has only four MOS transistors. The proposed circuit is suitable both for emulating the fabricated memristor and for using general memristor-based applications. Any circuit blocks such as a multiplier or active element are not used in the circuit to obtain memristive characteristics. All results of the proposed memristor emulator circuit are compatible with general characteristics of the fabricated semiconductor device. The MOSFET-based proposed memristor emulator circuit is laid out in the Analog Design Environment of Cadence Software using 180-nmTSMC CMOS process parameters and its layout area is 366 μm². So as to show its performance, the dependences of the operating frequency and process corner as well as effects of radical temperature changes have been investigated in the simulation results section. [ABSTRACT FROM AUTHOR]

The function of conductive particles on the insulator for a simple case is analyzed in this paper. In a certain insulator containing conductive particles, the electric dipoles in the conductive particles are induced by the external electric field, and the polarization orientation is along the direction of electric field. Macroscopically, the insulator containing conductive particles can be equivalent to a high-permittivity (εeff) insulator. Meanwhile, the maximum electric field (Emax) in the insulator containing conductive particles is enhanced. The εeff and Emax are determined not only by the geometric shape, size, and the packing modes of conductive particles. This paper presents several packing modes of conductive particles in the insulator. Simulation results indicate that when cubic conductive particles with side length 2R are stacked in the form of cubic close packing, the εeff and the Emax of the insulator containing conductive particles at R/d = 0.495 (d is the distance between the centers of the mass of closet conductive particles) are increased to 67.1 times and 97.5 times, respectively, compared with the insulator without conductive particles inside. [ABSTRACT FROM AUTHOR]

In this paper, a high-quality crystalline thin film (~10 nm) of titanium dioxide (TiO2-II) phase is grown on p-GaAs (100) substrate by employing the vapor--liquid--solid method. The formation of crystalline TiO2-II films is confirmed by X-ray diffraction study. A very small rms surface roughness of ~1 nm has been measured from atomic force microscopy. The capacitance--voltage characteristics of Al/TiO2-II/GaAs metal--oxide--semiconductor (MOS) capacitor indicate the growth of excellent thin film of TiO2-II phase with high effective dielectric constant of 28, 35, 65, and 14 for the as-grown and 600 °C, 625 °C, and 650 °C annealed samples, respectively. An effective oxide thickness of ~0.7 nm, a negligible hysteresis of 10 mV, very small frequency dispersion of 3.5%, and a reduced gate leakage current of ~10-13 A/μm² at +2 V are achieved due to annealing in the temperature range of 600 °C-625 °C. Thus, this paper provides a cost-effective novel alternative technique to grow high-quality TiO2-II films on GaAs substrate which may be used as the reliable high-k gate dielectrics on III-V semiconductor-based MOS devices and circuits. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the impact of gate-source/drain underlap on short-channel behavior of junctionless (JL) transistor through a quasi-analytical model and 2-D numerical simulations. The proposed five-region model for potential is developed for the symmetric mode operation of double-gate (DG) JL MOSFET in the subthreshold regime, to predict and minimize short-channel effects (SCEs) using the optimum design of underlap regions. The five-region model can be transformed into four or three regions to incorporate the possible dependence of biases, doping, and gate workfunction with the underlap length. The parameters indicating SCEs can also be extracted using an analytical approximation for sub-threshold drain current. The results from the proposed model are in reasonable agreement with simulation data. Analyses show that underlap length is a critical parameter to restrict the lateral extension of depletion region into the ungated portion. With increasing the underlap length, SCEs improve prominently for moderate doping concentration (1018 cm-3). The improvement in SCEs ceases once the device achieves the maximum lateral extension of the depletion region. This paper provides the physical insights into the optimal use of underlap region in nanoscale JL devices for suppressing SCEs. [ABSTRACT FROM AUTHOR]

An innovative complementary electric split-ring resonator metamaterial (MTM) structure applied as the slow-wave circuit for a cascade backward-wave oscillator (CBWO) operating in C-band is studied in this paper. The idea of a drift tube in a multiresonant cavity extended interaction klystronis borrowed to design a novel backward-wave oscillator (BWO). The construction of this device features two BWOs separated by a short cutoff waveguide for permitting the flow of the electronbeam and stopping the electromagnetic wave. The high-frequency characteristics are analyzed and optimized by using a high-frequency structure simulator and computer simulation technology (CST). Meanwhile, the S-parameter retrieval approach is used to retrieve the effective permittivity and permeability. In addition, the CST code is adopted to investigate the performance of the MTM-based CBWO. The particle-in-cell simulation results show that the novel CBWO is capable of achieving over 51.77% electronic efficiency from 4.8344 to 4.8687GHz. Meanwhile, the maximum electronic efficiency can reach 82.44%, corresponding to a peak output power of 14.51 MW at 4.8466 GHz. These results indicate that the MTM-based CBWO proposed in this paper has the characteristic of miniaturization, manufacturability, and high electronic efficiency. [ABSTRACT FROM AUTHOR]