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The dielectric screening property of a semiconductor is very crucial for the electrical characteristics of a MOSFET, and which can be described mathematically by Poisson equation via the permittivity. While the theory and experiments have corroborated the permittivity reduction of nanoscale Si, this paper studies the electrical characteristics of MOSFETs considering the reduced channel permittivity by quantum transport simulations. It is found that the channel permittivity reduction may mitigate the short-channel effects, showing subthreshold swing improvement and threshold voltage shift of MOSFETs in nanoscale. Compared to quantization effects, the positive and negative impacts of the channel permittivity reduction on the devices in particularly nanoscale have been investigated. This paper elucidates the necessity of considering semiconductor permittivity reduction for nanoscale device design and simulations. [ABSTRACT FROM AUTHOR]

In this paper, we have developed a physics-based analytical model for the electrical characteristics of passivated silicon carrier-selective contact (CSC) solar cells and validated it with numerical simulations. The model comprises analytical solutions of: 1) the Poisson equation, accurately capturing the level of inversion and accumulation at the crystalline silicon (c-Si) layer interfaces, and 2) the recombination current capturing the various recombination mechanisms at work in the solar cell. The calculations establish that CSC solar cells have the potential to achieve an efficiency greater than 26% even when both c-Si interfaces have realistic SRV values of 100 cm/s. The model helps illustrate the physics underlying the performance of CSC solar cells for variation in key device parameters such as surface recombination velocities, bulk lifetime, contact layer doping, and amorphous silicon (a-Si) thickness amongst others. By circumventing the need for resource-intensive numerical simulations, the analytical model described in this paper can assist in the design and development of high-performance CSC solar cells. [ABSTRACT FROM AUTHOR]

In this paper, an analytical model has been developed to observe the recombination losses involved in a tunnel oxide passivated contact solar cell with a carrier-selective layer constituting polycrystalline silicon (poly-Si). The main focus of this paper is to observe the contribution of each component of recombination current density and its effect on open-circuit voltage, Voc. The effect of emitter saturation current density (Joe), surface recombination velocity, substrate thickness, and doping density of carrier-selective layer on Voc has been presented. The analysis indicates that Voc = 766 mV can be achieved for Joe = 2 fA/cm2, and a doping density of poly-Si > 1021cm−3 in a c-Si/SiO2/poly-Si contact for a 50- $\mu \text{m}$ -thick substrate in case of ideal surface passivation. For identical conditions, Voc attains a lower value of 750mV for a 180- $\mu \text{m}$ -thick substrate. The dependence of Voc on bandgap of tunnel layers has also been observed by considering other materials like Si3N4 and SiC. These results from the analyticalmodel have been compared with results froma simulation using automat FOR simulation of HETerostructures v2.5 and have been found to be in good agreement with each other. [ABSTRACT FROM AUTHOR]

In this paper, we develop an explicit model to predict the dc electrical behavior in ultrathin surrounding gate junctionless (JL) nanowire field-effect transistors (FETs). The proposed model considers 2-D electrical and geometrical confinements of carrier charge density within few discrete subbands. Combining a parabolic approximation of the Poisson equation, the first-order perturbation theory for the Schrödinger subband energy eigen-values and the Fermi–Dirac statistics for the confined carrier density lead to an explicit solution of the dc characteristic in ultrathin JL devices. Validity of the model has been verified with technology computer-aided design simulations. The results confirm its validity for all regions of operation, i.e., from deep depletion to accumulation and from linear to saturation. This represents an essential step toward analysis of circuits based on JL nanowire devices. [ABSTRACT FROM AUTHOR]

In this paper, we have reported a renovated silicon-based tunnel field-effect transistor (TFET) structure with a channel length of 21 nm. The proposed structure has been optimized and analytically modeled. The broken gate TFET (BG-TFET) shows very low ambipolar current, good subthreshold swing (SS) and ON-currents comparable to the contemporary structures of similar dimensions. The surface potential and the electric field inside the device are modeled by solving the 2-D Poisson’s equation. The drain current is also modeled based on Kane’s generation rate. The results obtained from the analysis are validated against Synopsys Sentaurus TCAD nonlocal tunneling model-based simulations. [ABSTRACT FROM AUTHOR]

More and more attention has been paid to the heterogeneous semiconductor device based on the wafer-bonding method due to its high-quality wafer-bonded active layer. In this paper, we first theoretically study the dependence of the single-photon properties, including the single-photon detection efficiency (SPDE), dark count rate (DCR), and afterpulsing probability (AP), of the wafer-bonded Ge/Si single-photon avalanche photodiode (SPAD) on the interface state at the Ge/Si (hydrophilic reaction) and Si-Si (hydrophobic reaction or surface-activated method) wafer-bonded interface based on the Poisson statistics. It is found that the interface state density and the energy level position of the interface state significantly affect the linear-mode electric field distribution (avalanche probability), 3-dB bandwidth (dark carriers), gain (quantum efficiency), and effective transit time (trapped carriers), which in turn affect the DCR and the SPDE. Furthermore, the dependence of the AP on the avalanche charge and the interface recombination rate is clarified as well. It is expected that this paper may give guidance for the fabrication of high-performance SPAD. [ABSTRACT FROM PUBLISHER]

In this paper, a through-silicon via (TSV) array under Gaussian pulse is studied comprehensively with a rigorous consideration of its electrothermal characteristics. To enhance the computational efficiency and reduce the memory cost, we develop a unified radial point interpolation method (RPIM) to handle these TSV electrothermal coupling problems. The comparison between the results of the proposed formulas and fine-grid finite-element method (FEM) shows that the RPIM has a very high accuracy and reduces computational time by up to 88% in comparison with the fine-grid FEM. The transient temperature responses are studied in detail for three layouts of single-layered TSV arrays with different silicon dioxide layer thicknesses and areas enclosed by TSVs. Furthermore, the two-layered TSV array structure including microbumps and RDLs is simulated electrothermally to verify the scalability of this method. Our work demonstrated the capability of addressing a large number of TSV arrays and the proposed method enables faster and more accurate electrothermal design of TSV-based 3-D ICs. [ABSTRACT FROM AUTHOR]

This paper reports on the usefulness of shell-doped (SD) junctionless (JL) transistor architecture for operation as capacitorless dynamic random-access memory (1T-DRAM). SD topology overcomes the problem associated with shallower potential depth in heavily doped devices, thereby enhancing the retention time (RT) along with improved scalability. The use of a thinner shell for achieving high RT is beneficial as it reduces generation and recombination of holes. The results show that an undoped core region with shell thickness (${T}_{\textsf {Shell}}$) of 2 nm yields maximum retention. An SD (${N}_{\mathrm {d}}$) of $10^{18}$ cm $^{-\textsf {3}}$ attains RT of ~5.5 s and ~630 ms at 27 °C and 85 °C, respectively, whereas higher ${N}_{\textsf {d}}$ ($10^{19}$ cm $^{-\textsf {3}}$ shows RT of ~13ms at 85 °C for ${L}_{\textsf {g}} = \textsf {200}$ nm. SD JL transistor shows less degradation in RT with temperature. A 10 nm SD JL device with RT of ~11 ms at 85 °C demonstrates applicability as 1T-DRAM at shorter gate lengths. [ABSTRACT FROM AUTHOR]

This paper presents a commercial or industrial view of III–V compact models for circuit design. We contrast the requirements of III–V modeling to those of silicon. The differences in requirements are strongly rooted in the applications that III–V devices are used in the end user of III–V models and the differences in the “ecosystems” of the technologies. These differences create both challenges and opportunity for the III–V modeling community. [ABSTRACT FROM AUTHOR]

Silicon-based quantum computing has the potential advantages of low cost, high integration density, and compatibility with CMOS technologies. The detuning mechanism has been used to experimentally achieve silicon two-qubit quantum gates and programmable quantum processors. In this paper, the scaling behaviors and variability issues are explored by numerical device simulations of a model silicon quantum gate based on the detuning mechanism. The device physics of quantum gates modulation, tradeoff between device speed and quantum fidelity, and impact of variability on the implementation of a quantum algorithm are examined. The results indicate the attractive potential to achieve high speed and fidelity silicon quantum gates with a low operation voltage. To scale up, reducing the device variability and mitigating the variability effect are identified to be indispensable for reliable implementing a quantum computing algorithm with the silicon quantum gates based on the detuning mechanism. A scheme to use the control electronics for mitigating the variability of quantum gates is proposed. [ABSTRACT FROM AUTHOR]

In this paper, a universal analytical current model for a double-gate Si-based tunnel field-effect transistor (TFET) is presented considering the effects of charges in source depletion region and channel. An accurate surface potential model is developed first by solving the pseudo-2-D Poisson equations in the depletion regions, and then is used to calculate the drain tunneling current. The modeling results match well with that obtained from the Technology computer-aided design simulations under various biasing conditions, which indicate that the analytical current model would be very helpful for the further TFET-based circuits design. Furthermore, the influence of the source depletion is also studied, and the presented model with considering the source depletion region and the channel inversion charges is proved to be much more accurate than that ignoring the source depletion. [ABSTRACT FROM AUTHOR]

This paper presents a predictive device model implemented by a self-consistent solution of Poisson–Schrödinger drift-diffusion formulation for a thermally sensitive detector based on a ${\mathrm {Si/Si}}_{{1}-{x}}{\mathrm {Ge}}_{{x}}$ multiquantum-well structure. The physical phenomena governing the carrier transport were modeled to investigate the effect of physical design aspects (Ge content, well periodicity, and well thickness). In particular, we have analyzed the effect of these physical design parameters on the carrier dynamics quantified by the dc performance in terms of net current density. A fully integrated simulation framework was developed and employed to optimize Ge content and device doping for a desired figure of merits specified by temperature coefficient of resistance (TCR) and dc resistance (${R}$). This methodology was successfully utilized to realize device profiles for various amounts of Ge content and optimization of (${R}$) geared for both high TCR and low noise. The dc performance metrics of the optimized profiles obtained by modeling presented here are compared and validated with the fabricated test devices. [ABSTRACT FROM AUTHOR]

This paper compares two different analytic solutions to the 2-D potential in double-gate MOSFETs in subthreshold: Green’s function method and scale length model. Both models produce closed-form potential functions for every point in Si based on rigorous approaches to Poisson’s equation with boundary conditions. It is shown that despite the vastly different mathematical equations, the ${I}_{\textsf {ds}}$ – ${V}_{\textsf {gs}}$ characteristics generated from each model are completely consistent with each other and with Technology Computer Aided Design (TCAD). Testing examples include undoped and highly doped cases of both polarities, junction and junctionless. Also included is a case of severe short-channel effects. [ABSTRACT FROM AUTHOR]

Investigating random telegraph signals (RTS) observed in MOS devices is important for studying the gate-oxide defect characteristics and developing simulation and modeling tools in highly scaled devices. In this paper, we are presenting a comprehensive, variable-temperature, single-to-multitrap scalable RTS model and a simulation tool (RTSSIM) based on the first principles, and supported by experimental data. The physical and electrical characteristics of the actual oxide defects are considered, such as trapping barrier energy, capture cross section, trap-binding enthalpy, entropy change with emission, Coulombic scattering effect, and the trap location. Experimentally obtained time-domain switching data and RTS traces reconstructed by the developed simulation tool are compared for assessing the accuracy of the modeling. In this paper, we identified the trap species responsible for the RTS as an unrelaxed neutral oxygen deficiency center ( V^0 ODC II) with measured and theoretically verified relaxation energy of 1.11, 1.25, and 0.60 eV. RTSSIM is a tool used to mimic or reproduce a given noise measurement on a particular device. The simulation tool shows over 92% accuracy in replicating the RTS and trap characteristics. The model also represents the first realistic simulation of multilevel RTS. [ABSTRACT FROM AUTHOR]

This paper presents the quantum analytical model, based on the self-consistent solution of 1-D Schrödinger equation and 2-D Poisson’s equation for the ultrascaled dual-material double-gate (DMDG) silicon-on-nothing MOSFET structure. The quantum mechanical effects (QMEs) have been incorporated in our model to derive the analytical current expressions for the first time ever. Extensive calculations have been carried out to analyze the QMEs on such device performance parameters, like electric field, transconductance, drain conductance, and voltage gain. A comparative analysis based on the drain current has been presented in this paper for the classical and for the quantum model. The authenticity of our proposed quantum model for the DMDG structure is verified by the agreement among the results obtained from the analytical model as well as simulations. [ABSTRACT FROM AUTHOR]

In this paper, the effect of a choice of the tunneling path approach on electrical characteristics of the silicon tunnel field-effect transistor (TFET) is theoretically investigated with the use of a developed 2-D semiclassical numerical simulator and a nonlocal band-to-band tunneling generation model. Three different tunneling path approaches are defined and examined: horizontal path, maximum valence band gradient, and minimum tunneling distance. Double-gate (DG) and single-gate (SG) transistor structures are considered, and effects of the silicon body thickness and the gate–source overlap are investigated. The differently defined tunneling paths lead to significantly different on currents. It is shown that the minimum tunneling distance approach results in the highest tunnel current, whereas the horizontal path approach underestimates the current, especially for thick semiconductor body layers and the SG transistor structures. A choice of the tunneling path approach can be crucial for the accuracy of modeling the drain current of the TFETs. [ABSTRACT FROM AUTHOR]

This paper proposes a novel kinetic velocity model (KVM) for the drift-diffusion (DD) transport approach to describe ballistic effects. It also presents a simulation study of the ballistic effect in short-channel InGaAs and silicon FETs. Monte Carlo and subband Boltzmann transport equation results as well as DD simulations using the simple gate length-dependent ballistic mobility proposed in the literature and the KVM model are compared and discussed. Basic concepts, such as the Matthiessen rule and Fermi-Dirac statistics, are analyzed with a view on ballistic transport in devices in the linear and saturation regimes. [ABSTRACT FROM AUTHOR]

A new technique to control the kink effect in the high-voltage lateral double-diffused MOSFET (LDMOS) is presented in this paper. This technique produces a local minimum in the band diagram of the proposed structure, which causes the lower barrier height for the holes from the channel to the source region. So, the produced excess holes during the impact ionization process in the channel are reduced significantly. We have called the proposed structure as local minimum energy band LDMOS (LMEB-LDMOS) transistor. The LMEB-LDMOS structure contains modified source and drain regions. The modified source region creates a local minimum in the energy band diagram for absorbing the excess holes, and the modified drain region causes high breakdown voltage (462 V) and low specific on-resistance ( 5.1~\text m\Omega \cdot ~\text cm^2) . Also, the drift region with lower doping density than drain is deleted in LMEB-LDMOS transistor. The simulation with 2-D ATLAS simulator shows that the proposed structure improves the device performance. [ABSTRACT FROM PUBLISHER]

In this paper, we have developed an analytical model of double gate MOSFET using Green’s function approach in the subthreshold regime of operation. The exact analytical solution to 2-D Poisson’s equation by Green’s function approach is redefined and Fourier coefficients are calculated correctly that has a direct impact on the outcomes of the model. The approach considers 2-D mixed boundary conditions and multizone techniques while deriving potential equations. It is observed that the Green’s function approach of solving 2-D Poisson’s equation in both oxide and silicon region can accurately predict channel potential, subthreshold current ( I {\mathsf {sub}} ), and subthreshold slope of both long and short channel devices designed with higher as well as lower t {\mathsf {si}}/t {\mathsf {ox}} oxide thickness ratio. [ABSTRACT FROM PUBLISHER]

In this paper, a 2-D analytical model for surface potential and threshold voltage of novel vertical super-thin body (VSTB) FET has been derived by solving 2-D Poisson equation. The analytical surface potential expression for gate-side surface and sidewall side surface has been modeled using parabolic surface potential approximation. The threshold voltage model for the VSTB FET has been derived by applying strong inversion criterion at the surface potential minimum value. The threshold voltage model for the VSTB FET has been analyzed by varying the body thickness, oxide thickness, and channel doping concentrations. The drain-induced barrier lowering and threshold voltage roll-off parameters are also extracted and analyzed for different body thicknesses. The models for surface potential and threshold voltage have been compared with the results obtained from the 2-D numerical device simulator and a very good agreement between the two has been observed. [ABSTRACT FROM AUTHOR]

The field of flexible electronics is rapidly evolving. The ultrathin chips are being used to address the high-performance requirements of many applications. However, simulation and prediction of changes in response of device/circuit due to bending induced stress remains a challenge as of lack of suitable compact models. This makes circuit designing for bendable electronics a difficult task. This paper presents advances in this direction, through compressive and tensile stress studies on transistors and simple circuits such as inverters with different channel lengths and orientations of transistors on ultrathin chips. Different designs of devices and circuits in a standard CMOS 0.18- \mu \textm technology were fabricated in two separated chips. The two fabricated chips were thinned down to 20~\mu \textm using standard dicing-before-grinding technique steps followed by post-CMOS processing to obtain sufficient bendability (20-mm bending radius, or 0.05% nominal strain). Electrical characterization was performed by packaging the thinned chip on a flexible substrate. Experimental results show change of carrier mobilities in respective transistors, and switching threshold voltage of the inverters during different bending conditions (maximum percentage change of 2% for compressive and 4% for tensile stress). To simulate these changes, a compact model, which is a combination of mathematical equations and extracted parameters from BSIM4, has been developed in Verilog-A and compiled into Cadence Virtuoso environment. The proposed model predicts the mobility variations and threshold voltage in compressive and tensile bending stress conditions and orientations, and shows an agreement with the experimental measurements (1% for compressive and 0.6% for tensile stress mismatch). [ABSTRACT FROM PUBLISHER]

In this paper, we investigate a polarity controlled electrically doped tunnel FET (ED-TFET) based on the bandgap engineering for analog/RF applications. The proposed device exhibits a heavily doped n-type Si-channel with two distinctive gate: 1) control gate (CG) and 2) polarity gate (PG). First, the work function of 4.72 eV is considered for CG and PG to convert the layer beneath CG and PG of intrinsic type. Further, a bias of −1.2 V is applied at PG terminal to induce a p+ region, so that, it follows the similar trend as like a n+-i-p+ gated structure of conventional TFET. To improve the ON-state current of the proposed device, we investigate an interfacing of III–V with IV group material for heterojunction. It shows higher ON-state current in the order of 10^-4 A/ \mu \textm , I \mathrm{\scriptscriptstyle ON}/I \mathrm{\scriptscriptstyle OFF} ratio (in the order of 10^12 ) at V\sf DS = 0.7 V. Further, its higher transconductance g m\approx 1.02 mS and different RF performance parameters in the range of terahertz, enables its potential for analog/RF applications. However, linearity parameters are analyzed to give the assurance of the device for high-frequency applications. Moreover, a nonquasi-static RF model is adopted to analyze the behavior of the proposed ED-TFET in high frequency region. Based on this, the small-signal parameters were extracted and verified upto 500 GHz. The modeled result shows excellentmatching with the Y-parameters upto 500 GHz. [ABSTRACT FROM PUBLISHER]

The modeling and analysis of recombination properties is one of the critical aspects in the design and development of high efficiency amorphous silicon (a-Si)/crystalline silicon (c-Si) heterostructure solar cell (SH-SC). In this paper, we have developed a recombination model pertinent for a-Si/c-Si SH-SC. Based on the model, an analytical expression for the relationship between effective carrier lifetime ( \tau \mathrm {eff} ) and excess carrier concentration ( \Delta n ), commonly termed as lifetime curve, is derived and the results are validated with the experimental data. The results show that the inverse of \tau \mathrm {eff} , after correcting for the contributions of Auger and radiative recombination in silicon, when plotted as a function of \Delta n$ , shows a linear characteristic, with each of the slope and the intercept, providing definitive details about the recombination processes occurring in the device. [ABSTRACT FROM PUBLISHER]

Computational study of electrothermal effects on hot-carrier injection (HCI) in 100-nm silicon-on-insulator (SOI) MOSFET for digital integrated circuit is performed using in-house developed time-domain finite element algorithm. The simulated $I$ – $V$ curve is obtained by solving diffusive carrier transport equations, and it agrees well with our measured results. The time-dependent thermal conduction equation is solved to get the transient temperature response of the device. Furthermore, according to the transient temperature responses to different signal stresses, including step pulse, ac signal, and pseudorandom binary sequence (PRBS), HCI-induced threshold voltage shift (TVS) is captured by accounting for the temperature dependence of HCI. It is shown that the TVS of device under PRBS stress, which is used to mimic the circuit speed operation, is slightly larger than that of the device under ac signal with the same frequency. With the frequency of signal stress decreasing from gigahertz to tens of megahertz, TVS becomes more severe, because the temperature during ON-state is higher for the SOI MOSFET under low-frequency stress. Thick buried oxide leads to high temperature in channel and deteriorates the HCI. The method presented in this paper should also be applicable to the other MOSFET counterparts. [ABSTRACT FROM AUTHOR]

Nanostructured silicon oxide impedance biosensors with ordered nanopores promise highly sensitive and selective label-free electrical detection of biomolecules through unique frequency-dependent sensitivity characteristics. Despite these promising experimental results, the fundamental mechanisms controlling the frequency-dependent phenomena and hence the design considerations have not been explored. In this paper, we consistently model the fluid and the solid regions of the sensors and discuss the design issues with respect to the pore dimensions for enhancing the sensitivity, selectivity, and repeatability toward detection of ultralow and moderate concentration of target biomolecules. The simulation results have been validated with experiments. The results indicate that the optimal design of nanoporous silicon oxide biosensors is different from the conventional idea of increasing the surface-to-volume ratio of such sensors. Instead, the design approach is nontrivial and the optimum pore dimensions are dependent on the target biomolecule charge, concentration, and distribution. It has been observed that a figure of merit is essential to design such sensors with improved commercial viability. [ABSTRACT FROM PUBLISHER]

This paper demonstrates that collector current ( IC ), dc current gain ( \beta ), cutoff frequency ( f_{T} ), and maximum oscillation frequency ( f_{\max } ) of bipolar transistors (BJTs) can be improved by uniaxial stress. A unified modeling approach that includes a piezoresistive model for changes in mobility and a deformation potential model for changes in intrinsic carrier concentration was used to analyze the stress effects. This approach provides clear insight into the dominant effects of stress on BJT parameters. Experimental results of uniaxial in-plane normal stress are compared with simulation results. Our analysis reveals that for a vertical npn, substantial enhancement in \beta , f_{T} and f_{\max } can be achieved using a uniaxial in-plane compressive or out-of-plane tensile stress. In a vertical pnp, considerable improvement in \beta , f_{T} , and f_{\max }$ are minimal. These results show that stress analysis/prediction for different current-stress orientations can be performed with this model and the outcome can be used as a guide for strain engineering in BJTs. [ABSTRACT FROM PUBLISHER]

In this paper, a detailed evaluation of sub-10-nm n-/p-type GaSb–InAs double-gate tunneling FETs (TFETs) is presented. Source underlapping is shown to achieve lower subthreshold swing (SS) in both n- and p-type GaSb–InAs TFETs and is verified with the analytical treatment. The impact of parameter variations on the performance of underlapped TFETs is investigated through atomistic, 2-D ballistic simulations using self-consistently coupled nonequilibrium Green’s function-Poisson approach. Variations in underlap length, underlap doping, fin thickness, and temperature are comprehensively studied. It is shown that the underlap length of 6 nm is optimal for achieving low SS and it is found that the underlapped TFETs can maintain sub-60-mV/decade SS even when 3-nm fin thickness is relaxed by 40%. We also study the potential of TFETs in ultralow-power and high-density dynamic memories. A novel 4T gain cell embedded Dynamic Random Access Memory (e-DRAM) is proposed, which utilizes the low-leakage current of the source-underlapped TFETs to improve the data-retention time to 25 \mu \texts at V\mathrm {DD}=0.35 V, thereby enabling the prospects of e-DRAM at nanoscale gate lengths operating at ultralow supply voltages. [ABSTRACT FROM PUBLISHER]

In this paper, an analytical potential-based model in the subthreshold regime for short-channel junctionless cylindrical surrounding-gate MOSFETs is proposed as the source/drain depletion effect considered. The threshold voltage ( V\textrm {th} ), subthreshold slope, and drain-induced barrier lowering are also correspondingly derived, which give explicit explanations of the short-channel effects on junctionless MOSFETs in the subthreshold regime. The compact model is verified by the numerical simulation, and the results match well. [ABSTRACT FROM AUTHOR]

For ac negative bias temperature instability (NBTI), the composite model that combines the reaction–diffusion (R–D) model for permanent component and the trap–detrap (T–D) model for recoverable component has almost been accepted. However, simple analytical formulas, which are useful for product qualification, have not yet been established. In this paper, we present a coarse-graining approach to analyze the rate equations in the T–D and R–D schemes. Here, the time-averaged rate equations are derived from the equations for stress and recovery phases. The analytical solutions obtained by solving this set of equations can explain the essential features of ac-NBTI, such as the duty-cycle dependence and the memory effect of hole-trapping determined by the standby condition. For the T–D scheme, the exact analytical solutions of the original equations verify this approach, whereas for the R–D scheme, the double-interface R–D model rather than the conventional R–D model captures the duty-cycle dependence observed in the experimental universal curve. Our experimental data on the ac-NBTI are also consistent with the developed analytical model providing a general validity of the approach presented here. [ABSTRACT FROM AUTHOR]

This paper presents a simulation study using a novel distributive quasi-ballistic drift diffusion (DD) TCAD model applied to low mobility unstressed and high mobility stressed scaled pMOS devices. The model is implemented in a DD simulator and used to study the gate length dependence of current drives. The new model captures the physically correct potential distribution and gives the correct drive current limit in ballistic devices for both linear current response and current saturation source–drain bias conditions. The diffusive and ballistic transport is connected using a ballistic probability, which relates to the fundamental time scale in the problem—the mean energy relaxation time. The model captures the ballistic velocity degradation from the diffusive limit at linear source–drain biases. It is shown that the DD simulation with the distributive quasi-ballistic model describes the stress ballistic drive gains at high driving field, which are missed by the existing ballistic models. [ABSTRACT FROM AUTHOR]

Wide bandgap power devices have emerged as an often superior alternative power switch technology for many power electronic applications. These devices theoretically have excellent material properties enabling power device operation at higher switching frequencies and higher temperatures compared with conventional silicon devices. However, material defects can dominate device behavior, particularly over time, and this should be strongly considered when trying to model actual characteristics of currently available devices. Compact models of wide bandgap power devices are necessary to analyze and evaluate their impact on circuit and system performance. Available compact models, i.e., models compatible with circuit-level simulators, are reviewed. In particular, this paper presents a review of compact models for silicon carbide power diodes and MOSFETs. [ABSTRACT FROM AUTHOR]

This paper presents the results of mathematical modeling of heat transfer in the field emission process in a conic cathode of small dimensions with its possible melting considered. It is shown that the possibility of melting is determined by the cathode vertex angle. The melting is modeled in the framework of the phase field system using the proposed methods for the formation of the liquid phase zone. [ABSTRACT FROM AUTHOR]

Existing compact models for common double-gate (CDG) MOSFETs are based on the fundamental assumption of having symmetric gate oxide thickness. In this paper, we demonstrate that using the unique quasi-linear relationship between the surface potentials, it is possible to develop compact model for CDG-MOSFETs without such approximation while preserving the mathematical complexity at the same level of the existing models. In the proposed model, the surface potential relationship is used to include the drain-induced barrier lowering, channel length modulation, velocity saturation, and quantum mechanical effect in the long-channel model and good agreement is observed with the technology computer aided design simulation results. [ABSTRACT FROM AUTHOR]

In this paper, we have worked out a pseudo-2-D-analytical model for surface potential and drain current of a long channel p-type dual material gate gate all-around nanowire tunneling field-effect transistor. The model incorporates the effect of drain voltage, gate metal work functions, thickness of oxide, and silicon nanowire radius. The model does not assume a fully depleted channel. With the help of this model, we have demonstrated the accumulation of charge at the interface of the two gates. The accuracy of the model is tested using the 3-D device simulator Silvaco Atlas. [ABSTRACT FROM AUTHOR]