Search

The dielectric screening property of a semiconductor is very crucial for the electrical characteristics of a MOSFET, and which can be described mathematically by Poisson equation via the permittivity. While the theory and experiments have corroborated the permittivity reduction of nanoscale Si, this paper studies the electrical characteristics of MOSFETs considering the reduced channel permittivity by quantum transport simulations. It is found that the channel permittivity reduction may mitigate the short-channel effects, showing subthreshold swing improvement and threshold voltage shift of MOSFETs in nanoscale. Compared to quantization effects, the positive and negative impacts of the channel permittivity reduction on the devices in particularly nanoscale have been investigated. This paper elucidates the necessity of considering semiconductor permittivity reduction for nanoscale device design and simulations. [ABSTRACT FROM AUTHOR]

Inverter delay is often evaluated as $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ , where ${C}$ is the load capacitance, ${V}_{\text {dd}}$ is the supply voltage, and ${I}_{\text {eff}}$ is the effective drive current derived by approximating the inverter switching trajectory with a linear model. The ${I}_{\text {eff}}$ model utilizes high and low drain currents conventionally measured in wafer acceptance tests and does not require extraction of any parameters. Ease of use combined with reasonable accuracy (~15%) is the main reason for wide application of $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ delay metrics. However, $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ expression produces large errors when applied to another two important basic circuits: NAND and NOR. This is because NAND and NOR circuits contain transistor series connections not accounted for in the inverter model. In this paper, an analytical solution for the transistor series connection influence on the discharge/charge operation in NAND/NOR circuits is provided. The model for NAND/NOR effective drive current (denoted as ${I}_{\text {stack}}$) developed in this paper maintains simplicity of the original ${I}_{\text {eff}}$ expression. It requires only one additional measurement of the linear current. Model accuracy was assessed by comparing to extensive SPICE delay simulations of NAND and NOR circuits designed using state-of-the-art MOS technologies. Comparison results show that $\textit {CV}_{\text {dd}}/{I}_{\text {stack}}$ equation provides ~15% accuracy for NAND/NOR circuits in line with $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ accuracy for inverter. In an era of emphasis on low-power design, the developed model presents convenient means of exploring design space when optimizing circuit supply voltage for low-power operation. [ABSTRACT FROM AUTHOR]

The minimum specific ON-resistance $\text{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ of the semisuperjunction (semi-SJ) device is realized in this paper. Based on the similar SJ optimization method in our previous works, the minimum $\text{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ of the semi-SJ is searched by optimizing both the semi-SJ and the N-buffer regions. The proposed design formulas give the optimized doping concentration $\text{N}_{\textsf {SJ}}$ of the semi-SJ region, doping concentration $\text{N}_{\textsf {B}}$ , and length $\text{L}_{\textsf {B}}$ of the N-buffer region, respectively. As examples, 1000- and 1500-V semi-SJ devices are designed with the formulas. The calculated results are in a good agreement with the simulations. The comparisons between the simulations and the existing experiments demonstrate that the optimization in this paper realizes lower $\text{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ under the same breakdown voltage $\text{V}_{\textsf {B}}$ even with a shorter SJ length. [ABSTRACT FROM AUTHOR]

In this paper, the pinning process of pinned photodiodes (PPDs) is described by a new analytical model, assuming the PPD to be composed of inner and junction regions. There are two definitions of the pinning potential: maximum conduction band potential variation ($\Delta \varphi _{M}$) and maximum electron quasi-fermi level potential variation ($\Delta $ FP $_{M}$). The output of the previous pinning potential models is only an approximation of $\Delta \varphi _{M}$. In this paper, a comprehensive model is proposed in which both aforementioned definitions of pinning potential can be achieved analytically. The proposed model is a system of equations relating PPD’s main characteristics such as $\Delta \varphi _{M}$ and equilibrium full-well capacity to other main PPD parameters such as PPD spatial dimensions, impurity dopant concentrations, maximum inner region potential, and remnant carrier population at $\Delta \varphi _{M}$. The proposed model is verified by two previously reported experiment-based data. [ABSTRACT FROM AUTHOR]

This paper proposes a semianalytical model to estimate short-channel effects for independent gate operation in double-gate (DG) junctionless (JL) MOSFET incorporating gate-to-source/drain underlap, through the solution of Poisson’s equations in the subthreshold regime. The model also accounts for the asymmetry in device operation through variation in gate oxide thicknesses, gate work functions, and underlap lengths. Subthreshold drain current, threshold voltage, and subthreshold swing, evaluated from the channel potential, show reasonable agreement with simulation data. Results suggest the use of negative back gate bias and longer underlap length to reduce off-current. This paper highlights the role of doping, underlap length, and back gate bias in tuning the threshold voltage. This model serves as a generic formulation (within limits) with different asymmetries to estimate, design, and optimize self-aligned DG JL transistors for subthreshold logic applications. [ABSTRACT FROM AUTHOR]

In this paper, we develop an explicit model to predict the dc electrical behavior in ultrathin surrounding gate junctionless (JL) nanowire field-effect transistors (FETs). The proposed model considers 2-D electrical and geometrical confinements of carrier charge density within few discrete subbands. Combining a parabolic approximation of the Poisson equation, the first-order perturbation theory for the Schrödinger subband energy eigen-values and the Fermi–Dirac statistics for the confined carrier density lead to an explicit solution of the dc characteristic in ultrathin JL devices. Validity of the model has been verified with technology computer-aided design simulations. The results confirm its validity for all regions of operation, i.e., from deep depletion to accumulation and from linear to saturation. This represents an essential step toward analysis of circuits based on JL nanowire devices. [ABSTRACT FROM AUTHOR]

In this paper, we have reported a renovated silicon-based tunnel field-effect transistor (TFET) structure with a channel length of 21 nm. The proposed structure has been optimized and analytically modeled. The broken gate TFET (BG-TFET) shows very low ambipolar current, good subthreshold swing (SS) and ON-currents comparable to the contemporary structures of similar dimensions. The surface potential and the electric field inside the device are modeled by solving the 2-D Poisson’s equation. The drain current is also modeled based on Kane’s generation rate. The results obtained from the analysis are validated against Synopsys Sentaurus TCAD nonlocal tunneling model-based simulations. [ABSTRACT FROM AUTHOR]

In this paper, we present analytical models which are valid in all regions of operation and can accurately predict the potential profile and the output, as well as the transfer characteristics of the gate-all-around heterojunction tunnel field-effect transistors. Our potential model takes into account the charge carriers in the channel, as well as the space charges in the depletion regions of the two reservoirs. Later, this potential model is utilized to calculate the band-to-band tunneling generation rates at any spatial coordinate in the tunneling volume. Next, these rates are integrated over tunneling volume to find the total tunneling current. This leads to an analytical model for the drain current. We validate our models against the data obtained via numerical simulations for several common heterojunction tunnel devices at various geometries and bias conditions. [ABSTRACT FROM AUTHOR]

In this response, we show that the paper by Kim et al. by our group has a different research purpose and uses different modeling processes, which was not described in the previous work by Ortiz-Conde et al. The comments issued by Ortiz-Conde et al., who claim that our paper corresponds to a particular case of their previous work, are in our opinion overgeneralized. Differences compared to Ortiz-Conde’s previous work are discussed in detail. We also explain how the problem on threshold voltage pointed out by Ortiz-Conde et al. can be solved through a semiempirical method from measured data. [ABSTRACT FROM AUTHOR]

In this paper, we present a novel generalized multiparticle drift-diffusion (mp-DD) model capable to overcome some limitations imposed by the classic drift-diffusion model by taking into account multiple carrier populations. We demonstrate the model’s ability and flexibility in simulating systems from different application contexts. We conclude that the developed mp-DD model allows investigating a wide range of complex mechanisms, such as subband charge transport calculation or intersystem crossing (ISC), which are crucial for the understanding and design of organic and inorganic semiconductor devices largely employed for both photovoltaics and light emitting applications. [ABSTRACT FROM AUTHOR]

In spite of the apparent simplicity of the system under study, compact modeling of complementary resistive switching (CRS) devices, i.e., two antiserially connected memristive structures, is by no means straightforward. This requires a deep understanding of the voltage drops occurring across the circuit elements and correct treatment of the so-called snapback (SB) effect typical of the breakdown process of a thin dielectric film in an MIS or a MIM structure. The SB effect fundamentally consists in a sudden reduction of the device resistance caused by the formation of a filamentary path spanning the insulator. Beyond this point, the filament widens keeping the voltage drop across its extremes constant. The consequence of disregarding this effect is clearly distinguishable in the simulated curves: progressive openings of the on-state windows for both positive and negative voltages instead of abrupt ones. In this paper, a modification is introduced in the original memdiode model for memristive devices in order to account for this remarkable feature. Ta2O5-based CRS devices are considered to demonstrate the suitability of our approach. [ABSTRACT FROM AUTHOR]

Silicon carbide (4H-SiC) devices experiencing avalanche conditions can reach temperatures above 1500 K. Simulation of impact ionization in devices should, therefore, include models valid up to such high temperatures. However, calibrations of impact ionization coefficients are available only up to 580 K, and simulations of switching show deviations from measurements at higher temperatures. In this paper, a more accurate model based on the underlying physics of high temperature and anisotropic avalanche generation is proposed. This model enables calibrations performed at room temperature along the ${c}$ -axis to be more precisely extrapolated to any temperature of interest in 2-D device simulations. The model provides an excellent fit to the measurements of breakdown voltages during unclamped inductive switching tests of power MOSFETs, enabling a more accurate prediction of ruggedness. The more comprehensive physics included in the model makes it also applicable to other wide bandgap semiconductors such as GaN, diamond, and Ga2O3, which also exhibit a high critical electric field. [ABSTRACT FROM AUTHOR]

In this paper, we develop an accurate analytical electrostatic potential model for both the n-type and p-type double-gate heterostructure tunnel field-effect transistors (H-TFETs). We solve the Poisson’s equation in four distinct regions inside the device, the depletion regions of the source, channel, and drain, and the drift-diffusion region of the channel, where the mobile charge carriers should be taken into account. It is shown that the model predicts the electrostatic potential profile of the various heterostructure devices with different material systems in all regions of the device operation accurately. The potential model is used for developing a model for the tunneling distance at the given energy level. Due to the physical nature of the models, the influence of the transistor parameters on the electrostatic characteristics of H-TFETs with desired heterojunction materials may be easily pursued. We show that the model results accurately predict the numerical simulation results for different device parameters. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the relationship between size, shape, and the performance of the voltage-controlled magnetic anisotropy (VCMA)-based magnetic tunnel junctions (MTJs) suitable for gigabit scale MRAMs with 10 years of retention time. A Fokker–Planck simulation framework is developed to model the magnetization dynamics in the presence of thermal noise. Here, we numerically show that the optimization of the MTJ geometry can significantly improve the performance of the VCMA-based MTJs. Using an elliptical MTJ with aspect ratio (AR) of 3 reduces the required supply voltage and energy consumption by 80.7% and 92%, respectively, compared to a circular MTJ when the minimum feature size is 50 nm. The design requirements on the VCMA coefficient, ${\xi }$ , are also reduced by 67%. However, the influence of AR is observed to diminish with reduction in the minimum feature size of the MTJ. For instance, when the minimum feature size is 20 nm, the required supply voltage and energy consumption reduce only by 60.29% and 65.30%, respectively. We, then, perform a comprehensive scaling analysis on the VCMA-based MTJs by varying size, geometry, and ${\xi }$ of the MTJs. The predicted scaling trends are then compared with those of the STT MTJs. [ABSTRACT FROM AUTHOR]

A turn-OFF transient analysis of the superjunction (SJ) insulated-gate bipolar transistor (IGBT) based on an analytical model as a function of structural parameters is presented in this paper. The physical phenomenon dependent on the doping density of the n-/p-pillar of the SJ IGBT could be explained using the analytical model to predict the static and transient characteristics. From this model, tradeoff between turn-OFF loss and ON-state voltage has been obtained, as verified by the TCAD simulations with a good agreement. [ABSTRACT FROM AUTHOR]

Considering the demand of III–V multigate (MUG) transistors for next-generation CMOS technologies, a compact model is required to test their performance in different circuits. The low effective mass and highly confined geometry of these MUG devices demand the use of computationally expensive coupled Poisson–Schrödinger (PS) solver for terminal charges and surface potential. In this paper, we propose an approximation, which decouples the PS equations and enables the development of a computationally efficient analytical model. The surface potential and semiconductor charge equations for III–V low effective mass channel cylindrical nanowire (NW) transistors are derived using the proposed approximation. The proposed model is physics-based and does not include any empirical parameters. The accuracy of the model is verified across NWs of different sizes and materials using the data from the 2-D PS solver and found to be accurate. [ABSTRACT FROM AUTHOR]

This paper presents the derivation of a compact dc modeling approach for the band-to-band tunneling current in double-gate tunnel-field effect transistors (TFETs). The physics-based model equations are solved in closed form by including 2-D effects and are implemented in the hardware description language Verilog-A. The verification of the model is done in two steps. First, the modeling approach is verified by TCAD Sentaurus simulation data of the band diagram, the transfer current, and the output current characteristics as well as the output conductance. The modeling results show a good agreement with the TCAD data. Then, measurement data of complementary nanowire gate-all-around TFET devices are utilized to verify the model and to show possible fields of application. As a part of the verification, the benefits and limitations are analyzed and discussed. The numerical stability and flexibility of the model are pointed out by performing simulations of a single-stage TFET inverter. [ABSTRACT FROM AUTHOR]

In modern electronic devices, a variety of novel materials have been introduced such as transition metal oxides, chalcogenides, ferroelectric, and magnetic materials. The electrical response of such materials, used also as active layers, is strongly affected by atomic defects, which affect device performances, variability, and reliability. Extracting the defect properties (i.e., density, energy, and atomic nature) is, thus, crucial to both engineer the performances of electron devices and correctly project their scaling potential and reliability. In this paper, we propose a simple method to extract the atomic properties of defects from the thermal activation energy of the leakage current using a charge trapping relaxation model. [ABSTRACT FROM AUTHOR]

In this paper, a universal analytical current model for a double-gate Si-based tunnel field-effect transistor (TFET) is presented considering the effects of charges in source depletion region and channel. An accurate surface potential model is developed first by solving the pseudo-2-D Poisson equations in the depletion regions, and then is used to calculate the drain tunneling current. The modeling results match well with that obtained from the Technology computer-aided design simulations under various biasing conditions, which indicate that the analytical current model would be very helpful for the further TFET-based circuits design. Furthermore, the influence of the source depletion is also studied, and the presented model with considering the source depletion region and the channel inversion charges is proved to be much more accurate than that ignoring the source depletion. [ABSTRACT FROM AUTHOR]

An analytical surface-potential-based drain current model of dynamic-depletion (DD) polysilicon (poly-Si) thin-film transistors (TFTs) is proposed in this paper. In the 1-D Poisson equation, total charge density is reformulated by an effective charge density, which allows a closed-form surface potential calculation scheme. Different boundary conditions between partial depletion and full depletion are calculated and unified into one back-gate potential in the DD mode, which allows a unified-form surface potential calculation scheme. Combining with Gauss’s theory, we explicitly solve a closed- and unified-form surface potential of DD poly-Si TFTs. Based on the solution of the surface potential, the drain current is derived analytically from the Pao–Sah integration. Furthermore, our solution is verified by numerical results and experimental data, respectively. As a result, such a model can accurately predict I–V characteristics of DD poly-Si TFTs and provide computational efficiency for TFT process optimization and circuit simulations. [ABSTRACT FROM AUTHOR]

The inclusion of quantum effects in the transport direction plays an important role in the extensive research of ultrascaled electronic devices. In this context, it is necessary to study how these phenomena affect different technological architectures in order to conclude which one can be the best candidate to replace standard technology. This paper presents the implementation of direct source-to-drain tunneling effect in a multisubband ensemble Monte Carlo simulator showing its influence in different structures such as fully depleted silicon-on-insulator, double-gate silicon-on-insulator, and FinFET devices. The differences in the potential profile and the electron distribution in the subbands for these architectures modify the number of electrons affected by this quantum mechanism and, therefore, their short-channel behavior. [ABSTRACT FROM AUTHOR]

With the aid of an analytical and general model, this paper investigates the intrinsic difference in the negative-capacitance (NC) effect and design space between semiconductor-on-insulator (SOI) and double-gate (DG) metal–ferroelectric–insulator–semiconductor-type NC field-effect transistors (NCFETs) with a 2-D semiconducting transition-metal-dichalcogenide channel (2-D NCFET). By examining the distributions of internal charge, voltage gain, and capacitance matching over the whole bias range, the intrinsic difference in NC effects between these two topologies is pointed out and explained. Our study indicates that for an intrinsic DG 2-D NCFET, it is difficult to achieve sub-2.3 kT/q average subthreshold swing (SS). By contrast, the bias-dependent subthreshold internal charge and larger curvature of ferroelectric capacitance due to the independent backgate in the SOI 2-D NCFET enable larger design space and sub-2.3 kT/q average SS, making it more suitable for low-power applications. [ABSTRACT FROM AUTHOR]

The field-plate (FP) technique suppresses the electric field crowding at the p-n junction by inducing the interface charges in the drift region. However, due to the modeling difficulty, the physical meaning cannot be elaborated via the conventional 2-D methods, not to mention the designing optimization. Therefore, the FP assistant reduced surface field effective concentration profile (ECP) is proposed in this paper to explore the physical insight of the FP assistant 2-D coupling. The ECP simplifies the sophisticated 2-D coupling by equating the FP assistant effect to the variation of the ECP. As a result, a simple and effective 1-D analytical model is presented to qualitatively and quantitatively explore the FP-induced surface field reshaping and its distinctive breakdown mechanism. The analytical solutions are found out to be consistent with the simulation results obtained from MEDICI, a commercial TCAD tool. [ABSTRACT FROM AUTHOR]

This paper describes a robust, modular, and physics-based circuit framework to model the conventional and emerging magnetic tunnel junction (MTJ) devices. Magnetization dynamics are described by the stochastic Landau–Lifshitz–Gilbert (sLLG) equation whose results are rigorously benchmarked with a Fokker–Planck equation description of the magnet dynamics. We then show how sLLG is coupled to the transport equations of MTJ-based devices in a unified circuit platform. Step by step, we illustrate how the physics-based MTJ model can be extended to include different spintronics phenomena, including spin-transfer torque, voltage-controlled magnetic anisotropy (VCMA), and spin–orbit torque phenomena by the experimentally benchmarked examples. To demonstrate how our approach can be used in the exploration of novel MTJ-based devices, we present a recently proposed MEMS resonator-driven spin-torque nano-oscillator (STNO) that can reduce the phase noise of STNOs. We briefly elaborate on the use of our framework beyond conventional devices. [ABSTRACT FROM AUTHOR]

In this paper, a new continuous multilevel compact model for phase-change memory (PCM) is proposed. It is based on the modified rate equations with the introduction of a variable related to material melting. The model is evaluated using a large set of dynamic measurements and shows a good accuracy with a single model card. All fitting parameters are discussed, and their impacts are detailed. Full circuit simulation is performed. Good convergence and fast simulation time suggest that this new compact model can be exploited for PCM circuit design. [ABSTRACT FROM AUTHOR]

Due to the significance of electron and heat transfer in designing the nanoscale semiconductor devices, the transient analysis of electrothermal properties has attracted extensive attention. In this paper, the density-gradient and dual-phase-lag (DPL) equations are first combined to predict the electron and heat transport in nanoscale transistors. The DPL equation is solved with the consideration of the temperature jump boundary condition that dealing with phonon–wall collisions. We have shown that the temporal and spatial distributions of related physical variables can be obtained by self-consistently solving these equations. Furthermore, the spectral element time-domain method is used to discretize these equations. Numerical results of electrothermal properties for both 2-D and 3-D field-effect transistors have been demonstrated to show the robustness and universality of the proposed model. Therefore, the model we proposed can be used with the temporal and spatial distributions, which could be helpful for evaluating the electrothermal performance and computational designing of nanoscale transistors. [ABSTRACT FROM AUTHOR]

This paper presents a generalization of the charge-based model for ultrathin junctionless double-gate (JLDG) field-effect transistors (FETs) by including quantum electron density. The analytical derivation relies on a first-order correction to the infinite quantum well. When restricting the analysis to the first and second quantized states, the free carrier charge distribution and the current in an ultrathin body JLDG FETs are in agreement with numerical TCAD simulations in all the regions of operation, i.e., from deep depletion to accumulation and from linear to saturation. [ABSTRACT FROM AUTHOR]

This paper reports on the suppression of single-transistor latch, an extreme condition of impact ionization (I.I.), in n-type double-gate germanium (Ge) junctionless (JL) transistors. It is shown that JL transistors can be latched to the on-state due to an increase in the I.I. generated power per unit volume with an increase in drain bias, film thickness, oxide thickness, and doping. Latch, being detrimental to switching, can be effectively suppressed by applying an appropriate negative (positive) back-gate bias for n-type (p-type) JL MOSFET. The independent gate operation with appropriate back bias allows the device to overcome latching and regain switching action with a subthreshold swing (${S}$ -swing) <10 mV/decade at room temperature. The work showcases the limit imposed on back bias due to an increase in off-state current due to band-to-band tunneling along with the utility of sidewall spacer to effectively suppress the same. We also show the tunability of hysteresis using back-gate bias. The work highlights a systematic methodology to eliminate single-transistor latch while preserving sub-60 mV/decade switching in Ge JL MOSFETs. [ABSTRACT FROM AUTHOR]

Silicon-on-insulator (SoI) technology has been reported as a technique to improve electrical characteristics over those of bulk MOSFETs. However, this approach results in the disadvantage of increased drain-induced barrier lowering (DIBL) due to drain electric flux (or field) passing through the buried oxide (BOX) layer. Against such a background, the development of a method to easily estimate the amount of this electric flux is expected to support the prediction of BOX-related DIBL. This paper involved the investigation of a model-derived analytically using conformal mapping techniques to represent the amount of flux in subthreshold regions of ground-plane SoI MOSFETs. To create the model, this paper was divided into two parts. In Part I, as preparation for model development, the relationships between coordinates in MOSFETs and potential/stream function were derived using conformal mapping, and related validity was verified. In Part II, the model’s development was considered based on these relationships, and its validity was also verified. [ABSTRACT FROM PUBLISHER]

This paper presents the quantum analytical model, based on the self-consistent solution of 1-D Schrödinger equation and 2-D Poisson’s equation for the ultrascaled dual-material double-gate (DMDG) silicon-on-nothing MOSFET structure. The quantum mechanical effects (QMEs) have been incorporated in our model to derive the analytical current expressions for the first time ever. Extensive calculations have been carried out to analyze the QMEs on such device performance parameters, like electric field, transconductance, drain conductance, and voltage gain. A comparative analysis based on the drain current has been presented in this paper for the classical and for the quantum model. The authenticity of our proposed quantum model for the DMDG structure is verified by the agreement among the results obtained from the analytical model as well as simulations. [ABSTRACT FROM AUTHOR]

The double-gate (DG) junction field-effect transistor (JFET) is a classical electron device, with a simple structure that presents many advantages in terms of not only device fabrication but also its operation. The device has been largely used in low-noise applications, but also more recently, in power electronics. Physics-based compact models for JFETs, contrary to MOSFETs, are, however, scarce. In this paper, an analytical, charge-based model is established for the mobile charges, drain current, and transconductances of symmetric DG JFETs, covering all regions of device operation. The model is unified and continuous from subthreshold to linear and saturation operation and is valid over a large temperature range. This charge-based model constitutes the basis of a full compact model of the DG JFET. [ABSTRACT FROM AUTHOR]

In this paper, subthreshold channel potential, current, swing, threshold voltage, and drain-induced barrier lowering models of short-channel tri-gate junctionless field-effect transistors are presented. The models incorporate the effects of both substrate-induced surface potential and variable edges of channel. The quasi-3-D approach is used for the modeling of minimum of channel potential that is subsequently used in the drift–diffusion equation to obtain the current expression in subthreshold regime. Threshold voltage and subthreshold swing models are also based on the minimum of channel potential. The analytical results are compared with the simulation data obtained using 3-D visual TCAD device simulator from Cogenda Pvt., Ltd. [ABSTRACT FROM AUTHOR]

Characteristics of deep-ultraviolet (DUV) light-emitting diodes (LEDs) are investigated. DUV LEDs possess severe electron current leakage due to insufficient carrier confinement of the active region. Simply increasing the Al composition of quantum barriers (QBs) or electron-blocking layer (EBL) to enlarge the relevant potential barrier height would arise unexpected detrimental effects, such as extra polarization effect or more obstruction for hole injection. In this paper, band-engineered composition-graded QBs and EBL are proposed to resolve this issue. Simulation results show that, with appropriate designs, the leakage current of DUV LEDs could be effectively diminished with just slight side effects. [ABSTRACT FROM AUTHOR]

The lack of terahertz sources, especially the high-power ones, is one of the main obstacles in the developments of terahertz science and technology. A gyrotron, based on the electron cyclotron masers, is one of the most promising sources to generate high-power terahertz radiation. Therefore, a 0.42-THz gyrotron with a gradually tapered complex cavity operating at the second harmonic is designed and experimentally tested in this paper. Experimental results show that the designed gyrotron can generate high-power THz radiation of 19.2 kW at 0.42 THz with the beam voltage V0 of 51 kV, beam current I0 of 4.4 A and the external magnetic field B0 of 8.03 T, corresponding to an efficiency of 8.6%. By comparison with theoretical results, it can be shown that the operating mode in the designed gyrotron is confirmed as the TE17.4 mode. At the same time, the excitation of the fundamental TE0.5 mode is also observed in the experiment when the beam current is increased to 7.3 A, where the operating frequency is 216.143 GHz. Through extensive experimental efforts, it is found that the designed gyrotron can operate stably at the desired TE17.4 mode when the beam current is in the range of 3-7 A. [ABSTRACT FROM AUTHOR]

In this paper, a 2-D analytical model for surface potential and threshold voltage of novel vertical super-thin body (VSTB) FET has been derived by solving 2-D Poisson equation. The analytical surface potential expression for gate-side surface and sidewall side surface has been modeled using parabolic surface potential approximation. The threshold voltage model for the VSTB FET has been derived by applying strong inversion criterion at the surface potential minimum value. The threshold voltage model for the VSTB FET has been analyzed by varying the body thickness, oxide thickness, and channel doping concentrations. The drain-induced barrier lowering and threshold voltage roll-off parameters are also extracted and analyzed for different body thicknesses. The models for surface potential and threshold voltage have been compared with the results obtained from the 2-D numerical device simulator and a very good agreement between the two has been observed. [ABSTRACT FROM AUTHOR]

A physics-based compact model for double-gate polysilicon thin-film transistors (TFTs) with a doped channel is proposed in this paper. Through the effective charge density approach, the electrostatic potential is solved explicitly from the Poisson’s equation without using the conventional regional approach. The resulting single-piece electrostatic potential equation, which does not consist of the intermediate parameter, offers clear physics meaning and good accuracy, particular when the TFT operates in the transition region. The TFT’s drain current model is then developed by integrating the electrostatic potential equation analytically with the Pao-Sah equation. Finally, the model is verified by numerical and experimental data. Such a compact model is highly suitable for circuit simulations. [ABSTRACT FROM PUBLISHER]

Formulation of accurate yet computationally efficient surface potential equation (SPE) is the fundamental step toward developing compact models for low effective mass channel quantum well MOSFETs. In this paper, we propose a new SPE for such devices considering multisubband electron occupancy and oxide thickness asymmetry. Unlike the previous attempts, here, we adopt purely physical modeling approaches (such as without mixing the solutions from finite and infinite potential wells or using any empirical model parameter), while preserving the mathematical complexity almost at the same level. Gate capacitances calculated from the proposed SPE are shown to be in good agreement with numerical device simulation for wide range of channel thickness, effective mass, oxide thickness asymmetry, and bias voltages. [ABSTRACT FROM AUTHOR]

This paper proposes an analytical threshold voltage model for the dielectric pocket double gate (DP-DG) junctionless FETs (JLFETs). The channel potential function has been obtained by solving 2-D Poisson’s equation using an evanescent mode analysis with suitable boundary conditions. The potential function has then been used for modeling the threshold voltage to investigate the effects of the DP thickness and length on the short-channel effects of the structure. The effects of source and drain depletion regions have been included for improving the accuracy of the model. The model results of DP-DG JLFETs have been compared with the simulation data obtained from the 2-D TCAD ATLAS device simulator. [ABSTRACT FROM AUTHOR]

In this paper, we present a compact model for surface potential and drain current in transition metal dichalcogenide (TMD) channel material-based n-type and p-type FETs. The model considers 2-D density of states and Fermi–Dirac statistics along with drift-diffusion transport model and includes velocity saturation and trap state effects. The developed model has been implemented in Verilog-A and is applicable for symmetric double gate as well as top-gated TMD-on-insulator FETs. The presented model is extensively validated with simulation as well as experimental data for different TMD materials-based FETs and shows excellent agreement with both the simulation and the experimental data. We further validate the model at circuit level using experimental data of MoS2 FET-based inverter. [ABSTRACT FROM AUTHOR]

This paper presents an analytical model of drain current in a silicon tunnel FET with a circular gate (CG TFET). The method involves the bifurcation of the complete geometry into a rectangular gate conventional TFET, and the CG TFET itself based on the number of solvable regions of the CG TFET. The 2-D Poisson equation is solved on the regions of focus of each structure, and both the substructures are mathematically connected through conditions of continuity to arrive at the solution for the original geometry. The effect of the circular gate is considered by segregating the circular region into a number of rectangular segments, and solving the Poisson equation on each of them. The model takes into account the effect of drain on channel potential, bandgap narrowing, and quantum correction. The model is validated by comparing the results with outputs from a TCAD simulation tool. [ABSTRACT FROM PUBLISHER]

An amorphous indium–tin–zinc-oxide thin-film transistor (a-ITZO TFT)-based voltage-mode active pixel sensor (V-APS) is discussed, for the first time, in this paper. The a-ITZO TFT shows superior electrical characteristics, including a high field-effect mobility ( \mu \mathrm {\mathbf {EFF}} > 30 cm2/ \text V\cdot \text s ), a steep subthreshold slope (SS < 200 mV/decade), and a low OFF-current ( I\mathrm{\scriptscriptstyle OFF} < 10^{-14} A), that are suitable for applications such as X-ray imagers. The proposed V-APS is based on the top-illuminated organic photodiode (OPD) or amorphous silicon p+-i-n+ photodiode (a-Si p+-i-n+ PD). Simulation results indicate that, in contrast with common source V-APS, source follower (SF) V-APS is more desirable for X-ray imagers due to its better linearity property. The OPD or the a-Si p+-i-n+ PD does not affect the voltage gain of SF V-APS. But the PDs have different influences on charge-to-voltage conversion gain. The impact of PD capacitances and dark saturation currents on detectable quantities of electrons is also investigated. The influence of the TFT threshold voltage shift on circuit performance, sensitivity, and noise analysis of SF V-APS is discussed. [ABSTRACT FROM PUBLISHER]

In this paper, we have proposed a new analytical model for FETs working in the quasi-ballistic regime. The model is based on a calculation of the charge density along the channel which is then used to solve Poisson’s equation to get the variation of the channel potential. This is then used to calculate the ballistic and drift-diffusive components of the current. The model is capable of accurately predicting the terminal $I$ – $V$ characteristics for all drain and gate biases and includes short-channel effects. It takes length scaling into account and can be used for the full range of devices starting from complete drift diffusive to completely ballistic. The model has been verified with data for high electron mobility transistors (degenerate) and common multigate and nanowire FETs (nondegenerate) proving its ability to take different geometries into consideration. It can be easily implemented as a compact model and used for SPICE circuit simulations. [ABSTRACT FROM AUTHOR]

The effect of voltage on the anisotropy of a magnetic tunnel junction (MTJ) is of substantial interest for low-power nonvolatile memory applications. In this paper, we develop a device-to-bit-cell level simulation framework for voltage-assisted switching of the MTJs, which can satisfactorily reproduce the published experimental data. Our simulation framework is based on a coupled Landau–Lifshitz–Gilbert–Slonczewski equation and nonequilibrium greens function formalism. Using this simulation framework, we investigate the effect of scaling the oxide thickness of an MTJ to enhance the electric field effect. Although it seems attractive for an isolated device, yet, in a bit-cell configuration, reducing the oxide thickness leads to an increase in the supply voltage. In addition, we demonstrate that the unipolar characteristic of the voltage-assisted switching leads to write failures depending on the initial state stored in the MTJ. We, therefore, suggest a read before write scheme exhibiting approximately $2\times $ improvement in the write energy consumption at a bit-cell level compared with a standard STT-MRAM for iso-oxide thickness. However, the latency overhead associated with voltage-assisted MTJs results in a $1.55\times $ degradation of the write speed. Moreover, our layout analysis indicates that the bit-cell area reduction is constrained by the metal pitch, in spite of smaller access transistors. [ABSTRACT FROM AUTHOR]

In this paper, we present an analytical model for the drain current of a double-gate tunnel field-effect transistor (DGTFET), derived using the pseudo-2-D Poisson’s equation in order to obtain the surface potential in both the channel and the source regions. We have proposed a new model for the surface potential when the channel is under accumulation, and have analytically modeled source depletion as well. We have also proposed a modification in the existing model for the band-to-band tunneling, by taking into account the change in the carrier momentum vector during its transit from the source valence band to the channel conduction band. Another important contribution of our work is the prediction of zero drain current at zero drain bias, which is physically modeled for the first time. The negative conductance region for low gate bias is also modeled for the first time using an empirical formulation, without using any fitting parameter. Extensive TCAD simulations were performed in order to prove the veracity of our model with respect to drain bias, gate bias, substrate doping, and metal work function, and the match of our model results with the simulated data was found to be excellent. [ABSTRACT FROM PUBLISHER]

This paper presents new work regimes accompanied by specific conduction models of an SOI nanotransistor with a vacuum cavity. The tunneling mechanisms are separately explored to find out the dominant mechanism. Afterward, the simulations show for the first time two firms on and off states under the gate command. Strong and weak tunneling regimes are emphasized. For the first time, a quasi-saturation region of the ID – V\mathrm {\mathrm {DS}} curves is obtained for V\mathrm {\mathrm {DS}}> 6 V. Different device structures are compared. The best configuration has the swing of 290 mV/decade, threshold voltage of −0.5 V and maximum I\mathrm{\scriptscriptstyle ON}/I\mathrm{\scriptscriptstyle OFF} ratio of 10^\mathrm \mathrm 10 , which is a real gain among the vacuum transistors. Some applications as vacuum diode, switch under the gate command or action as parasitic device are emphasized. [ABSTRACT FROM PUBLISHER]

This paper presents a systematic analytical model development for a sub-45-nm gate length double gate tunnel FET (DG TFET) and assessment of the tunneling current based on classical model under asymmetric circumstances with the ambipolar characteristic. Performance analysis of the tunneling current for a sub-45-nm gate length TFET is performed using Kane’s model by considering high doping in the source and drain regions keeping the channel region low doped. The model explains the variation of tunneling current with the change in oxide thickness under symmetric front and back gate voltages with 5 eV metal work function. The variation in tunnel current is also analyzed for the change in channel thickness under symmetric front and back gate voltages for symmetric oxide thickness. The increase in tunneling current for channel thickness scaling under asymmetric operation of the DG TFET is also efficiently captured by the developed model. The model is compared and verified with Sentaurus TCAD for all bias conditions and good agreement has been achieved. [ABSTRACT FROM PUBLISHER]

In this paper, we have developed a model for the surface potential and the drain current of a dual-material double-gate (DMDG) junctionless FET (JLFET) transistor. A finite-differentiation method has been used to decompose the 2-D Poisson’s equation into two 1-D equations, which allows the modeling of the DMDG structure as two individual single-material double-gate JLFETs. The two 1-D models are then combined using appropriate boundary conditions to provide a simple solution to the complex 2-D Poisson’s equation. The proposed model has been verified for different values of doping concentration ( ND ), oxide thickness ( T\mathrm{ ox} ), and channel thickness ( T\mathrm{ si} ) against the numerical simulations. [ABSTRACT FROM AUTHOR]

This paper proposes an analytical 2-D model for the channel potential and threshold voltage of double-gate junctionless FETs with a vertical Gaussian-like doping profile. The 2-D Poisson equation has been solved by using the evanescent-mode analysis to obtain the potential distribution function in the channel. The position of the conduction path also has been modeled to calculate the potential at different positions of the conduction path. The validity of the proposed 2-D potential and threshold voltage models is shown by comparing the results with the simulation data obtained by a 2-D TCAD ATLAS device simulator. [ABSTRACT FROM AUTHOR]

The optimization methodology of the minimum specific ON-resistance R\mathrm{\scriptscriptstyle ON,\textrm {min}} for the lateral superjunction device is proposed based on the concepts of charge and potential electric fields in this paper. From the R\mathrm{\scriptscriptstyle ON,\textrm {min}} method, a new relationship between R\mathrm{\scriptscriptstyle ON} and breakdown voltage VB is developed, and the analytical formulas are obtained to directly give the doping concentration $N$ and the drift length L_{d} . The calculated results, including the 800 and 1600 V examples, are in good agreement with the simulations. The optimized designs are also compared with the existing experimental and simulated data. It is shown that R\mathrm{\scriptscriptstyle ON} from the proposed optimization method is minimum, and the methodology of R\mathrm{\scriptscriptstyle ON,\textrm {min}} is universal. [ABSTRACT FROM AUTHOR]

In this paper, an analytical potential-based model in the subthreshold regime for short-channel junctionless cylindrical surrounding-gate MOSFETs is proposed as the source/drain depletion effect considered. The threshold voltage ( V\textrm {th} ), subthreshold slope, and drain-induced barrier lowering are also correspondingly derived, which give explicit explanations of the short-channel effects on junctionless MOSFETs in the subthreshold regime. The compact model is verified by the numerical simulation, and the results match well. [ABSTRACT FROM AUTHOR]