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The introduction of metal nanocrystals (NCs) has been confirmed to improve electrical uniformity of oxide-based resistive random access memory (RRAM) devices significantly; however, the current reports do not systematically elucidate the relationship between the size/distribution of NCs and the electrical uniformity of RRAM devices. In this paper, we focused on the impact of metal NCs size and areal density on the resistive switching (RS) performances of oxide RRAM by atomic layer deposition (ALD) based on the experimental results and theoretical calculation. The dependence of ALD cycles of 50–130 during Pt or CoPtx NCs growth on the RS parameters of Al2O3 or HfO2 memory units has been evaluated systematically. The RRAM embedded Pt or CoPtx NCs shows the trends: with increasing ALD cycles, the forming voltage, set/reset voltage, the resistance in off and on state, and ${R}_{ \mathrm{\scriptscriptstyle OFF}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$ ratio entirely first decrease, then flatten, and increase later with a minimum value at about 100 cycles. Although all metal NCs with various sizes enhance the electric field strength compared to at the planar region, only metal NCs with proper NCs size and areal density (9 nm/6– $10\times 10^{\textsf {11}}$ /cm2 in this paper) can effectively produce stronger localized electric field at the tip of metal NCs, leading to optimal RS behavior. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate a tunable Schottky diode based on amorphous indium–gallium–zinc–oxide (a-IGZO) film with high performance for rectifying circuit and bipolar one diode-one resistor (1D1R) crossbar applications. By modulating the oxygen content in the a-IGZO film, the device shows adjustable behavior. Under the high oxygen content condition, the device displays outstanding diode features with a large rectification ratio up to 108 at ±1 V and a high forward current density of 100 A/cm2 at ±1 V when used Cu as the top electrode. The thermionic emission model is proposed to explain the Schottky diode behavior. And by utilizing the superior rectifying performance, we successfully demonstrate the dynamic rectifying application. In addition, we combine the optimized Schottky diode device with the bipolar-type resistive random access memory (RRAM) device to investigate the Schottky diode device in 1D1R crossbar application. As a result of its tunable nature and low processing temperature, the a-IGZO Schottky diode is a promising element for rectifying circuit and bipolar 1D1R crossbar applications. [ABSTRACT FROM AUTHOR]

In this paper, the transition rate (TR) from the high-resistance state to the low-resistance state of a HfO2-based resistive random access memory (RRAM) is investigated. The TR is statistically characterized by applying constant voltage stresses in the range from 0.45 to 0.65 V. It is found that TR follows a voltage dependence which closely resembles the one exhibited by metal-insulator-semiconductor / metal-insulator-metal structures when subjected to constant voltage stress, but with remarkably different fitting parameters. This result suggests a common underlying mechanism in both evolutionary behaviors. Furthermore, the investigation provides additional evidence supporting the micro-structural changes in the oxide after the forming step as well as the role played by the atomic species during the SET event. [ABSTRACT FROM AUTHOR]

This paper addresses the design challenges of simulating the 3-D vertical-resistive random access memory (V-RRAM) toward MB-level. The interconnect IR drop and sneak paths are known to be the limiting factors for building large-scale V-RRAM arrays. The previous approach to evaluate the write/read margin of V-RRAM was based on the exhaustive SPICE simulations, which prohibits the design exploration to MB-level as it takes huge amount of computation resources. In this paper, a quasi-analytical model is proposed, which aims to reduce the simulation time and the required memory usage. Through the validation with the SPICE simulation results, the proposed model shows a similar accuracy. Based on the proposed quasi-analytical model, the worst case data pattern of 3-D V-RRAM with large array size up to 4 MB is analyzed. The results show that it is more efficient to increase the number of stack layers than expanding the horizontal array size to achieve large subarray size. [ABSTRACT FROM AUTHOR]

This paper investigates material modifications induced by cosputtering indium-tin oxide (ITO) with gadolinium (Gd) at two different power levels. In addition, resistance switching (RS) properties were also verified for use as an insulator in resistive random access memory (RRAM). Comparison of scanning electron microscope (SEM) measurements for the two different cosputtering powers indicated significant changes of the ITO surface. Transparency was also verified by an N&K analyzer measurement, with results indicating a constant in transparency induced by the lower power Gd doping, indicating potential for transparent applications. Furthermore, the mole fraction ratio defined by X-ray photoelectron spectroscopy reveals a Gd2O3 peak, a likely reason for the ITO thin film becoming less conductive. This ITO/Gd:ITO/TiN RRAM can exhibit stable and robust RS characteristics at a lower forming voltage. In addition, lower operating voltages, including both SET and RESET voltages, can be obtained. Reliability tests including endurance and retention were carried out to confirm its RS stability. The RS mechanism of this ITO/Gd:ITO/TiN device was also investigated with the current–voltage (${I}$ – ${V}$) fitting method. Moreover, temperature effects were also applied to verify the high-resistance state (HRS) mechanism. Finally, a conduction model was proposed to clarify the RS characteristics and confirm that the ITO/Gd:ITO/TiN device is appropriate for data storage. [ABSTRACT FROM AUTHOR]

This paper investigates the issues of oxygen accumulation and variation in the high-resistance state of HfO2-based resistive random access memory (RRAM), with improvement attained by inserting a thin oxygen-vacancy-rich layer of indium-tin-oxide (ITO) film. By acting as the oxygen ion reservoir, this ITO thin film on the TiN electrode can further stabilize resistance switching (RS) characteristics. In terms of reliability, ac endurance, and retention tests confirm stable RS characteristics for the Pt/HfO2/ITO/TiN device. Finally, a conducting model was proposed to explain the influence of the ITO thin layer and clarify the physical mechanism of electrical improvements. [ABSTRACT FROM AUTHOR]

In this paper, we report about the derivation of a physics-based compact model of random telegraph noise (RTN) in HfO2-based resistive random access memory (RRAM) devices. Starting from the physics of charge transport, which is different in the high resistive states and low resistive states, we explore the mechanisms responsible for RTN exploiting a hybrid approach, based on self-consistent physics simulations and geometrical simplifications. Then, we develop a simple yet effective physics-based compact model of RTN valid in both states, which can be steadily integrated in state-of-the-art RRAM compact models. The RTN compact model predictions are validated by comparison with both a large experimental data set obtained by measuring RRAM devices in different conditions, and data reported in the literature. In addition, we show how the model enables advanced circuit simulations by exploring three different circuits for memory, security, and logic applications. [ABSTRACT FROM AUTHOR]

A versatile multiphysics simulation packet for investigating different resistive random acces memories (RRAMs) is developed in this paper. Heat transfer, electrical conduction, and ion migration in such heterogeneous structure are all taken into consideration. Three fully coupled partial differential equations are solved using our self-developed finite-difference algorithm, where Scharfetter–Gummel method is adopted to simulate ion migration with fast convergence achieved. This packet is validated in comparison with the commercial software based on the finite-element method. With its implementation, complete and clear pictures for crosstalk effect in vertically integrated RRAM are captured and compared, where the effects of key physical and geometrical factors are characterized and understood. Some useful suggestions to mitigate its unfavorable influences are given. [ABSTRACT FROM PUBLISHER]

This paper investigates the characteristics of applying indium–tin oxide (ITO) with and without nitride gas (N2) as the insulator in resistive random access memory (RRAM). After cosputtering an ITO target with N2 as the insulator and capping the same ITO material as the top electrode, the device exhibits rectifier and resistance switching characteristics before and after the forming process, respectively. The Schottky diodelike rectifier mechanism was also verified by various temperature measurements. Furthermore, robust resistance switching at a positive forming voltage, smaller than that required during negative bias forming, can be achieved. Both positive and negative forming processes are examined with current fitting results, which show different dominant mechanisms when using positive or negative biases. All these mechanisms have also been verified by temperature effect experiments, which confirmed the dominant conduction mechanisms. This, in combination with the fact that the positive forming voltage itself is smaller than the negative forming voltage, and decreases with device scale down, provides two highly beneficial results. This good performance achieved by using ITO with N2 suggests significant progress of RRAM and remarkable potential applications. [ABSTRACT FROM PUBLISHER]

A comprehensive physical model on the resistive switching (RS) behaviors of bilayered TaOx-based RS access memory [resistive random access memory (RRAM)] is presented. In the model, the effects of the generation and recombination (G-R) of oxygen vacancies ( $V_{{\rm{O}}}$ ), phase transition (P-T) between Ta2O5 and TaO2, and the interaction (I-A) between Ta2O5 and TaOx layers are involved to explain the RS behaviors based on ab initio calculations. An atomistic Monte Carlo simulation method based on the model is developed to investigate the dynamic physical processes and reproduce the experimental phenomena. The impacts of G-R and P-T as well as the I-A effects on the RS behaviors of a bilayered Ta2O5/TaOx structure and the device performances are identified. This paper indicates that the G-R effect dominates the RS behaviors, and self-compliance is due to the I-A effect. Based on the simulations, the optimization guidance of a bilayered TaOx-based RRAM is presented. [ABSTRACT FROM AUTHOR]

In this paper, we present a compact model for metal–oxide-based resistive random access memory (RRAM) devices with bipolar switching characteristics. The switching mechanism relies on the dynamics of conductive filament growth/dissolution in the oxide layer. Besides the dc and pulsed $I$ – $V$ characteristics, the model also captures the RRAM retention property and the temperature dynamics. The model parameters and the device variations are calibrated from the experimental data of IMEC HfOx-based RRAM devices. The model has been implemented in Verilog-A, which can be easily adapted into the SPICE simulator for the circuit-level analysis. As case studies, we demonstrate the model’s applications on the programming scheme design of the 1-transistor-1-resistor array, as well as the design space exploration of the 1-selector-1-resistor cross-point array toward megabit-level. [ABSTRACT FROM PUBLISHER]

In this paper, we demonstrate three key features of oxide-based nano-oscillators: 1) the observation of threshold switching and filamentary oscillations in TaOx; 2) the highest frequency achieved by oxide-based oscillators; and 3) a study with linear (resistor) and nonlinear (transistor) ballasts to clearly understand the role of filament dynamics in scaling. These oscillators show frequency tunability over the range of 20 kHz–250 MHz, with 250 MHz being the highest reported frequency for this class of oscillators. Different types of ballasts show frequency tunability using two distinct methods: 1) by tuning the channel resistance of the transistor and 2) by increasing the rail voltage across the ballast–device pair. This sheds new light on the oscillator dynamics for dense oscillator arrays aimed at oscillatory neural networks and other applications. [ABSTRACT FROM AUTHOR]

In this paper, the nonlinear switching mechanism of the Ti/HfO2/Al2O3/TiN crossbar structure resistive random access memory device with good reliability is investigated. The nonlinearity of the device can be revealed by inserting a large bandgap of an Al2O3 thin layer between the TiN bottom electrode and the HfO2 switching film. The nonlinear switching mechanism caused by Flower–Nordheim tunneling involves the tunneling barrier of the Al2O3 layer. Besides, the nonlinear behavior is also sensitive to the thickness of the inserting Al2O3 layer. A high nonlinear factor of 37, large endurance more than 10^4 , and good retention properties are achieved in the Ti/HfO2/Al2O3 (1-nm)/TiN structure. [ABSTRACT FROM AUTHOR]

3-D resistive switching random access memory (RRAM) is a promising candidate for high-density nonvolatile memory applications, as well as for monolithic 3-D integration interleaved with logic layers. In this paper, we develop a methodology for assessing and optimizing large-scale 3-D RRAM arrays. A systematic study on the intrinsic switching behaviors and optimization of 3-D RRAM arrays is performed, combining device measurements and 3-D array simulations. The dependence of programming voltage on array size, cell location and pulse parameters, statistical properties of operating 3-D RRAM arrays, and subthreshold disturbance on RRAM cells is experimentally investigated. Optimization guidelines for the performance and reliability of 3-D RRAM arrays from device level to architecture level are presented: 1) an optimized 1/ $n$ architecture for 100-kb 3-D RRAM arrays can improve write margin by 69.6% and reduce energy consumption by 75.6% compared with a conventional full-size array design; 2) a strategy of prioritizing storage location for reliable operation is presented; and 3) an optimal hopping barrier of oxygen ions is found to improve array immunity to disturbance. [ABSTRACT FROM PUBLISHER]

This paper investigates the impact of threshold switching (TS) selector characteristics on the one-selector one-resistor (1S1R) cross-point array performance. TS selector parameter requirements are extracted for 1 Mb array, considering 1S, 1R cell compatibility, read/write margin, and power consumption constraints. The SPICE simulation results show that the threshold voltage ( V\mathrm {\mathbf {th}} ) and the ON-state resistance ( Rs ) are important selector parameters. Low V\mathrm {\mathbf {th}} eliminates 1R disturb issue during the read operation, but this comes at the expense of losing full cell nonlinearity (NL) during the write operation. Increase of V\mathrm {\mathbf {th}} and Rs improves the full cell NL and alleviate read disturb issue. However, these reduce 1S1R read window and additional voltages are required for both read and write operations. Compared with selector with nonabrupt current-voltage ( $I$ – $V$ ) characteristics, the TS selector is more favorable for the low-voltage operation. Finally, different reported TS selectors are evaluated, and the improvement directions are suggested. [ABSTRACT FROM PUBLISHER]

This paper provides new insights into the effect of device characteristics on multilevel-cell (MLC) operation, aiming at potential benefits, such as the reduction of write latency and peripheral circuit design overhead. A general categorization of the MLC-operating schemes in storage-class memory (SCM) is proposed to connect the total number of write inputs with fundamental device properties. The categorization method is validated using two resistive random access memory devices based on different switching mechanisms. Favorable device characteristics and the corresponding simplified MLC operating schemes are addressed to facilitate future development of MLC SCM. [ABSTRACT FROM AUTHOR]

A model of resistive random access memory (RRAM) cells aimed at providing an optimal programming/erase scheme in which the timing and biasing can be accurately optimized is proposed and implemented. To expedite technology development with an emphasis on ICs, a predictive model to capture the physical operation of every memory cell is needed. Although a number of compact RRAM models have been developed, this paper further considers the time-dependent reset process and the heat transfer in the conductive filaments. These phenomena are becoming critical in scaled memory cells and need to be carefully addressed. Due to the physical nature of the model, model parameters can be straightforwardly calibrated, relying on limited measurement data. The compact model is implemented using Verilog-A, and it is flexible for different circuit simulators. [ABSTRACT FROM PUBLISHER]

The resistive random access memory (RRAM) crossbar array has been extensively studied as one of the most promising candidates for future high-density nonvolatile memory technology. However, some problems caused by circuit and device interaction, such as sneak leakage paths, result in limited array size and large power consumption, which degrade the array performance significantly. Thus, the analysis on circuit and device interaction issue is imperative. In this paper, a simulation method is developed to investigate the critical issues correlated with the interaction between devices and the circuit. The simulations show that a large off/on ratio of resistance states of RRAM is beneficial for large readout margin (i.e., array size). The existence of the selector connected in series with an RRAM device can eliminate the need for high Ron resistance, which is critical for the array consisted of only RRAM cells. The readout margin is more sensitive to the variation of Ron and is determined by the nonlinearity of the I–V characteristics of RRAM, whereas the nonlinear characteristics of the selector device are beneficial for a larger readout margin. An optimal design scheme for turn-on voltage and conductance of the selector is proposed based on the simulation. [ABSTRACT FROM PUBLISHER]

The goal of neuromorphic engineering is to build electronic systems that mimic the ability of the brain to perform fuzzy, fault-tolerant, and stochastic computation, without sacrificing either its space or power efficiency. In this paper, we determine the operating characteristics of novel nanoscale devices that could be used to fabricate such systems. We also compare the performance metrics of a million neuron learning system based on these nanoscale devices with an equivalent implementation that is entirely based on end-of-scaling digital CMOS technology and determine the technology targets to be satisfied by these new devices. We show that neuromorphic systems based on new nanoscale devices can potentially improve density and power consumption by at least a factor of 10, as compared with conventional CMOS implementations. [ABSTRACT FROM AUTHOR]

This paper reports on comprehensive analytical and numerical circuit analyses on the read margin of the one selector–one resistor (1S1R) resistive-switching crossbar array. These analyses are based on the experimental characteristics of the 1S1R cells and provide a valuable insight into their potential for ultrahigh-density data storage. Three read schemes, namely, one bit-line pull-up (One-BLPU), all bit-line pull-up (All-BLPU), and partial bit-line pull-up (Partial-BLPU), are investigated. In contrast to the One-BLPU scheme, the All-BLPU scheme can realize a large crossbar array of 16 Mb, even when the line resistance is nonnegligible because the effective resistance at the sneak current path is substantially less sensitive to the array size. Additionally, the Partial-BLPU scheme can be used to reduce power consumption if random read access is desirable. Finally, the effects of line resistance on the read and write margins are discussed. [ABSTRACT FROM AUTHOR]