Search

Several miniaturized viscometers, or microviscometers, have been developed exploiting numerous rapid prototyping techniques. Among them, paper microstrips, famously known as microfluidic paper-based analytical devices ($\mu $ PADs), have become popular due to their cost-efficacy, simple fabrication, fast response, and easily disposable. Many fabrication methods are existing to develop paper microstrips. Herein, an alternative fabrication method is proposed where fused deposition modeling (FDM)-based 3-D printer (3DP) has been employed using polycaprolactone (PCL) filament. F, image processing has been utilized to measure viscosity in such microfluidic domain. Viscosity was calculated by measuring the time taken by the fluid to cover a fixed length between two spots in the microchannel based on the programed and color-coded regions-of-interest. The image processing program was developed considering the change in the gray scale in the virtual region of interests (ROIs) in the microchannel during the fluid flow in the paper microstrips. A 3-D printed handheld platform, containing raspberry pi with on-board camera and display, was developed to execute the image processing and automate the entire work flow. In the proposed device, the accuracy was measured to be >92%. [ABSTRACT FROM AUTHOR]

We report on investigation of the mechanical properties of paper electronics (printed and made out of paper). One key objective of such paper electronics is to achieve ultraflexibility. Therefore, it is important to understand electrical functionality and reliability of paper electronics under various physical (mechanical) deformations. Here, we show the general mechanical properties of the cellulose paper used and its electrical behavior under applied strain, tackling the main effects that need to be identified when building paper-based systems, from product performance and stability perspective. An overview of the stress–strain behavior of silver ink on paper is discussed, and then, we tackle a more specific analysis of the performance variations of paper sensors made with recyclable household materials when exposed to various mechanical conditions of tensile and compressive bending. This paper is important for developing stable wearable sensors for incorporation into Internet of Everything applications. [ABSTRACT FROM PUBLISHER]

The electrophoretic display (EPD) is the main solution to electronic papers, but most of them can display the image or text in black and white particles only. The users may prefer the EPD showing multiple colors rather than the black/white content only. In this paper, we introduce the driving system for a color EPD, which is composed of three kinds of particles. The system aims at optimizing the visual quality based on a new driving waveform by equipping with an optimization method for color and tone reproduction. The experimental result shows that the proposed EPD driving system can display three-color pictures with promising visual quality. [ABSTRACT FROM AUTHOR]

Describes the above-named upcoming special issue or section. May include topics to be covered or calls for papers. [ABSTRACT FROM AUTHOR]

Describes the above-named upcoming special issue or section. May include topics to be covered or calls for papers. [ABSTRACT FROM AUTHOR]

The article offers information of Technology Computer-Aided Design (TCAD) which refers to the use of computer simulations to develop and optimize semiconductor process technologies and devices.

During the past few years, we have seen an increasing number of submissions of “physics-based simulation only” papers to the IEEE TRANSACTIONS ON ELECTRON DEVICES (T-ED). The popularity of such papers may be explained by the fact that the present widespread technology computer-aided design (TCAD) tools are a significant and welcome boost to creativity in the electronic device community. In fact, TCAD tools allow researchers to explore and optimize device structures without being burdened by technology concerns in terms of availability, cost, and time delay. [ABSTRACT FROM AUTHOR]

This paper provides an industry perspective on the present state of compact models for MOS transistors. It highlights the complexity of layout-dependent effects in modern transistors, reviews some common misunderstandings of MOS transistor capacitances, and introduces a new, structurally symmetric, “gate-as-input” equivalent network for these capacitances. Areas of focus for the future model developments are also proposed. [ABSTRACT FROM AUTHOR]

An introduction is presented in which the editor discusses articles in the issue on topics including IEEE Transactions on Electron Devices on New simulation methodologies for next-generation TCAD tools, and large-scale simulations.

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Since 2017, the IEEE Transactions on Electron Devices (TED) has published a selection of extended versions of papers presented at the Symposia on VLSI Technology and Circuits held in the corresponding years (vol. 64, no. 10; vol. 65, no. 11; vol. 66, no. 12). Since 2018, the papers have been collected in a Special Section of TED titled “Papers from Symposium on VLSI Technology.” This initiative, which was the result of a fruitful cooperation between the Electron Device Society and the VLSI Symposium chairs and committees, has brought to TED a number of carefully selected (by the VLSI TPC first and then through the TED usual review process), high-quality submissions. We have been able to continue this cooperation also in this difficult 2020, and we are therefore happy to announce the publication in the December issue (Vol. 67, No. 12) of a Special Section on papers from the 2020 Symposium, held virtually on June 15–19, 2020. A special thanks to the Guest Editors of the section, Peide Ye, Purdue University (Publication Chair, 2020 VLSI Symposium), and Masaharu Kobayashi, The University of Tokyo, Japan (Publication Co-Chair, 2020 VLSI Symposium). [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

This Special Issue of the IEEE Transactions on Electron Devices will feature the most recent developments and the state of the art in the field of ultra wide band gap semiconductors and devices for power control and conversion, including both experimental results and theoretical developments. Papers must be new and present original material that has not been copyrighted, published or accepted for publications in any other archival publications, that is not currently being considered for publications elsewhere, and that will not be submitted elsewhere while under considerations by the Transactions on Electron Devices. Topics of interest include, but are not limited to: IDtra Wide Band Gap Materials: Advances in material synthesis, defect characterization, transport and high-field properties, and material-level integration; evaluation of fundamental materials-limited figures of merit; Power Devices: Vertical and lateral MOSFETs, HEMTs and MIS-HEMTs, IGBTs, Schottky and pn junction rectifiers, and other device concepts; fabrication and device characterization; designs and device structures for controlling field profiles, edge termination; Thermal Management: Approaches to mitigate thermal effects in power devices using ultra wide band gap materials; Integration: Monolithic and heterogenous integration for system-level applications using ultra wide band gap materials. Integration with Si or other semiconductors for system-on-chip and system-in-package implementations, including heterogenous and package-level integration for high-performance power conversion applications. [ABSTRACT FROM AUTHOR]

Describes the above-named upcoming special issue or section. May include topics to be covered or calls for papers. [ABSTRACT FROM AUTHOR]

This paper reports an industry standard monolithic 555-timer circuit designed and fabricated in the in-house silicon carbide (SiC) low-voltage bipolar technology. This paper demonstrates the 555-timer integrated circuits (ICs) characterization in both astable and monostable modes of operation, with a supply voltage of 15 V over the wide temperature range of 25 °C–500 °C. Nonmonotonic temperature dependence was observed for the 555-timer IC frequency, rise time, fall-time, and power dissipation. [ABSTRACT FROM AUTHOR]

The article highlights call for papers from Ieee Transactions on Electron Devices on several topics including advanced transistors; gate dielectrics; and power devices.

The article invites, papers from authors for a special issue of the journal "IEEE Transactions on Electron Devices" on "Reliability of CMOS Logic, Memory, Power and Beyond CMOS Devices."

The article presents the invitation of the journal to interested individuals to submit papers and articles on memory, logic and CMOS devices.

Describes the above-named upcoming special issue or section. May include topics to be covered or calls for papers. [ABSTRACT FROM AUTHOR]

The article offers information on electronics devices, complementary metal–oxide–semiconductor (CMOS) logic, power and memory. Topics discussed include electronics devices with features related to experimental results and theoretical model; include advanced transitory with features of self-heating effect and variability; and discusses power devices like the metal–oxide–semiconductor field-effect transistor (MOSFET) and insulated-gate bipolar transistor (IGBT).

The article talks about the reliability of electronic devices as an issue for technology, impact of Bias Temperature Instability on CMOS logic devices and evolving Hot Carrier Degradation and Self Heating Effect. It talks about degradation of program window, development in the field of device reliability and topics that includes Advanced Transistors, Gate Dielectrics and Memory Devices.

Flexible, highly sensitive, easy fabricating process, low-cost pressure sensors are the trend for flexible electronic devices. Despite the tremendous progress in recent years, it is still challenging to prepare pressure sensors with high sensitivity, high stability, and fast responsiveness. In this study, we report a simple and low-cost method for the preparation of novel pressure sensors. Inspired by the pomegranate structure, a 3-D porous structure consisting of polystyrene (PS) microspheres filled with reduced graphene oxide (rGO) paper is proposed. This pressure sensor has high linear sensitivity (1.41 kPa−1 in the pressure range of 0–50 kPa), high stability (1000 cycles), and quick response time (~20 ms). Furthermore, a robotic arm interacting control system based on pressure sensor arrays is constructed, which demonstrates the far-reaching potential of pressure sensors in human–machine interaction. Therefore, this work provides a low-cost and effective method for preparing high linear sensitivity pressure sensors. [ABSTRACT FROM AUTHOR]

Describes the above-named upcoming special issue or section. May include topics to be covered or calls for papers. [ABSTRACT FROM AUTHOR]

Describes the above-named upcoming special issue or section. May include topics to be covered or calls for papers. [ABSTRACT FROM AUTHOR]

Describes the above-named upcoming special issue or section. May include topics to be covered or calls for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

We have fabricated fully transparent high performance flexible nickel-doped zinc oxide thin-film transistors (NZO TFTs) on flexible plastic substrates using magnetron sputtering. The effects of active layer thickness on the performance of NZO TFTs was investigated. We found that the channel layer thickness has a notable influence on the characteristics of NZO TFTs. The electrical characteristics of NZO TFTs reached the optimization when the active channel layer thickness was 71 nm, with a low off-current lower than 1 pA, a high on/off drain current ratio of 2.1 \times 10^9 , a high saturation mobility of 27.5 cm ^2\cdot \mathrm V^-1\cdot \mathrm s^-1 , a steeper subthreshold swing of 67 mV/decade, and a low threshold voltage of 1.88 V. It is demonstrated that NZO is a promising active channel layer materials for future transparent flexible displays. [ABSTRACT FROM AUTHOR]

Over the past 10 years, 3-dimensional (3-D) wafer-level stacked backside Illuminated (BSI) CMOS image sensors (CISs) have undergone rapid progress in development and performance and are now in mass production. This review paper covers the key processes and technology components of 3-D integrated BSI devices, as well as results from early devices fabricated and tested in 2007 and 2008. This article is divided into three main sections. covers wafer-level bonding technology. covers the key wafer fabrication process modules for BSI 3-D wafer-level stacking. presents the device results. [ABSTRACT FROM AUTHOR]

We demonstrate that the residual carbon concentration in the drift region can have a significant impact on the reverse leakage, breakdown voltage, and breakdown stability of GaN-on-GaN vertical diodes. Two generations (Gen1, Gen2) of polarization-doped p-n junctions with different C concentrations were compared, in terms of avalanche voltage, avalanche instability, and deep-level concentration. The original results collected within this paper show that: 1) both generations of devices can safely reach the avalanche regime; diodes with a lower residual CN have a higher reverse leakage and a lower avalanche voltage, due to an uneven distribution of the electric field; 2) the presence of residual carbon can lead to breakdown walkout, i.e. a recoverable increase in breakdown voltage under reverse-bias stress. Specifically, devices with higher C concentration show a fully-recoverable breakdown walkout, whereas the breakdown voltage is stable in devices with lower C concentration; and 3) steady-state photocapacitance measurements confirm the presence of CN in both generations, and are used to assess the relative difference in concentration between Gen1 and Gen2, even for levels below secondary ion mass spectroscopy (SIMS) sensitivity. The results described in this paper indicate the existence of a trade-off between breakdown voltage (increasing by improving compensation) and breakdown stability (improving by reducing CN concentration) and are of fundamental importance for the optimization of GaN power devices. [ABSTRACT FROM AUTHOR]

We report in this paper the design and fabrication of single-chip alternating current-LEDs (AC-LEDs) by monolithically integrating, for the first time, high-breakdown Schottky barrier diodes (SBDs) and micro-LED arrays using III-nitride LED epi-wafers of standard specs for volume production. A technique of cyclic mixed-etching has been introduced to restore the surface of inductively coupled-plasma (ICP) etching processed gallium nitride to device quality for fabricating high-breakdown Schottky junctions. Proof-of-concept single-chip AC-LED devices and a prototype driver-free white AC-LED lamp were demonstrated, showing high-efficiency LED emission, high chip area utilization efficiency, low power loss of the on-chip SBD bridge rectifier, and good luminous efficacy of the prototype AC-LED lamp. This paper paves the way toward mass-producing reliable and low-cost driver-free AC-LED lamps for solid-state lighting with existing LED manufacturing infrastructures. [ABSTRACT FROM AUTHOR]

Detailed physics of the third quadrant electrical characteristics of 1.2-kV rated 4H-SiC accumulation (Acc) and inversion (Inv) channel MOSFETs, based on experimentally measured data and TCAD numerical simulations, are described in this paper for the first time. The power MOSFETs with various channel lengths (0.3, 0.5, 0.8, 1.1 $\mu \text{m}$) used in this paper were fabricated in a 6-in commercial foundry. Numerical simulations verified that there are two current paths in the third quadrant: 1) through the base region and 2) through the p-n body diode. This paper demonstrates that the Acc MOSFETs have a smaller third quadrant knee voltage (${V}_{{\text {knee}}})$ of −1.2 V compared with −1.9 V for the Inv MOSFETs (at ${V}_{g} = {0}$ V and room temperature). Numerical simulations show that this difference is due to a smaller potential barrier for electron transport from the drain to the source in the base region for accumulation channel devices than inversion channel devices. Acc devices are shown to have a lower voltage drop in the third quadrant. [ABSTRACT FROM AUTHOR]

High-power, high-frequency gyrotrons are the only promising sources for the electron cyclotron resonance heating and current drive (ECRH&CD) in the present thermonuclear fusion plasma experiments and in future power plants. Compared to the hollow-cavity gyrotron design, the coaxial cavity gyrotron design facilitates improved mode competition control, which eventually increases the output power per tube. At KIT-IHM, the successful operation of a 170-GHz gyrotron has been demonstrated in the short-pulse regime, and the ongoing research activities are aiming to upgrade the existing coaxial cavity gyrotron from short-pulse (1–10 ms) to long-pulse (~ 1s) operation. In this paper, with the help of multiphysics simulations, the performance of the insert cooling system is verified for the continuous wave (CW) operation and the operating limits of the insert cooling systems are determined. The perfectly aligned coaxial Glidcop insert will be able to withstand operating conditions leading to a maximal heat flux of about 0.39 kW/cm2. The influence of insert misalignment on insert loading is also studied systematically in this paper. [ABSTRACT FROM AUTHOR]

In this paper, we present a detailed investigation of the impact of fin width (${w}_{\text {fin}}$) on tri-gate AlGaN/GaN metal–oxide–semiconductor high electron mobility transistors (MOSHEMTs). As ${w}_{\text {fin}}$ is reduced, the threshold voltage (${V}_{\text {TH}}$) increases, which is due to the enhanced gate control (especially for ${w}_{\text {fin}} < {200}$ nm) thanks to the 3-D geometry of the tri-gate, and the reduced carrier concentration (${N}_{\text {s}}$) caused by a more pronounced strain relaxation and sidewall depletion, as explored using Hall and capacitance–voltage (${C}$ – ${V}$) measurements. Normally- OFF operation was achieved for ${w}_{\text {fin}}$ close to the sidewall depletion width (${w}_{\text {dep}}$) of 19.5 nm, since the fin is depleted from its two sidewalls. The impact of ${w}_{\text {fin}}$ on ON-resistance (${R} _{{{ {6{8} {\text {ON}}}}}}$) and current capability (${I} _{\text {D},\text {max}}$) was also investigated, along with the influence of the effective source injection, the trench conduction and the filling factor (FF) on these key characteristics. The degradation caused by the tri-gate fin etching could be fully recovered by increasing the FF. Finally, we show that the tri-gate can reduce gate capacitance (${C}_{\text {G}}$) and charge (${Q}_{\text {G}}$) in normally- ON MOSHEMTs, depending on the design of the tri-gate and the gate voltage (${V}_{\text {G}}$), leading to a smaller ${R}_{{{ {6{8} {\text {ON}}}}}} \cdot {Q}_{\text {G}}$ product that is beneficial for high-frequency switching applications. The results in this paper offer insights into important phenomena in tri-gate GaN devices and are fundamental for the further advance of this technology. [ABSTRACT FROM AUTHOR]

In this paper, a microfluidic device is introduced based on direct current (dc) dielectrophoresis for the separation of circulating tumor cells from normal blood cells. Differential sidewall electrodes are designed inside the channel and two middle-channel outlets are located after the end of the electrodes, which are assigned to collect the normal blood cells. A maximum dc potential of 3 V is applied to the electrodes, resulting in a differential dielectrophoretic forces acting on the cells. This paper involves isolating MCF-7 breast cancer cells from white blood cells (WBCs) and red blood cells (RBCs), eliminating the demand for primary RBC lysis. Numerical simulation results revealed that the differential electrodes not only suppressed successfully the need for high applied voltages by dc dielectrophoresis but also diminished the joule heating effects. Besides that, the arrangement of the differential electrodes was observed to play a critical role in the separation performance. In particular, designing the outlets, as well as adjusting the electrode potentials, has effectively assisted the device to be tunable for different cancer cells even with different radii. More strikingly, the ability of the device to deflect the waste cells (WBCs and RBCs) to out of the microchannel prior to the cancer cells was proven to positively affect the separation efficiency and purity. The proposed device was capable of separating different cells leveraging various diameters with capture purity and efficiency of higher than 83% and 100%, respectively. [ABSTRACT FROM AUTHOR]

This paper presents an optical sensor based on amorphous In–Ga–Zn–O (a-IGZO) photo thin-film transistors (TFTs). To maintain a high signal-to-noise ratio (SNR) of the optical sensor against a variety of ambient white light, this paper employed a-IGZO photo-TFTs for detecting optical input signal sensitive only to short-wavelength light. Measurements of the photosensitivity for optical signal with different wavelengths and optical response for optical input signal under various white light irradiances are proposed to support the reliability of the a-IGZO photo-TFTs under different ambient white light conditions. This paper also simulates a-IGZO photo-TFTs under various white light conditions to predict and design the proposed new sensors and circuits. The simulation results indicated that the proposed optical sensor can maintain the obvious difference in the output voltages with or without optical input signal under the white light irradiances of 0, 268, and $750~\mu \text{W}$ /cm2, demonstrating the feasibility and the reliability of the proposed optical pixel sensor. [ABSTRACT FROM AUTHOR]

To develop an efficient thermal design for gallium-nitride (GaN) high-electron-mobility transistors (HEMTs) that usually hold a super-high-power density, it is essential to accurately predict the junction temperature. In GaN HEMTs, the heat transfer process is dominated by thermal spreading resistance. Moreover, the phonon mean free paths (MFPs) of GaN are comparable with the channel layer thickness and the heat spot width. Thus, a ballistic effect emerges, resulting in the invalidity of Fourier’s heat conduction law. Therefore, Fourier’s law-based thermal resistance model should be reexamined and modified for this case. In this paper, we used the phonon Monte Carlo (MC) method to investigate the thermal spreading resistance in a ballistic-diffusive regime for GaN HEMTs. Our simulation results indicate that the ballistic effect significantly altered the temperature distributions within channel layers and resulted in a dramatic increase in the thermal resistance when compared with Fourier’s law-based predictions. Furthermore, a semiempirical thermal resistance model with a fitting parameter was derived. This model can accurately address the issues of thermal spreading and the ballistic effect. This paper can provide a more in-depth understanding of the thermal spreading resistance in a ballistic-diffusive regime, and it can be useful for the prediction of junction temperatures and for the thermal management of HEMTs. [ABSTRACT FROM AUTHOR]

This paper proposes a robust to defects and short length device (RDSLD), a newly in-plane resonant tunneling diode (RTD), and its ac-modeling with the minimum length of 3 nm. The proposed structure has robust performance in the presence of defects. It also has a high degree of flexibility in tuning electronic specifications. By using bipolar doping and a special h-boron nitride barrier pattern, these unique features are obtained. The simulation results verify that the proposed structure has the potential for replacing conventional RTD diodes. Such that the peak-to-valley ratio (PVR) and the maximum current of 4500, 450 nA for perfect bowtie and 3.45, 1256 nA for rhombic barrier shape structure are obtained, respectively. Also, negative differential resistance (NDR) is observed in all of the structures with vacancy and impurity defects. The effect of the geometrical parameters on the charge transmission of the device is another issue that is addressed in this paper. Furthermore, the analytical and numerical capacitance model parameters are presented. [ABSTRACT FROM AUTHOR]

Efficiency roll-off defined as the rapid efficiency drop by increasing the electrical current density is a major issue in the design of novel organic light-emitting diodes (OLEDs) based on thermally activated delayed fluorescence (TADF). In this paper, it is shown that efficiency enhancement and suppression of efficiency roll-off in TADF OLEDs can be accomplished by broadening the exciton generation zone by precisely tuning the doping concentration of the TADF emissive material in the host matrix. This universal and simply tunable parameter can be applied to any TADF OLED to further enhance its performance characteristics. In this paper, a typical TADF OLED with realistic parameters is numerically investigated by solving the charge carrier transport and excitonic equations and taking into account all relevant processes such as triplet–triplet annihilation, triplet–polaron, and singlet–triplet quenching, and (reverse) intersystem crossing. It is shown that the internal quantum efficiency (IQE) decreases at very low and very high doping densities due to exciton distribution nonuniformity and charge balance factor reduction, respectively. Power efficiency depends on the IQE as well as the potential drop across the emissive layer and decreases at very low doping densities even for a perfectly balanced device; however, the reduction for an unbalanced device is much more substantial. For a perfectly balanced device with an emissive layer thickness of 30 nm, at a current density of 10 mAcm−2, the IQE can be increased from 18% to more than 58% by decreasing the doping concentration from ${c}= {15}$ % to 0.5%. Power efficiency reaches its peak value of 38 lm/W at 1.4% doping. [ABSTRACT FROM AUTHOR]

The first part of this paper presented mymargin the device-level comparison of emerging materials (In0.53Ga0.47As and 2-D materials) and device architecture (NW FETs) with s-Si FinFETs. In order to further understand the performance and energy efficiency of these device options for future technology nodes, it is required to go beyond the device-level comparison by accounting for not only intrinsic but also the extrinsic parasitic elements. In this paper, we present the comparison of s-Si, In0.53Ga0.47As, and 2-D material-based n-type MOSFETs using the circuit-level figure of merits across three successive future technology nodes. The analysis incorporates both device characteristics obtained from an advanced quantum mechanical simulation tool and circuit-level comparison, which accounts for device parasitic elements and wiring load. The results show that 2-D material DG MOSFETs present a more energy-efficient device option than s-Si and In0.53Ga0.47As FinFETs in sub-0.7-V supply voltage regime and In0.53Ga0.47As nanowire (NW) FETs can outperform s-Si multi-gate (MuG) FETs and 2-D material FETs, but when considering non-idealities, s-Si NW FETs remain both faster and more energy-efficient device option. [ABSTRACT FROM AUTHOR]

A novel plasma Charge Accumulative Model (pCAM) by calculating time-integrated Fowler–Nordheim (FN) tunneling charges and field of the gate dielectric in plasma processes is proposed in this paper. Our prior studies have developed and presented a quantitative FinFET plasma recording device by an effective fin-shaped field effect transistor (FinFET) contact-to-metal coupling structure to record and quantify plasma ion charges created in FinFET backend processes. In this paper, a precise analytical model is proposed to model the magnitude of plasma ion charges, time-integrated stressing field, and the criteria of the plasma process for optimum FinFET process technology. The new pCAM is highly matching with the measurement result of 16- and 7-nm FinFET wafers. The model can be adapted to practically estimate the plasma damage with different charge types, process parameters, and ion distribution; it can optimize the FinFET process and further understand the plasma damage mechanism in charging processes of 7-nm FinFET and beyond. [ABSTRACT FROM AUTHOR]

Technology computer-aided design (TCAD) is an integral part of the development process of semiconductor technologies and devices, a field which has become increasingly complex and heterogeneous. Processing of integrated circuits requires nowadays over 400 process steps, and the resulting devices often have an intricate 3-D structure and contain various specifically designed materials. The full device behavior can only be understood by considering effects on all length scales from atomistic (material properties, interfaces, defects, and so on), to nanometric (quantum confinement, non-bulk properties, tunneling, ballistic transport, and so on), to full-chip dimensions (strain, heat transport, and so on), and time scales from femtoseconds (scattering, ferroelectric switching time, and so on) to seconds (trapping times, degradation, and so on). Voltages, currents, and charges have been scaled to such low levels that statistical effects and process variations have a strong impact. Devices based on new materials (e.g., 2-D crystals) and physical principles (ferroelectrics, magnetic materials, qubits, and so on) challenge standard TCAD approaches. While the simulation methods developed by the physics community can describe the basic device behavior, they often lack important simulation capabilities like, for example, transient simulations or integration with other TCAD tools, and are often too slow for daily use. Due to the complexity of semiconductor technology, it becomes more and more difficult to assess the impact of a change in processing or device structure on circuit performance by looking at a single aspect of an isolated device under idealized conditions. Instead, a TCAD tool chain is required which can handle realistic device structures embedded in a chip environment. New methodologies are required for all aspects of TCAD to ensure an efficient tool chain covering from atomistic effects to circuit behavior based on flexible simulation models that can handle new materials, device principles, and the ensuing large-scale simulations and that make use of artificial intelligence for well-chosen (sub)routines to decrease the overall simulation time. This Special Issue features six invited and 18 regular papers that address these problems. [ABSTRACT FROM AUTHOR]