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Magnetic tunnel junctions (MTJs) with low switching current, high thermal stability, and small device size are strongly preferred for low-power, high-reliability, and high-density spintronic memory and logic applications. The research of MTJs from shape in-plane magnetic anisotropy to interfacial perpendicular magnetic anisotropy (i-PMA) has successfully paved the way down to 20-nm scale, below which, however, the i-PMA approach reaches a physical limit in sustaining sufficient thermal stability while achieving low-power spin transfer torque switching. Recently, studies have been reported a new approach to pave the way toward sub-10-nm MTJs satisfying the requirements by revisiting shape perpendicular magnetic anisotropy (s-PMA). In this paper, we present a compact model of the sub-10-nm s-PMA MTJ device, which captures both the static and dynamic physical behaviors. This model is SPICE-compatible for hybrid MTJ/CMOS circuit designs. This paper is expected to push forward the development of sub-10-nm-scale MTJ-based spintronic memory and logic circuits. [ABSTRACT FROM AUTHOR]

Although spin transfer torque (STT)-based magnetic tunneling junction (MTJ) owns advantages of nonvolatility, nonlimited endurance, and fast write/read, its demand for high current density significantly casts a shadow over its future prospects. Recently, a novel three-terminal MTJ cell that combines voltage-controlled magnetic anisotropy (VCMA) effect and negative capacitance (NC) effect is proposed. Drawing support from the NC amplified VCMA effect and the three-step operation scenario, this novel MTJ cell can dramatically lower the energy consumption to fJ as well as keep high operation speed within nanoseconds. The feasibility of the proposed NC enhanced VCMA spintronics device for memory and logic application is proved by extensive physical simulation in our previous work. However, a SPICE compatible compact model of the proposed NC enhanced VCMA spintronics device is still demanded for circuit and system level evaluation. In this paper, we provide an accurate and fast compact model of NC enhanced VCMA device for both memory and logic applications. [ABSTRACT FROM AUTHOR]

The current-induced perpendicular magnetic anisotropy magnetic tunnel junctions (p-MTJs) offer a number of advantages, such as high density and high speed. As p-MTJs downscale to $\sim 40$ nm, further performance enhancements can be realized thanks to high spin-torque efficiency, i.e., lower critical current density and higher thermal stability. In this paper, we investigate the origin of high spin-torque efficiency and give a phenomenological theory to describe the critical current reduction due to the subvolume activation. Based on various physical theories and structural parameters, a compact model of nanoscale MTJ is developed and demonstrates a satisfactory agreement with experimental results. Dynamic, static, and stochastic switching behaviors have been addressed and validated. Then, we perform mixed simulations for hybrid MTJ/CMOS read/write circuits, magnetic random access memory, and magnetic flip-flop to evaluate their performance. Analyses of energy consumption are given to show the prospect of MTJ technology node miniaturization. [ABSTRACT FROM AUTHOR]

The aim of this paper is to introduce a compact model for perpendicular spin-transfer torque (STT)-magnetic tunnel junctions (MTJs) implemented in Verilog-A to assure easy integration with electrical circuit simulators. It takes into account the effects of voltage-dependent perpendicular magnetic anisotropy, temperature-dependent parameters, thermal heating/cooling, MTJ process variations, and the spin-torque asymmetry of the Slonczewski spin-polarization function in the switching process. This translates into a comprehensive modeling that was adopted to investigate the writing performance under voltage scaling of a $256\times256$ STT- magnetic random access memory array implemented at three different technology nodes. Obtained results show that scaling from 30- to 20-nm node allows a write energy saving of about 43%, while the supply voltage that assures the minimum-energy write operation increases. [ABSTRACT FROM PUBLISHER]

Magnetic tunnel junctions (MTJs) composed of ferromagnetic layers with perpendicular magnetic anisotropy (PMA) are of great interest for achieving high-density nonvolatile memory and logic chips owing to its scalability potential together with high thermal stability. Recent progress has demonstrated a capacity for high-speed performance and low power consumption through current-induced magnetization switching. In this paper, we present a compact model of the CoFeB/MgO PMA MTJ, a system exhibiting the best tunnel magnetoresistance ratio and switching performance. It integrates the physical models of static, dynamic, and stochastic behaviors; many experimental parameters are directly included to improve the agreement of simulation with experimental measurements. Mixed simulation based on the 65-nm technology node of a magnetic flip-flop validates its relevance and efficiency for MTJ/CMOS memory and logic chip design. [ABSTRACT FROM AUTHOR]

A circuit-level model of a magnetic tunnel junction (MTJ) that accurately depicts the spin-transfer torque switching behavior of an MTJ along with its voltage/temperature dependency is presented. The unified switching model that was suggested in our previous work is suitable for the circuit-level model because the model seamlessly covers the entire current pulsewidth region. Based on this switching behavior model, a method of dynamic current monitoring is proposed for an advanced circuit-level model. The voltage/temperature characteristics of an MTJ are also integrated for a more accurate circuit-level simulation. The proposed model corresponds well with the experimental data for switching characteristics at different temperatures. The design margin in the read/write circuits with an MTJ is analyzed to demonstrate the effectiveness of the model. [ABSTRACT FROM AUTHOR]

Spin-transfer torque random-access memory (STT-RAM) is gaining momentum as a promising technology for high-density and embedded nonvolatile memory. Owing to random thermal fluctuations, switching transitions generally display statistical variations from cycle to cycle. Stochastic variations are critical to the hindering of memory and computing applications of STT-RAM. To enable the design of STT-RAM circuits for memory and computing, there is a need for accurate compact models capable of predicting the stochastic behavior. Here, we present a detailed model accounting for the anomalous thermal regime of switching deviating from the Néel–Brown thermal model below 200 ns. Anomalous switching is explained by the nonlinear lowering of the energy barrier associated with the perpendicular magnetic anisotropy (PMA). The model is extensively verified against the write-error-rate (WER) data as a function of applied voltage and pulsewidth and experimental switching time-delay distributions. [ABSTRACT FROM AUTHOR]

A simulation framework that can comprehend the impact of material changes from the device level to the system level design can be of great value, especially to evaluate the impact of emerging devices on various applications. To that effect, we developed a SPICE-based hybrid magnetic tunnel junction (MTJ)/CMOS simulator, which can be used to explore new opportunities in large scale system design. In the proposed simulation framework, MTJ modeling is based on Landau–Lifshitz–Gilbert (LLG) equation incorporating both spin-torque and external magnetic field(s). LLG, along with heat diffusion equation, thermal variations, and electron transport, is implemented using SPICE-inbuilt voltage-dependent current sources and capacitors. The proposed simulation framework is flexible because the physical device parameters such as MgO thickness, ferromagnet material anisotropy (Ku), and device dimensions are user-defined parameters. Furthermore, we benchmarked this model with experiments in terms of switching current density (JC), switching time (TSWITCH), and tunneling magnetoresistance. Finally, we used the simulation framework to study different MTJ structures, such as in-plane magnet anisotropy and perpendicular magnet anisotropy, the impact of parametric process variations and temperature on the yield of spin transfer torque magnetoresistive random access memories, magnetic flip-flops, and spin-torque oscillators. [ABSTRACT FROM AUTHOR]