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The dc and radio-frequency (rf) characteristics of [Al.sub.0.3][Ga.sub.0.7]N/GaN/[In.sub.0.1][Ga.sub.0.9]N/GaN double-heterojunction HEMT (DH-HEMT) structure are analyzed. The E-mode devices with good dc, RF small signal, and power performances are fabricated on the InGaN-notch DH-HEMT structure by using C[F.sub.4] plasma treatment before the deposition of the gate electrodes.

A physical-based analytical model for on-chip spiral inductors with accurate substrate modeling is developed. This generic model can be applied to various substrate resistivities and can also facilitate the design and optimization of on-chip inductor for radio-frequency (RF) IC applications.

The monolithic integration of enhancement/depletion-mode (E/D-mode) HEMTs in the GaN material system is demonstrated based on a novel technique of fabricating high-performance E-mode HEMT using fluoride-based C[F.sub.4] plasma treatment. The integration technology, used to fabricate integrated AlGaN/GaN HEMT inverters and ring oscillators for evaluating the performance of the digital IC technology, results in an improved input voltage swing by about 1V for the E-mode HEMT.

A fabrication method with an accurate control of threshold voltages ([V.sub.th] of AlGaN/GaN high-electron mobility transistors (HEMTs) using a fluoride-based plasma treatment is presented, whereby the [V.sub.th] of AlGaN/GaN HEMTs can be continuously shifted from -4V in a conventional depletion-mode HEMT to 0.9V in an enhancement-mode HEMT. A physical model of the threshold voltage is provided to analyze the effects of the fluoride-based plasma treatment on AlGaN/GaN HEMTs.

The samples grown on a low-cost silicon substrate fabrication process were used to demonstrate the high-performance enhancement-mode AlGaN/GaN HEMTs (E-HEMTs) based on a fluoride-based plasma treatment of the gate region and postgate annealing at 450 degree Celsius. It was found that the fabricated HEMTs almost had the same peak transconductance and cutoff frequencies as the depletion-mode HEMTs and suggested little mobility degradation by plasma treatment.

The design, fabrication and characterization of AlGaN-GaN double-channel of high-electron mobility transistors (HEMTs) are presented. Two carrier channels are formed in an AlGaN-GaN-AlGaN-GaN multilayer structure grown on a sapphire substrate.

A high performance InP-based enhancement-mode high electron mobility transistor (E-HEMT) fabrication involves the use of non-alloyed ohmic contacts and Pt-based buried gate technologies. The technique lowers the source resistance. An E-HEMT with a 0.5 micrometer gate shows a minimum transconductance of 1170 millisecond/millimeter. The fabrication procedure involves making depletion-mode HEMT's first and then later annealing them at 250 degrees celsius to give E-HEMT's. The process maintains the source resistance at about 0.2 ohm-millimeters.

We conducted reliability characterization under reverse-bias stress (i.e., stress at OFF-state with high VDS) on the E-mode GaN metal–insulator–semiconductor field-effect-transistors (MIS-FETs) with various substrate terminations. The MIS-FETs with floating substrate (FS) show worse threshold voltage (VTH) stability than that with a grounded substrate. A non monotonic dependence of VTH shifts and OFF-state time-to-breakdown (tbd) on the positive substrate bias (Vsub) was also observed. The underlying mechanisms are the different impacts of positive Vsub on the drift of electrons and holes during the long-term stress. An important indication is that positive-biased and FS terminations should be restricted at OFF-state in order to obtain good VTH stability in applications of the GaN MIS-FET. [ABSTRACT FROM AUTHOR]

In this paper, we carried out a systematic comparison between the enhancement-mode GaN-based fully recessed metal-insulator-semiconductor field-effect transistors (MIS-FETs) and partially recessed MIS-high-electron-mobility transistors (MIS-HEMTs) with the same gate dielectric stack (LPCVD-SiNx/PECVD-SiNx) that has delivered promising long-term reliability and stability. Despite a moderately larger on-resistance (${R}_{ \mathrm{ON}}$), the MIS-FETs deliver superior ${V}_{\text {TH}}$ uniformity and thermal stability. Under long-term gate bias stress, both the MIS-HEMT and MIS-FET deliver similar small positive-bias temperature instability, while the negative-bias temperature instability of the MIS-HEMT is much larger than that of MIS-FET. The MIS-FET also delivers a higher ${V}_{\text {TH}}$ stability than the MIS-HEMT under dynamic gate bias stress. It is suggested that the differences in ${V}_{\text {TH}}$ stability mainly originate from the different spatial separation between the trap states and the conducting channel, with it being larger in MIS-HEMT than in MIS-FET. [ABSTRACT FROM AUTHOR]

Bulk traps in the high-resistivity buffer stack underneath the 2-dimensional electron gas (2DEG), which can interact with the high vertical electric field at OFF state, impose a critical challenge to the dynamic ON-resistance (RON) of AlGaN/GaN-on-Si power devices. In this paper, the impact of substrate bias polarity on carrier injection/transport and buffer-induced current collapse has been investigated by using ramped and transient back-gating characterizations as well as TCAD simulations. High voltage applied to the conductive Si substrate can modulate 2DEG conductivity through the back-gate effect, whereby the dynamics of both acceptor and donor buffer traps are identified. Distinct buffer trapping and asymmetric vertical leakage under opposite top-to-substratebias polarities have been observed, which are attributed to the fundamentally different carrier injection/transport mechanisms. It is suggested that the energy barrier at the nucleation-layer/Si interface can limit the electron injection from Si substrate into the buffer stack and consequently influence the bufferrelated current collapse. [ABSTRACT FROM AUTHOR]

Effective interface trap characterization approaches are indispensable in the development of gate stack and dielectric surface passivation technologies in III-nitride (III-N) insulated-gate power switching transistors for enhanced stability and dynamic performance. In III-N metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) that feature a buried channel, the polarized barrier layer separates the critical dielectric/III-N interface from the two-dimensional electron gas (2DEG) channel and consequently complicates interface trap analysis. The barrier layer not only causes underestimation/uncertainty in interface trap extraction using conventional ac-conductance method but also allows the Fermi level dipping deep into the bandgap at the pinch-off of the 2DEG channel. To address these issues, we analyze the frequency/temperature dispersions of the second slope in capacitance-voltage characteristics and develop systematic ac-capacitance techniques to realize interface trap mapping in MIS-HEMTs. The correlation between ac-capacitance and pulse-mode hysteresis measurements show that appropriate gate bias need to be selected in the interface trap characterization of MIS-HEMTs, in order to match the time constant of interface traps at the Fermi level with ac frequency and pulsewidth. [ABSTRACT FROM AUTHOR]