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This paper provides an industry perspective on the present state of compact models for MOS transistors. It highlights the complexity of layout-dependent effects in modern transistors, reviews some common misunderstandings of MOS transistor capacitances, and introduces a new, structurally symmetric, “gate-as-input” equivalent network for these capacitances. Areas of focus for the future model developments are also proposed. [ABSTRACT FROM AUTHOR]

An introduction is presented in which the editor discusses various articles within the issue on topics including research and development in compact models, metal oxide semiconductor field-effect transistors (MOSFET) modeling and RF Compact Model for Bulk MOSFET.

The first part of this paper presented mymargin the device-level comparison of emerging materials (In0.53Ga0.47As and 2-D materials) and device architecture (NW FETs) with s-Si FinFETs. In order to further understand the performance and energy efficiency of these device options for future technology nodes, it is required to go beyond the device-level comparison by accounting for not only intrinsic but also the extrinsic parasitic elements. In this paper, we present the comparison of s-Si, In0.53Ga0.47As, and 2-D material-based n-type MOSFETs using the circuit-level figure of merits across three successive future technology nodes. The analysis incorporates both device characteristics obtained from an advanced quantum mechanical simulation tool and circuit-level comparison, which accounts for device parasitic elements and wiring load. The results show that 2-D material DG MOSFETs present a more energy-efficient device option than s-Si and In0.53Ga0.47As FinFETs in sub-0.7-V supply voltage regime and In0.53Ga0.47As nanowire (NW) FETs can outperform s-Si multi-gate (MuG) FETs and 2-D material FETs, but when considering non-idealities, s-Si NW FETs remain both faster and more energy-efficient device option. [ABSTRACT FROM AUTHOR]

Because of charge trapping in GaN HEMTs, dc characteristics of these devices are not representative of high-frequency operation. The advanced spice model GaN model presented in Part I of this paper is combined with a Shockley–Reed–Hall-based trap model, yielding a comprehensive FET model for GaN HEMTs which can accurately model GaN devices exhibiting trapping-related dispersion effects. Measurement results of the dc and pulsed output and transfer characteristics of a commercially available GaN HEMT are presented, trapping in the device is modeled, and excellent fit to the measured data is shown. This paper presents an accurate model of trapping which is validated for eight different quiescent bias points of pulse measurements, with quiescent drain voltage ranging from 5 to 20 V and quiescent gate voltage ranging from −2.8 to −3.8 V, and a large range of gate and drain voltages to which the device was pulsed in the pulse measurements and at which the device was measured in the dc measurements, with gate voltage ranging from −4 to 0.4 V and drain voltage ranging from 0 to 40 V. This paper also presents high-frequency (10 GHz) large-signal RF validation of the model for optimal complex load condition. [ABSTRACT FROM AUTHOR]

In negative capacitance field-effect transistors (NCFETs), drain current may decrease with increasing ${V}_{\mathrm {ds}}$ in the saturation region, leading to negative differential resistance (NDR). While NDR is useful for oscillator design, it is undesirable for most analog circuits. On the other hand, the tendency toward NDR may be used to reduce the normally positive output conductance ( ${g}_{ \mathrm {ds}}$ ) of a short-channel transistor to a nearly zero positive value to achieve higher voltage gain. In this paper, we analyze the NDR effect for NCFET in the static limit and demonstrate that it can be engineered to reduce ${g}_{\mathrm {ds}}$ degradation in short-channel devices. Small and positive $g_{\mathrm{ ds}}$ is achieved without compromising the subthreshold gain, which is crucial for analog applications. The 7-nm ITRS 2.0 FinFET with 0.7 V ${V}_{\mathrm {dd}}$ is used as the baseline device in this paper. [ABSTRACT FROM AUTHOR]

This paper presents a new approach for compact modeling of aging and radiation effects for MOS transistors including process variation and environmental influences. This approach can be used in common design flows for analog integrated circuits. Moreover, the aging behavior of whole circuits can be analyzed without the need for abstractions or extrapolation. Only one common physically motivated transistor parameter is used in order to model radiation and degradation mechanisms. [ABSTRACT FROM AUTHOR]

Magnetic tunnel junctions (MTJs) with low switching current, high thermal stability, and small device size are strongly preferred for low-power, high-reliability, and high-density spintronic memory and logic applications. The research of MTJs from shape in-plane magnetic anisotropy to interfacial perpendicular magnetic anisotropy (i-PMA) has successfully paved the way down to 20-nm scale, below which, however, the i-PMA approach reaches a physical limit in sustaining sufficient thermal stability while achieving low-power spin transfer torque switching. Recently, studies have been reported a new approach to pave the way toward sub-10-nm MTJs satisfying the requirements by revisiting shape perpendicular magnetic anisotropy (s-PMA). In this paper, we present a compact model of the sub-10-nm s-PMA MTJ device, which captures both the static and dynamic physical behaviors. This model is SPICE-compatible for hybrid MTJ/CMOS circuit designs. This paper is expected to push forward the development of sub-10-nm-scale MTJ-based spintronic memory and logic circuits. [ABSTRACT FROM AUTHOR]

Stacks of 2-D materials, known as van der Waals (vdW) heterostructures, have gained vast attention due to their interesting electrical and optoelectronic properties. This paper presents an intuitive circuit model for the out-of-plane electrostatics of a vdW heterostructure composed of an arbitrary number of layers of 2-D semiconductors, graphene, or metal. We explain the mapping between the out-of-plane energy band diagram and the elements of the equivalent circuit. Although the direct solution of the circuit model for an n-layer structure is not possible due to the variable, nonlinear quantum capacitance of each layer, this paper uses the intuition gained from the energy band picture to provide an efficient solution in terms of a single variable. Our method employs Fermi–Dirac statistics while properly modeling the finite density of states (DOS) of 2-D semiconductors and graphene. The approach circumvents difficulties that arise in commercial TCAD tools, such as the proper handling of the 2-D DOS and the simulation boundary conditions when the structure terminates with a nonmetallic material. Based on this methodology, we have developed 2dmatstacks, an open-source tool freely available on nanohub.org. Overall, this paper equips researchers to analyze, understand, and predict experimental results in complicated vdW stacks. [ABSTRACT FROM AUTHOR]

In this paper, we systematically evaluate the variation in the reversal delay of a nanomagnet driven by a longitudinal spin current under the influence of thermal noise. We then use the results to evaluate the performance of an all-spin-logic (ASL) circuit. First, we review and expand on the physics of previously published analytical models on stochastic nanomagnet switching. The limits of previously established models are defined, and it is shown that these models are valid for nanomagnet reversal times <200 ps. Second, the insight obtained from previous models allows us to represent the probability density function (pdf) of the nanomagnet switching delay using the double exponential function of the Fréchet distribution. The pdf of a single nanomagnet is extended to more complex nanomagnet circuit configurations. It is shown that the delay-variation penalty incurred by nanomagnets arranged in parallel configuration is dwarfed by the average delay increase for nanomagnets arranged in a series configuration. Finally, we demonstrate the impact of device-level performance variation on the circuit behavior using ASL logic gates. While the analysis presented in this paper uses an ASL-AND gate as the prototype switching circuit in the spin domain, the physical concepts are generic and can be extended to any complex spin-based circuit. [ABSTRACT FROM PUBLISHER]

In this paper, we present a surface potential-based explicit continuous model for a metal-ferroelectric-insulator-semiconductor (MFIS) type gate-all-around negative capacitance transistor (GAA-NCFET). Unlike previously reported models, an explicit formulation to calculate the electrical characteristics of GAA-NCFET is proposed. Our model includes the radial dependence of the electric field in the ferroelectric, ignored in the previous works and accurately captures ferroelectric material parameter variations in the nonhysteretic regime. In contrast to bulk NCFETs, GAA-NCFET characteristics show different bias dependence due to the absence of bulk charge. We also present analytical expressions for the terminal charges which are essential to obtain the trans-capacitances for transient simulations. We find that, compared with conventional MOSFETs, the gate charge saturates to a different fraction of its maximum value. Furthermore, the modeling of quantum mechanical effect and overlap capacitances in an MFIS NCFET structure is discussed. Finally, the proposed model has been implemented in Verilog-A and tested for the transient response of ring oscillator in a commercial circuit simulator. [ABSTRACT FROM AUTHOR]

In this paper, we report a physics-based compact model for monolayer graphene field-effect transistors (m-GFETs) based on the 2-D Density of States of monolayer graphene and the drift-diffusion equation. Furthermore, the Ward-Dutton charge partitioning scheme has been incorporated to the model extending its capabilities to AC and transient simulations. The model has been validated through comparison with DC and RF measurements from two different long-channel m-GFET technologies. Moreover, values of parasitic elements included in the model are extracted from measurements on dedicated test structures and verified through electromagnetic simulations (EM). Finally, an EM-SPICE co-simulation has been carried out to assess the applicability of the developed m-GFET model for the design of “balun” circuits. [ABSTRACT FROM PUBLISHER]

A bond-pad charging protection design for charging-free reference transistor test structures was examined. This paper concludes that truly charging-free reference transistors cannot be realized with the one conventional bond-pad charging protection design of protecting transistor gates only. This, however, can be achieved by simultaneously protecting all terminals of the reference transistors. The simulations, in this paper, reconfirm the earlier important experimental conclusion that placing protection device(s) at transistor gates may inflict severe damage to transistor gate oxides instead of protecting them. The implication of the above suggests that attention may be required in a circuit layout design stage for those transistors which gates begin to connect, at high metal layers, to highly efficient leakage paths, such as protection devices, n-type source/drain diffusion regions, and VSS bus lines, which tend to pull transistor gates to low potentials during a backend integrated-circuit manufacturing process. This paper proposes an optimum bond-pad charging protection design for the truly charging-free reference transistor test structures by considering a minimum usage in a layout space and minimum gate oxide stress in the fuse zap-off process. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel compact statistical model for the low-frequency noise (LFN) of MOS devices with halo implants. The compact model is suited for the incorporation in modern models, such as BSIM, PSP, and EKV, and can be used to predict the dependence of the LFN of halo-implanted MOSFETs with bias, temperature, geometry, and technological parameters. This compact model is based on the physics-based random telegraph noise (RTN) model, previously published by our group. The previous model was simplified in analytical expressions dependent on parameters and on physical quantities already calculated in modern compact models. Following the physics-based model, the LFN compact model predicts the large bias dependence of the LFN statistics induced by the halo implants in long-channel devices. Moreover, we show for the first time that the halo implants also induce a large temperature dependence of the LFN statistics for devices operated near the weak inversion or saturation, and the proposed compact model predicts this dependence. [ABSTRACT FROM AUTHOR]

Integrated circuits operated in the near-threshold region exhibit specific merit with high energy efficiency. A near-threshold model is highly required for the circuit design. In this paper, a near-threshold drain current model is proposed based on the surface inversion layer charge model for analyzing digital circuits. The short-channel effect in deep submicrometer is also included in the model. Moreover, the delay and energy parts based on the near-threshold drain current model are derived and integrated in the model. Two process design kits (PDKs) are used for parameter extraction to demonstrate the feasibility of the proposed model. The results show that the proposed model can be used for the near-threshold circuit calculation, with the benefit of high accuracy. [ABSTRACT FROM AUTHOR]

This paper examines metal–ferroelectric–insulator–semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse Vds-dependence of threshold voltage (VT), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low VDD. [ABSTRACT FROM AUTHOR]

This paper presents the analyses on the self-sustained oscillation of superjunction MOSFET intrinsic diode. At first, the characteristics of the self-sustained oscillation for the superjunction MOSFET intrinsic diode are identified by the double-pulse switching test. The test results show that the self-sustained oscillation with significant self-amplification phenomenon can be triggered during the reverse recovery transient of superjunction MOSFET intrinsic diode. Based on the Sentaurus TCAD simulation, the self-sustained oscillation is reproduced. The simulation results reveal the root cause of the self-sustained oscillation. Due to the snappy reverse recovery of superjunction MOSFET intrinsic diode, the steep slope of diode snap off current can generate high voltage across the common source inductance, which drives the gate–source voltage and turns on the high-side MOSFET. The unexpected MOSFET turn-on can, in return, enhance the steepness of the current slope when the diode snap off. This leads to a positive feedback process and self-sustained oscillation is generated. In the end, based on the theoretical analyses and experimental results, the necessary methods that can suppress the oscillation are presented. [ABSTRACT FROM AUTHOR]

In this paper, the read margin (RM) and write power (WP) of 3-D vertical resistive random access memory (VRRAM) are analyzed by considering the variation in RRAM cell (self-rectifying cell) characteristics. To demonstrate the cell variation effect on a large 3-D VRRAM array, we develop a modified lumping method in HSPICE simulator and show that this method substantially reduces the computation time while maintaining high accuracy. Read and write performances including cell variation are investigated according to various array sizes and RRAM characteristics. A large distribution of cell current reduces the RM but hardly affects the WP. Moreover, in 3-D VRRAM with a small number of wordline (WL) layers, a large on/off ratio (RHRS/RLRS) is advantageous for improving the RM and reducing the variation effect. In contrast, a large on/off ratio has little effect on the RM in 3-D VRRAM with many WL layers. This difference occurs because the increased leakage induced in the half-selected cells mainly affects the RM, and the half-selected cells are located in the selected vertical pillar in 3-D VRRAM. [ABSTRACT FROM AUTHOR]

Variability is a challenge for future scaling as process dimensions reduce. The emerging 3-D sequential stacking technology is more than Moore’s scaling alternative. The 3-D design flow requires the partitioning of the netlist between the tiers. This paper presents the variability analysis of circuits partitioned into different levels. A comparison among local and global variations effects on ring oscillators (ROs) and SRAM is demonstrated. The across-chip variations and correlation range are shown as a critical point for the 3-D very large-scale integrated circuits, where the local variability is dominant. The correlations between devices due to the distances or the allocation into different tiers are directly taken into account in the SPICE model due to a statically unified model applied to 3-D circuits based on Monte Carlo simulations. Design wise, the 3-D integration can further decrease the circuit variability as shown in RO output frequency and SRAM static noise margin. [ABSTRACT FROM AUTHOR]

This paper proposes amorphous indium–gallium–zinc oxide thin-film transistors (TFTs) four-transistor-two-capacitor (4T2C) pixel circuit in combination with a top-anode organic light-emitting diode (OLED) for the use in 8K4K active-matrix organic light-emitting diode displays (AM-OLEDs). The proposed pixel circuit compensates for driving TFTs threshold voltage (${V} _{\textsf {TH}}$) shifts and mobility variations, ${V} _{\textsf {DD}}$ current–resistance (${I}$ – ${R}$) drops, and ${V} _{\textsf {SS}}~{I}$ – ${R}$ -induced rises. Both the positive and negative ${V} _{\textsf {TH}}$ of the driving TFT can be sensed by the proposed circuit. In this paper, we analyze the impact of the driving TFT compensation time for low gray levels. The current error rates are calculated when TFT mobility variations are considered. The proposed pixel circuit allows an increase in the compensation time to reduce the impact of driving TFT ${V} _{\textsf {TH}}$ and mobility variations on the performance of 4T2C pixel circuit. Conventional two-transistor-one-capacitor, five-transistor-two-capacitor, and proposed 4T2C pixel circuits are simulated and compared in this paper. The proposed pixel 4T2C circuit reduces the current error rates to below 5.79% when the ${V} _{\textsf {TH}}$ shifts of ±2 V, mobility variations of ±10%, ${V} _{\textsf {DD}}~{I}$ – ${R}$ drops of 1 V, and ${V} _{\textsf {SS}}~{I}$ – ${R}$ rises of 1 V are all considered. We show that the proposed 4T2C pixel circuit is suitable for 8K4K AM-OLEDs. [ABSTRACT FROM AUTHOR]

We present the latest developments in Advance SPICE Model for GaN (ASM GaN) HEMTs in this paper. The ASM GaN model has been recently selected as an industry-standard compact model for GaN radio frequency (RF) and power devices. The core surface-potential calculation and the modeling of real device effects in this model are presented. We discuss the details of the nonlinear access region model and enhancement in this model to include a physical dependence on barrier thickness. We also present the novel model feature of configurable field-plate modeling and discuss the extraction procedure for the same. New results with the ASM GaN model on high-frequency and enhancement-mode GaN power devices are also presented. [ABSTRACT FROM AUTHOR]

This paper proposes a compact model for chipless radio frequency identification (RFID) tag. This compact scalable model consists of capacitors, inductors, and resistors of which their values are directly described by the physical dimension of the chipless tag. Moreover, based on this compact model, radar cross section of chipless RFID tag is predicted, by analyzing polarizability based on surface current distribution in different modes. To validate the proposed model, a 5-bit chipless RFID tag based on high-impedance surface (HIS) is presented, with good agreement among modeled, simulated, and measured results. A wide range of physical parameters have also been validated to show the scalability. This compact scalable model of chipless RFID tag not only simplifies the tag design, but also provides an insight understanding of the HIS structure. [ABSTRACT FROM AUTHOR]

This paper illustrates the usefulness of the physics-based compact device models in investigating the impact of device behavioral nuances on the operation and performance of the circuits and systems. The industry standard MIT virtual source gallium nitride high electron-mobility transistor (GaN HEMT) (MVSG) model is used as the modeling framework to understand the operation of the GaN HEMTs and study the key device–circuit interactions in the GaN-based high-frequency and power conversion circuits. Details of the core model equations along with their physical underpinnings are presented along with the benchmark tests to verify the model’s convergence robustness and simulation accuracy. The usefulness of such a compact model in circuit design is highlighted through examples of the GaN-based high-voltage converter and RF-power amplifiers. It is shown that the slew-rates in hard-switched buck converters are determined by the dynamic charge distribution among the field plates in GaN HEMTs, indicating the importance of the device-level effect on circuit performance. Likewise, it is shown using the MVSG model that the performance metrics, such as drain efficiency and linearity, of the GaN RF-power amplifiers are heavily dependent on the device-level effects, such as access-region depletion, thermal effects, and charge-trapping effects. These GaN-based circuits designed using the MVSG model can be used as the example cases to demonstrate the importance of the accurate physical compact models in designing high performance circuits and systems in emerging technologies. [ABSTRACT FROM AUTHOR]

A new curved-profile undepressed collector designed for a planned 35-GHz gyrotron traveling-wave tube (gyro-TWT) is proposed in this paper. This gyro-TWT, which is driven by a 70-kV, 10-A electron beam, is working at the fundamental TE01 mode with an efficiency of 20% and gain of 45 dB. Studies including theoretical analysis, numerical calculation, and computational simulation have been done. Key issues concerning electronic collecting density, dissipated power distribution, transmission performance, secondary electrons, and thermal property are considered. Simulation results show that curved-profile structure collector has a better heat-handling capacity than the conventional line structure collector. [ABSTRACT FROM AUTHOR]

Ballistic (collision free) and drift-diffusive (collision dominated) transport mechanisms are both present in graphene, and they together contribute in the current conduction in a graphene FET (GFET). In this paper, we propose an analytical drain current model based on ballistic (${n}_{B}$) and drift-diffusive (${n}_{D}$) charge densities, backscattering coefficient (${R}$), and quasi-ballistic mobility ($\mu _{\text {eff}}$). ${n}_{B}$ is calculated using the McKelvey flux theory and ${n}_{D}$ using the surface potential approach. A closed-form analytical expression is derived for the backscattering coefficient, which is valid under both low and high electric field conditions. The effective quasi-ballistic mobility is obtained by considering both scattering-dominated and scattering free mobilities. The proposed model is well aligned with experimental data, in all regions of operation, for single- and double-gate GFETs. [ABSTRACT FROM AUTHOR]

In this paper, an enhanced compact model of multiwalled carbon nanotube (MWCNT) interconnects while considering defects and contact resistance is proposed. Based on the atomistic-level simulations, we have found that defect densities impact MWCNT resistance and ultimately their electrical performance. Furthermore, we have computed by atomistic-level simulations, the end-contact resistance between single-wall carbon nanotube and palladium (Pd) electrode to mimic the Pd–CNT end-contact resistance of each CNT shell in MWCNT. We have developed an advanced shell-by-shell model to include various parameters, such as shell diameter, shell chirality, defects on each shell, and connectivity of each shell to end contacts. We run Monte Carlo simulations to perform variability studies on each of these parameters to understand the electrical performance variation on MWCNT interconnects. We present the simulation results to convey the critical impact of variations. The impact of doping on MWCNT variability in the form of Fermi level shift will be addressed in Part II of this paper. [ABSTRACT FROM AUTHOR]

A general equivalent circuit model for the metal/organic semiconductor (OSC)/liquid/metal system is presented. Each circuital element, representative of a physically observable phenomenon associated with the device working principle, is analyzed and discussed. Two case studies of electrochemical impedance spectroscopy of devices featuring NaCl (concentration of 0.1 M) and MilliQ water as liquid are reported, showing that both cases can be considered as a particular case of the general model presented in this paper. Experimental verification of the two practical cases is achieved by performing measurements onto electrodes coated by either an n-type or a p-type OSC deposited by sublimation or drop casting, respectively. The good agreement with the experimental data makes our model a useful tool for the characterization and failure analysis of electronic devices, such as water-gated transistors, electrophysiological interfaces, fuel cells, and others electrochemical systems. [ABSTRACT FROM AUTHOR]

This paper presents a physics-based analytical model for the MOS transistor operating continuously from room temperature down to liquid-helium temperature (4.2 K) from depletion to strong inversion and in the linear and saturation regimes. The model is developed relying on the 1-D Poisson equation and the drift-diffusion transport mechanism. The validity of the Maxwell–Boltzmann approximation is demonstrated in the limit to 0 K as a result of dopant freezeout in cryogenic equilibrium. Explicit MOS transistor expressions are then derived, including incomplete dopant ionization, bandgap widening, mobility reduction, and interface charge traps. The temperature dependence of the interface trapping process explains the discrepancy between the measured value of the subthreshold swing and the thermal limit at deep-cryogenic temperatures. The accuracy of the developed model is validated by experimental results on long devices of a commercial 28-nm bulk CMOS process. The proposed model provides the core expressions for the development of physically accurate compact models dedicated to low-temperature CMOS circuit simulation. [ABSTRACT FROM AUTHOR]

In our earlier work, we presented a percolation theory-based analytical model to estimate FinFET’s VT distribution due to fin edge roughness. The earlier models in the literature were based on minimum fin width, the limitations of which were discussed in detail. In this paper, we advance the percolation theory-based model to capture the variability in all key-device parameters, viz. I \mathrm{\scriptscriptstyle ON} , I \mathrm{\scriptscriptstyle OFF} , subthreshold slope, and VT . The entire distribution of these parameters obtained by the model is presented and compared against stochastic TCAD to demonstrate excellent match. The model reduces rms error in $\mu $ of various parameters by 5%–60%, and 20%–50% in $\sigma $ with respect to the minimum fin width-based models present in the literature. [ABSTRACT FROM PUBLISHER]

Compact flicker noise models used in SPICE circuit simulators are derived from the seminal BSIM unified noise model. In this paper, we show that use of this model can give anomalous bias dependence of input referred noise. In addition, we find that the state-of-the art flicker noise models are not adequate to capture the drain bias dependence of flicker noise in short channel devices. In this paper, we address both the issues with a new compact model. [ABSTRACT FROM AUTHOR]

The base series resistance is an important parameter for bipolar junction transistors and heterojunction bipolar transistor (HBTs). Although many methods have been proposed for its experimental determination, their results vary significantly. In this paper, the most widely used methods are reviewed and applied to SiGe HBTs of different technologies and generations including different device types, i.e. high-speed and high-voltage SiGe HBTs. The accuracy of the methods is evaluated by applying them to a sophisticated physics-based compact model, allowing to clearly detect and explain the causes for the observed inaccuracies or failures. The methods are then also applied to experimental data. In both cases, a large variety of device sizes have been investigated. This paper and its results provide insight into each method’s accuracy, its application limits with respect to a technology, device size, and operating range as well as its requirements in terms of equipment and extraction effort. [ABSTRACT FROM PUBLISHER]

This paper exhibits systematic results for lateral light emitting diodes (LEDs) with various conditions. The simulation results and circuit model are both included to describe the current spreading effect at the same time. A fully 2-D model that solves Poisson and drift-diffusion equations to investigate the current flow and radiative recombination distribution specifies the uniformity of the carrier distribution, which is combined with the Monte Carlo ray tracing technique to calculate the light extraction efficiency (LEE). This paper focuses on the modulation of the transparent conducting layer. In addition, this paper will discuss bottom emission LEDs addressing the current spreading effect and LEE compared with top emission LEDs. We also examine the droop effect to verify our discussion. A thorough analysis provides deep insights for achieving high efficiency lateral LEDs. [ABSTRACT FROM PUBLISHER]

This paper presents a circuit performance benchmarking using the large-signal model of graphene FET reported in Part I of this two-part paper. To test the model, it has been implemented in a circuit simulator. In particular, we have simulated a high-frequency performance amplifier, together with other circuits that take the advantage of the ambipolarity of graphene, such as a frequency doubler, an RF subharmonic mixer, and a multiplier phase detector. A variety of simulations comprising dc, transient dynamics, Bode diagram, S parameters, and power spectrum have been compared with experimental data to assess the validity of the model. [ABSTRACT FROM PUBLISHER]

Circuit-level models are developed to determine the upper bound on the performance of a 3-D IC link with through silicon vias (TSVs). It is shown that the performance of a 3-D link is limited not only by the on-chip interconnect RC, driver resistance, and TSV capacitance, but also by the current carrying capacity of the on-chip wires connecting the TSV to the input/output (I/O) driver. The models developed in this paper are used to optimize the I/O driver size, the number of on-chip wires connecting the TSV to the driver, and the data-rate to maximize the aggregate bandwidth per unit energy. Furthermore, in order to maximize the aggregate bandwidth of a 3-D link, it is shown that splitting the TSV array into smaller subarrays and placing the I/O drivers closer to the TSVs is better compared with having large TSV arrays. [ABSTRACT FROM AUTHOR]

This paper presents the wideband modeling and analysis of differential through-silicon vias (D-TSVs) in 3-D ICs. An equivalent-circuit model of the ground–signal–signal–ground-type D-TSVs is given and validated against a commercial full-wave electromagnetic simulation tool. The common- and differential-mode impedances are extracted using the partial-element equivalent-circuit method, while the admittances are calculated analytically, with the MOS effects considered and treated appropriately. The circuit model can also be used for studying the differential annular TSVs (ATSVs). It is shown that the ATSVs are more suitable for transmitting differential signals in comparison with the cylindrical TSVs. Based on the equivalent-circuit model, the characteristic impedances and the forward transmission coefficients of the D-TSVs made of Cu and carbon nanotubes are characterized and compared under different settings of frequencies and temperatures. [ABSTRACT FROM PUBLISHER]

In this paper, we identify the level shifter (LS) for voltage up-conversion from the ultralow-voltage regime as a key application domain of tunnel FETs (TFETs). We propose a mixed TFET–MOSFET LS design methodology, which exploits the complementary characteristics of TFET and MOSFET devices. Simulation results show that the hybrid LS exhibits superior dynamic performance at the same static power consumption compared with the conventional MOSFET and pure TFET solutions. The advantage of the mixed design with respect to the conventional MOSFET approach is emphasized when lower voltage signals have to be up-converted, reaching an improvement of the energy-delay product up to three decades. When compared with the full MOSFET design, the mixed TFET–MOSFET solution appears to be less sensitive toward threshold voltage variations in terms of dynamic figures of merit, at the expense of higher leakage variability. Similar results are obtained for four different LS topologies, thus indicating that the hybrid TFET–MOSFET approach offers intrinsic advantages in the design of LS for voltage up-conversion from the ultralow-voltage regime compared with the conventional MOSFET and pure TFET solutions. [ABSTRACT FROM PUBLISHER]

Performance of the crossbar memory array highly depends on the selector characteristics. In this paper, rigorous transient analyses are performed for a large-size crossbar memory array using novel NbO2-based selectors with a threshold switching behavior. To enable accurate and efficient array-level simulation, an electrostatic discharge-based compact model is employed to effectively describe the ${I}$ – ${V}$ characteristics of the selector. Multiple key design parameters of the selector are investigated, such as the threshold voltage, leakage current, and intrinsic switching speed. A sensitivity analysis is performed to evaluate the impact of hypothetical improvements in various selector parameters. In addition, the impacts of resistances of interconnect and memory element on the array-level access delay and energy dissipation are quantified. The results show that reducing the threshold voltage of selectors provides the most significant performance improvement, where up to 80% of the energy-delay product saving is observed if the threshold voltage is reduced by 50%. [ABSTRACT FROM AUTHOR]

A W-band extended interaction oscillator (EIO) operating at two different types of $2\pi $ modes is presented. The modes and output characteristics were studied, and the circuit was optimized to ensure similar and efficient outputs of two standing-wave modes. For a cylindrical electron beam radius of 0.2 mm, voltage of 14 kV, and current of 0.5 A, particle-in-cell simulation predicts 616 W at 93.76 GHz for the $2\pi $ gap mode and 367 W at 94.22 GHz for the $2\pi $ cavity mode. In this paper, numerical simulations demonstrate the ability of the EIO circuit to be operated with two standing-wave modes in the millimeter-wave range. [ABSTRACT FROM AUTHOR]

In this paper, we present an effective switching current model ( I\textsf {eff} ) for inverter followed by a transmission gate structure (Inv-Tx) based on its switching trajectory. Unlike an inverter or NAND/NOR gates, where I\textsf {eff} depends only on nMOSFET (pMOSFET) current for a falling (rising) transition, it is a function of both nMOSFET and pMOSFET currents for an Inv-Tx cell. The proposed model is verified against HSPICE simulations for a wide range of supply voltages and fan-outs at different technology nodes (e.g., 180, 130, and 65 nm). The model predicts the transition delay values with an average (maximum) error of 7% (11%) compared with HSPICE simulations. Synopsys TCAD Sentaurus simulations at 32-nm technology node are also used to validate the basic model assumptions. To demonstrate the utility of our model, design of some representative circuits while incorporating layout-dependent effects and inverse-narrow-width effect is presented. Finally, we show that a 256X1 multiplexer and a static D-flip-flop, with their transistor sizes and layout, optimized using the proposed model improves the performance of these circuits significantly over the conventional design methodologies. [ABSTRACT FROM PUBLISHER]

In this paper, we use an automated tool flow in a 14 nm CMOS fin-shaped field-effect transistor (FinFET)/ static random access memory (SRAM) simulation-based design-technology cooptimization (DTCO) including both process-induced and intrinsic statistical variabilities. A 22 nm FinFET CMOS technology is used to illustrate the sensitivity to process-induced fin shape variation and to motivate this paper. Predictive Technology Computer Aided Design (TCAD) simulations have been carried out to evaluate the transistor performance ahead of silicon. Draft-diffusion simulations calibrated to the ensemble Monte Carlo simulation results are used to explore the process and the statistical variability space. This has been enabled by the automation of the tool flow and the dataset handling. The interplay between the process and the statistical variability has been examined in details. A two-stage compact model strategy is used to capture the interplay between process and statistical variability. To close the DTCO loop, the static noise margin and write noise margin sensitivity to cell design parameters and variability in FinFET-based SRAM designs are studied in details. [ABSTRACT FROM AUTHOR]

An equivalent-circuit model of shield differential through-silicon vias (SDTSVs) in 3-D integrated circuits (3-D ICs) is proposed in this paper. The proposed model is verified using the 3-D full-wave field solver High Frequency Simulator Structure, showing that it is highly accurate up to 100 GHz. Furthermore, a full-wave extraction method for the resistance–inductance–capacitance–conductance (RLCG) parameters of SDTSVs is also proposed in this paper, which can be applied to all of differential transmission lines. It is shown that the results of the RLCG parameters obtained from the full-wave extraction method agree well with that from the analytical calculation up to 100 GHz, further validating the accuracy of the proposed model. Finally, using the proposed model, a deep analysis of electrical characteristics of SDTSVs is carried out to provide helpful design guidelines for them in future 3-D ICs. [ABSTRACT FROM AUTHOR]

This paper presents an extended model for transient and ac circuit-level simulation of minority carriers propagation through the substrate of smart power integrated circuits (ICs). A p-n junction and a diffusion resistor with capacitive components are proposed to efficiently simulate transient parasitic coupled currents in high-power stages. From a general chip layout, an equivalent substrate network including capacitive effects (junction and diffusion capacitances) can be extracted and parasitic bipolar transistor can be simulated for the first time in transient operation by circuit simulators once the minority carriers continuity conditions are satisfied. This paper shows simulation results of the implemented models in good agreement with those obtained from technology computer-aided design. This implies that transient layout dependent mechanisms between high-voltage aggressor wells and low-voltage victims can be verified in early stages of IC design flow. [ABSTRACT FROM AUTHOR]

3-D integrations are unavoidable task for new emerging memories, including resistive switching random-access memory (RRAM), in order to overcome the market-leading nand flash. However, an RRAM crossbar array (CBA) suffers severe read margin degradation due to the sneak current, which becomes even more critical as the memory density increases with the 3-D integration. In this paper, we extend the two-port readout scheme for a 2-D CBA, proposed in our previous work, to the 3-D vertical structure. A closed-form expression of the operating principle is derived, and HSPICE simulation using a $32\times 32\times8$ vertical RRAM CBA considering practical circuit parameters verifies feasibility of the two-port scheme to the 3-D CBA. [ABSTRACT FROM AUTHOR]

In this paper, we present a capacitance model for field-plate AlGaN/GaN High Electron Mobility Transistor (HEMTs) accounting for the contribution of substrate capacitances and cross-coupling between field plates. TCAD simulations are performed to analyze both these contributions and analytical expressions for charges corresponding to the cross-coupling and substrate capacitances are presented in terms of our existing surface-potential-based model. The modeled results are validated by comparing the time-domain waveforms of a test circuit using a mixed-mode simulation setup in which the impact of cross-coupling and substrate capacitances on accuracy of switching transients predicted by the model is discussed. [ABSTRACT FROM AUTHOR]

This paper describes a novel compact model for a SiC-MOSFET. The model is useful to achieve accurate simulation of output characteristics from a linear region to a saturation region, selecting both gate–source voltage and temperature as parameters. In order to construct the model systematically, attention is paid to a physics-based modeling procedure with channel mobility as an adjustable parameter. The model also features characterization and modeling of an internal drain–gate capacitor. The model shows fairly good agreement in the output characteristics and the dynamic behavior of both gate drive circuit and main power circuits between the experimental and simulated results. This successful validation indicates that this model offers a promising circuit-based simulation tool for designing whole power conversion systems using SiC-MOSFETs. [ABSTRACT FROM AUTHOR]

The focus of this paper is to understand the impact of the material properties of GaN, exploited using a vertical device, in power switching by estimating switching loss. The study was performed with a cascoded current aperture vertical electron transistor (CAVET). The normally OFF device was simulated and analyzed using a Silvaco ATLAS 2-D drift diffusion model integrated to SPICE-based circuit simulator. Besides evaluating the performance space and, hence, potential application space for GaN CAVETs, this paper presents significant accomplishment in establishing a device to circuit model, thereby, offering a reliable method of evaluating GaN-based power transistors. The accuracy of the model was established through the excellent agreement of simulated data with the data sheet specs of a commercial cascoded GaN high electron mobility transistor. The model was successfully applied to compare SiC MOSFETs with GaN CAVETs. A cascoded GaN CAVET has $2\times $ faster switching time, $3\times $ lower switching loss compared with standard commercial SiC MOSFET, owing to the higher electron mobility in GaN. Operating at frequencies of megahertz with low power loss, a GaN CAVET will, therefore, lead to smaller converter size and higher system efficiency. [ABSTRACT FROM PUBLISHER]

In this paper, for the first time, we report a nonmonotonic dependence of the snapback voltage ( V\text {sb} ) on the buried oxide thickness ( t\text {BOX} ) in silicon-on-insulator laterally double-diffused MOS (SOI-LDMOS) transistors. Step-by-step analysis of this effect is carried out by decoupling the self-heating and impact-ionization effects that cause the turning ON of the parasitic bipolar junction transistor (BJT) and subsequently the snapback effect. It is observed that for LDMOS transistors with low t\text {BOX} , V\text {sb} increases with increase in t\text {BOX} due to reduction in drain current density as well as reduced impact ionization at higher lattice temperature. On the other hand, for high t\text {BOX} , V\text {sb} reduces with the increase in t\text {BOX} due to early switching ON of the parasitic BJT at higher temperature. Therefore, it is possible to find an optimum value of t\text {BOX} to obtain the highest V\text {sb} for an SOI-LDMOS transistor. An interesting observation is that with proper choice of t\text {BOX} , the safe operating area in SOI-LDMOS can be more than that of the corresponding bulk-LDMOS. A physics-based compact model is developed and implemented in Verilog-A. When compared with the Technology Computer Aided Design simulated results, our model exhibits high level of accuracy. [ABSTRACT FROM PUBLISHER]

The spin-transfer torque domain wall (DW) magnetic tunnel junction (MTJ) enables spintronic logic circuits that can be directly cascaded without deleterious signal conversion circuitry and is one of the only spintronic devices for which cascading has been demonstrated experimentally. However, experimental progress has been impeded by a cumbersome modeling technique that requires a combination of micromagnetic and SPICE simulations. This paper, therefore, presents a SPICE-only device model that efficiently determines the DW motion resulting from spin accumulation and calculates the corresponding MTJ resistance. This model has been validated through comparison to the authoritative micromagnetic-based model, enabling reliable prediction of circuit behavior as a function of device parameters with a 10 000 $\times $ reduction in the simulation time. This model thus enables deeper device and circuit investigation, advancing the prospects for nonvolatile spintronic computing systems that overcome the von Neumann bottleneck. [ABSTRACT FROM AUTHOR]

This paper focuses on the modeling of the avalanche multiplication coefficient in state-of-the-art SiGe:C HBTs suffering from radical self-heating and impact-ionization effects. Experimental data are measured in a wide current range on devices fabricated during the DOTFIVE project and used as a reference. A comparative analysis of the available empirical descriptions for the avalanche coefficient is made at low current density; the best model is then extended to account for medium/high-current effects by resorting to a suitable parameter optimization methodology. The same procedure is adopted to examine the accuracy of physics-based formulations implemented in advanced transistor models for circuit design. [ABSTRACT FROM AUTHOR]

This paper investigates the RF intermodulation characteristics of transistors from a 14-nm RF FinFET technology using experimental measurements, circuit simulation with Berkeley short-channel IGFET model-common multi-gate (BSIM-CMG), and Volterra series. Linearity sweet spots with respect to gate voltage and RF power, as well as its drain voltage dependence, are examined. Key BSIM-CMG model parameters required for simultaneous fitting of dc I–V, S-parameters, and intermodulation distortion are identified and demonstrated. Volterra series analysis shows that distortion resulting from ${V}_{\textsf {DS}}$ derivatives of ${I}_{\textsf {DS}}$ dominates at most biases. A minimum third-order intercept gate voltage ${V}_{\textsf {GS,IP3}}$ of 0.5 V is observed, compared with 0.7 V in a 28-nm high- ${k}$ metal-gate planar device. [ABSTRACT FROM AUTHOR]

Although spin transfer torque (STT)-based magnetic tunneling junction (MTJ) owns advantages of nonvolatility, nonlimited endurance, and fast write/read, its demand for high current density significantly casts a shadow over its future prospects. Recently, a novel three-terminal MTJ cell that combines voltage-controlled magnetic anisotropy (VCMA) effect and negative capacitance (NC) effect is proposed. Drawing support from the NC amplified VCMA effect and the three-step operation scenario, this novel MTJ cell can dramatically lower the energy consumption to fJ as well as keep high operation speed within nanoseconds. The feasibility of the proposed NC enhanced VCMA spintronics device for memory and logic application is proved by extensive physical simulation in our previous work. However, a SPICE compatible compact model of the proposed NC enhanced VCMA spintronics device is still demanded for circuit and system level evaluation. In this paper, we provide an accurate and fast compact model of NC enhanced VCMA device for both memory and logic applications. [ABSTRACT FROM AUTHOR]