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This paper reports an industry standard monolithic 555-timer circuit designed and fabricated in the in-house silicon carbide (SiC) low-voltage bipolar technology. This paper demonstrates the 555-timer integrated circuits (ICs) characterization in both astable and monostable modes of operation, with a supply voltage of 15 V over the wide temperature range of 25 °C–500 °C. Nonmonotonic temperature dependence was observed for the 555-timer IC frequency, rise time, fall-time, and power dissipation. [ABSTRACT FROM AUTHOR]

Technology computer-aided design (TCAD) is an integral part of the development process of semiconductor technologies and devices, a field which has become increasingly complex and heterogeneous. Processing of integrated circuits requires nowadays over 400 process steps, and the resulting devices often have an intricate 3-D structure and contain various specifically designed materials. The full device behavior can only be understood by considering effects on all length scales from atomistic (material properties, interfaces, defects, and so on), to nanometric (quantum confinement, non-bulk properties, tunneling, ballistic transport, and so on), to full-chip dimensions (strain, heat transport, and so on), and time scales from femtoseconds (scattering, ferroelectric switching time, and so on) to seconds (trapping times, degradation, and so on). Voltages, currents, and charges have been scaled to such low levels that statistical effects and process variations have a strong impact. Devices based on new materials (e.g., 2-D crystals) and physical principles (ferroelectrics, magnetic materials, qubits, and so on) challenge standard TCAD approaches. While the simulation methods developed by the physics community can describe the basic device behavior, they often lack important simulation capabilities like, for example, transient simulations or integration with other TCAD tools, and are often too slow for daily use. Due to the complexity of semiconductor technology, it becomes more and more difficult to assess the impact of a change in processing or device structure on circuit performance by looking at a single aspect of an isolated device under idealized conditions. Instead, a TCAD tool chain is required which can handle realistic device structures embedded in a chip environment. New methodologies are required for all aspects of TCAD to ensure an efficient tool chain covering from atomistic effects to circuit behavior based on flexible simulation models that can handle new materials, device principles, and the ensuing large-scale simulations and that make use of artificial intelligence for well-chosen (sub)routines to decrease the overall simulation time. This Special Issue features six invited and 18 regular papers that address these problems. [ABSTRACT FROM AUTHOR]

In negative capacitance field-effect transistors (NCFETs), drain current may decrease with increasing ${V}_{\mathrm {ds}}$ in the saturation region, leading to negative differential resistance (NDR). While NDR is useful for oscillator design, it is undesirable for most analog circuits. On the other hand, the tendency toward NDR may be used to reduce the normally positive output conductance ( ${g}_{ \mathrm {ds}}$ ) of a short-channel transistor to a nearly zero positive value to achieve higher voltage gain. In this paper, we analyze the NDR effect for NCFET in the static limit and demonstrate that it can be engineered to reduce ${g}_{\mathrm {ds}}$ degradation in short-channel devices. Small and positive $g_{\mathrm{ ds}}$ is achieved without compromising the subthreshold gain, which is crucial for analog applications. The 7-nm ITRS 2.0 FinFET with 0.7 V ${V}_{\mathrm {dd}}$ is used as the baseline device in this paper. [ABSTRACT FROM AUTHOR]

This paper demonstrates a novel nanofabrication technology for producing high-density gated molybdenum (Mo) field-emitter array (FEA) based on modified nanosphere lithography (NSL). The arc-shaped side wall of gate apertures introduced by the conventional NSL process put obstacles in the formation of sharp cone-type emitters. In this paper, a two-method solution was employed to facilitate the realization of gate apertures with sharper cutting side wall which are beneficial for the formation of sharper gated Mo emitters. One method was softening nanosphere to enlarge the contact area between nanosphere and substrate. The other was optimizing gate film deposition conditions to dramatically reduce the diffraction effects. Due to the improvements in the geometrical shape of gated Mo emitters, a low-voltage working high-density gated Mo FEA was demonstrated in this paper. This is the first observation of remarkable electron emission from high-density gated Mo FEA fabricated using such as low-cost, high-throughput, and high-efficiency technique which is expected to substantially overcome the challenges in the traditional fabrication process and promotes the low-cost and large-area application of high-density gated field-emitter devices. In addition, the novel nanofabricating method is expected to offer a simple and scalable route which allows fabrication of many gated field-emission devices. [ABSTRACT FROM AUTHOR]

In this paper, we present a comprehensive study of multisection, velocity-tapered slow wave structures (SWSs) for highly efficient backward-wave oscillators (BWOs). The SWS velocity variation profiles are characterized by mathematical functions. Using particle-in-cell (PIC) simulations, the efficiencies of these SWSs are obtained along with their oscillation frequency response to variations in beam voltage. This paper is aimed at determining the optimum SWS profiles for high-efficiency BWO operation along with the corresponding tunability. The profile with the highest possible efficiency is fabricated and cold tested to experimentally determine and validate the underlying efficiency enhancement mechanisms. This resulting cold test experiment demonstrates higher order dispersion in the form of multiple secondary inflection points. PIC simulations using this SWS design predict an output power of 8.25 MW at 2.62 GHz corresponding to a peak power conversion efficiency of 70%. [ABSTRACT FROM AUTHOR]

In this paper, an innovative process flow developed to improve the thermal resistance of power ICs was presented. In this field, one of the major device failure mechanisms is related to the high temperatures reached during the working cycles due to the extremely critical electrical current densities. Therefore, heat transfer and dissipation are crucial aspects that need continuous improvements. Usual approaches to face this issue deal with package heat sinks design, solder selection, and wafer thinning. In this paper, a novel technological approach was settled, in which heat sinks microstructures were successfully integrated at wafer level stage on standard p-i-n diodes. To this aim, the bulk Si on the backside was partially replaced with Cu, a material characterized by a higher thermal conductivity material. Moreover, the well microstructures filled by Cu provide the advantage of wafer self-support, without requiring dedicated and more expensive thinning and handling technologies. An extensive characterization of the final devices was also carried out to evaluate the process and the thermal and electrical improvements. Finally, a failure analysis on selected devices was performed to identify any critical issue with the standard packaging process. [ABSTRACT FROM PUBLISHER]

Integrated circuits operated in the near-threshold region exhibit specific merit with high energy efficiency. A near-threshold model is highly required for the circuit design. In this paper, a near-threshold drain current model is proposed based on the surface inversion layer charge model for analyzing digital circuits. The short-channel effect in deep submicrometer is also included in the model. Moreover, the delay and energy parts based on the near-threshold drain current model are derived and integrated in the model. Two process design kits (PDKs) are used for parameter extraction to demonstrate the feasibility of the proposed model. The results show that the proposed model can be used for the near-threshold circuit calculation, with the benefit of high accuracy. [ABSTRACT FROM AUTHOR]

This paper examines metal–ferroelectric–insulator–semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse Vds-dependence of threshold voltage (VT), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low VDD. [ABSTRACT FROM AUTHOR]

Oxide semiconductors are highly attractive for fabrication of large-area thin-film electronics because of their high electrical performance, low process temperature, high uniformity, and ease of industrial manufacturing. n-type oxide semiconductors, such as InGaZnO, are highly developed and have already been commercialized for backplane drivers of flat-panel displays. To date, developing CMOS technology is still an urgent issue in order to build low-power electronic circuits based on oxide semiconductors. In this paper, various CMOS circuits, including inverters, NAND, NOR, XOR, d-latches, full adders, and 7-, 11-, 21-, and 51-stage ring oscillators (ROs), are fabricated based on sputtered p-type tin monoxide and n-type InGaZnO. The inverters show rail-to-rail output voltage behavior, low average static power consumption of 8.84 nW, high noise margin level up to ~40% supply voltage, high yield of 98%, and high uniformity with negligible standard deviation. The NAND, NOR, XOR, d-latches, and full adders show desirably ideal input–output characteristics. The performances of ROs indicate small stage delay of $\sim 1~\mu \text{s}$ , extremely high uniformity and high yieldwhich are essential for large-area thin-film electronics. This paper may inspire constructions of low power, large area, large scale, and high-performance transparent/flexible CMOS circuits fully based on oxide semiconductors for applications beyond flat-panel displays. [ABSTRACT FROM AUTHOR]

The state-of-the-art RF and millimeter-wave circuits design requires accurate prediction of the nonquasi-static (NQS) effects at high frequency for all levels of channel inversion. This paper provides a practical insight to help high-frequency performance assessment of ultrathin body and box fully depleted silicon-on-insulator MOSFETs through a powerful frequency normalization scheme. Frequency dependence of small signal characteristics derived from experimental S-parameters is analyzed and reveals that the transconductance efficiency (${g}_{\textsf {m}}/{I}_{\textsf {D}}$) concept, already adopted as a low-frequency analog figure-of-merit (FoM), can be generalized to high frequency, including under asymmetric operation. We report that the normalized frequency dependence of the generalized transadmittance efficiency (${y}_{\textsf {m}}/{I}_{\textsf {D}}$) FoM only depends on the mobility and inversion coefficient. In addition, this approach is also used to extract essential parameters such as the critical NQS frequency ${f}_{\textsf {NQS}}$. [ABSTRACT FROM AUTHOR]

Variability is a challenge for future scaling as process dimensions reduce. The emerging 3-D sequential stacking technology is more than Moore’s scaling alternative. The 3-D design flow requires the partitioning of the netlist between the tiers. This paper presents the variability analysis of circuits partitioned into different levels. A comparison among local and global variations effects on ring oscillators (ROs) and SRAM is demonstrated. The across-chip variations and correlation range are shown as a critical point for the 3-D very large-scale integrated circuits, where the local variability is dominant. The correlations between devices due to the distances or the allocation into different tiers are directly taken into account in the SPICE model due to a statically unified model applied to 3-D circuits based on Monte Carlo simulations. Design wise, the 3-D integration can further decrease the circuit variability as shown in RO output frequency and SRAM static noise margin. [ABSTRACT FROM AUTHOR]

With the aid of an analytical and general model, this paper investigates the intrinsic difference in the negative-capacitance (NC) effect and design space between semiconductor-on-insulator (SOI) and double-gate (DG) metal–ferroelectric–insulator–semiconductor-type NC field-effect transistors (NCFETs) with a 2-D semiconducting transition-metal-dichalcogenide channel (2-D NCFET). By examining the distributions of internal charge, voltage gain, and capacitance matching over the whole bias range, the intrinsic difference in NC effects between these two topologies is pointed out and explained. Our study indicates that for an intrinsic DG 2-D NCFET, it is difficult to achieve sub-2.3 kT/q average subthreshold swing (SS). By contrast, the bias-dependent subthreshold internal charge and larger curvature of ferroelectric capacitance due to the independent backgate in the SOI 2-D NCFET enable larger design space and sub-2.3 kT/q average SS, making it more suitable for low-power applications. [ABSTRACT FROM AUTHOR]

In-memory computing architecture is an emerging revolutionary computing paradigm that can break the von Neumann bottleneck. Computing methodology and circuit codesign using the CMOS compatible 1T1R resistive random access memory (RRAM) integration structure is presented in this paper. Functionally complete Boolean logic and arithmetic functions are experimentally demonstrated. With a single 40-nm CMOS process 1T1R unit, each of the 16 binary logics can be realized in two logic steps with an additional readout step for cascading, which shows functional reconfiguration and low computational complexity. Up to 107 cycles of NAND and XOR logic operations are performed to validate the correctness and reliability. Moreover, several fundamental adder circuits are designed and experimentally demonstrated in 1T1R devices as the proof of concept of the 1T1R computing architecture. The adders proposed in this paper include a ripple-carry adder and its optimized design and a carry-select adder, which all show promising advantages in nonvolatility, computation speed, and circuit area. This paper reports the most complex yet efficient RRAM-based 8-bit addition function experimentally so far and lays a solid foundation for constructing the future in-memory computing architecture. [ABSTRACT FROM AUTHOR]

In this paper, we report on the assessment of self-amplified silicon–oxide–nitride–oxide–silicon (SONOS) memory device architecture for sub-50-nm gate length (${L}_{g}$) through calibrated simulations. Self-amplification (SA) effect in tunnel field-effect transistor-based SONOS (T-SONOS) memory device has been analyzed. Results show that memory window ($\Delta {W}$) in T-SONOS cell increases as buried oxide thickness increases due to capacitive coupling between the front and back gates. Although the enhanced $\Delta {W}$ can also be achieved in inversion-mode SONOS (I-SONOS) device, its performance is deteriorated when the gate length is scaled down. We have compared the performance of I-SONOS and T-SONOS memory devices for ${L}_{g}$ varying from 100 to 25 nm. Results highlight that I-SONOS device cannot be programmed at ${L}_{g} ={25}$ nm and thus deteriorate the memory operation. However, SA T-SONOS at ${L}_{g} = {25}$ nm achieves ${W} \sim {6}$ V. In addition, the effect of underlap on the performance of T-SONOS cell has been analyzed, and it is shown that memory operation of 25-nm T-SONOS device can further improved with a drain side underlap of 20 nm. This paper provides new opportunities to design SA T-SONOS memory device for the next-generation nonvolatile memories. [ABSTRACT FROM AUTHOR]

According to the thermal theory, the self-heating effect is equivalent to an R–C thermal equivalent circuit. Based on a small-signal equivalent circuit analysis, an analytical method to extract the thermal resistance and capacitance for RF silicon-on-insulator (SOI) MOSFETs is proposed in this paper. The geometry dependence of the thermal resistance and capacitance is investigated by using this method. The method is verified by using RF partial depletion-SOI process. The results show that the thermal resistance decreases and the thermal capacitance increases as the effective channel area increases. A simple equation to estimate the thermal characteristics is proposed to help optimize the device structure and circuit design for application. This method is easy to scale and adjust to devices with different dimensions and fabrication processes. [ABSTRACT FROM AUTHOR]

In this paper, we present a charge-based compact model for transition metal dichalcogenide (TMD)-based thin-channel field-effect transistor. In model development, first, charge densities at the source and drain terminals are calculated in terms of the applied gate and drain voltages. Calculated charge densities are then used to develop a charge-based drain-current model. Effects of interface traps, ambipolar current behavior, and negative capacitance are then included in the developed drain-current model in terms of charge densities. Predictions of the proposed model are verified by the simulation and experimental data of the TMD channel material-based n-type and p-type MOSFETs. [ABSTRACT FROM AUTHOR]

High-temperature integrated circuits provide important sensing and controlling functionality in extreme environments. Silicon carbide bipolar technology can operate beyond 500 °C and has shown stable operation in both digital and analog circuit applications. This paper demonstrates an 8-b digital-to-analog converter (DAC). The DAC is realized in a current steering R-2R configuration. High-gain Darlington current switches are used to ensure ideal switching at 500 °C. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) at 25 °C are 0.79 and 1.01 LSB, respectively, while at 500 °C, the DNL and INL are 4.7 and 2.5 LSB, respectively. In addition, the DAC achieves 53.6 and 40.6 dBc of spurious free dynamic range at 25 °C and 500 °C, respectively. [ABSTRACT FROM AUTHOR]

Circuit-level models are developed to determine the upper bound on the performance of a 3-D IC link with through silicon vias (TSVs). It is shown that the performance of a 3-D link is limited not only by the on-chip interconnect RC, driver resistance, and TSV capacitance, but also by the current carrying capacity of the on-chip wires connecting the TSV to the input/output (I/O) driver. The models developed in this paper are used to optimize the I/O driver size, the number of on-chip wires connecting the TSV to the driver, and the data-rate to maximize the aggregate bandwidth per unit energy. Furthermore, in order to maximize the aggregate bandwidth of a 3-D link, it is shown that splitting the TSV array into smaller subarrays and placing the I/O drivers closer to the TSVs is better compared with having large TSV arrays. [ABSTRACT FROM AUTHOR]

Performance of the crossbar memory array highly depends on the selector characteristics. In this paper, rigorous transient analyses are performed for a large-size crossbar memory array using novel NbO2-based selectors with a threshold switching behavior. To enable accurate and efficient array-level simulation, an electrostatic discharge-based compact model is employed to effectively describe the ${I}$ – ${V}$ characteristics of the selector. Multiple key design parameters of the selector are investigated, such as the threshold voltage, leakage current, and intrinsic switching speed. A sensitivity analysis is performed to evaluate the impact of hypothetical improvements in various selector parameters. In addition, the impacts of resistances of interconnect and memory element on the array-level access delay and energy dissipation are quantified. The results show that reducing the threshold voltage of selectors provides the most significant performance improvement, where up to 80% of the energy-delay product saving is observed if the threshold voltage is reduced by 50%. [ABSTRACT FROM AUTHOR]

The metal--insulator--semiconductor capacitor formed by a through-silicon via (TSV) with its insulating layer and the p-type Si substrate may show an anomalous inversion behavior in the C--V characteristic. The dominant cause is the presence of positive charges in the backside (BS) passivation layer. In this paper, a dedicated test structure is proposed and characterized to confirm this hypothesis. Furthermore, a charge-free oxide/nitride BS passivation layer for preventing the anomalous C--V inversion, proposed in our previous work, is validated by experimental results on TSV structures manufactured up to the complete BS metallization processing. [ABSTRACT FROM AUTHOR]

In this paper, the positive bias temperature instability (PBTI) of the tunnel thin-film transistor (TFT) is well studied and compared with the conventional-TFT. The tunnel-TFT exhibits superior PBTI immunity at high temperature and shows distinct temperature dependence of PBTI from the conventional-TFT. This is due to different influences of trap-state generation on electrical behavior of the two devices. For the poly-Si tunnel-TFT featuring trap-assisted tunneling (TAT), the impact of trap-state generation on tunneling probability is found to be temperature dependent. At lower temperature, the TAT current of a tunnel-TFT is reduced due to the lower interband transition probability, resulting in pronounced temperature dependence on the additional generated trap states after electrical stress. Therefore, the worst PBTI behavior of a tunnel-TFT occurs when the device is stressed at low temperature. Our results may be helpful to further reliability investigation of tunneling devices. [ABSTRACT FROM AUTHOR]

A gate engineered InGaN dopingless tunnel FET (DL-TFET) using the charge plasma concept is proposed and investigated by silvaco Atlas simulation. In0.75Ga0.25N is a direct gap semiconductor, and the effective tunneling mass of electron and hole is smaller than that of silicon, which induces that the drain current and average subthreshold swing (SSavg) of InGaN DL-TFET improve 1.3 x 10² times and 51.1% than that of Si DL-TFET at the overdrive voltage of 0.5 V, respectively. What is more, better device performances are achieved by gate engineering with appropriate "In" fraction, proper space between the gate and source (Lgs), and appropriate tunneling gate work function (ΦTG). The direct-current, RF, and energy-efficient performance studies show that SSavg of 7.9 mV/dec, an on-state current (ION) of 8.02 x 10-5 A/µm, a cutoff frequency (fT) of 119 GHz, and an energy delay product of 0.64 fJ-ps/µm can be obtained in the proposed TFET. This paper indicates that the gate engineered InGaN DL-TFET is a promising TFET for low-power RF and digital logic applications. [ABSTRACT FROM AUTHOR]

With the development of novel device applications, e.g., in the field of Internet of Things or point-of-care personalized diagnostic systems, came an increased demand for MESFETs for fast and low-power consumption integrated circuits and active-matrix displays. In this paper, we present fabrication and characterization of transparent Ru–Si–O/In–Ga–Zn–O MESFETs on flexible substrates. The use of transparent conducting oxide, namely, Ru–Si–O, as Schottky gate electrode, allows for processing the devices at room temperature, enabling the utilization of such low-temperature substrates as polyethylene terephthalate foil and paper. It was shown that tuning the device geometry allows realization of transistors providing on-current up to 2 mA, while the highest on-to-off current ratio equals 2\times 10^\mathrm 5 , with off-current below 1 nA, carrier mobility in the channel exceeds 9 cm ^\mathrm 2\cdot \textV^\mathrm -1\cdot \texts^\mathrm -1 , and subthreshold swing is below 250 mV $\cdot $ decade ^{\mathrm { {-1}}} . [ABSTRACT FROM PUBLISHER]

For the experimental determination of the emitter resistance of bipolar junction transistors and HBTs, many methods exist in the literature, which yield quite different results though. In this paper, the most widely used methods are reviewed and applied to SiGe HBTs of different technologies and generations, including different device types (i.e., high-speed and high-voltage transistors). First, the accuracy of the methods is evaluated based on simulated data using a compact model. Explanations for causes of observed inaccuracy or failure are given and discussed. Second, suitable methods are applied to experimental data. In both cases, the results are compared for a large variety of device sizes. This paper and its results provide insight into each method’s accuracy; its application limits with respect to a technology, device size, and operating range; as well as its requirements in terms of equipment and extraction effort. A guideline for extracting the emitter resistance is also given. [ABSTRACT FROM AUTHOR]

This paper presents an extended model for transient and ac circuit-level simulation of minority carriers propagation through the substrate of smart power integrated circuits (ICs). A p-n junction and a diffusion resistor with capacitive components are proposed to efficiently simulate transient parasitic coupled currents in high-power stages. From a general chip layout, an equivalent substrate network including capacitive effects (junction and diffusion capacitances) can be extracted and parasitic bipolar transistor can be simulated for the first time in transient operation by circuit simulators once the minority carriers continuity conditions are satisfied. This paper shows simulation results of the implemented models in good agreement with those obtained from technology computer-aided design. This implies that transient layout dependent mechanisms between high-voltage aggressor wells and low-voltage victims can be verified in early stages of IC design flow. [ABSTRACT FROM AUTHOR]

Signal processing is fundamental to the modern information society. Sensing and signal processing of various biological signals using human body conformable flexible organic integrated circuits have been actively researched to enable continuous health condition monitoring via wearable devices. To amplify very small electrical biological signals from humans, high performance flexible organic amplifiers are required. In this paper, we briefly review the principles and recent progresses of printable organic amplifiers, including materials, processes, and circuits. [ABSTRACT FROM AUTHOR]

The proposed chord-fractal pattern has a significant impact on IC capacitor, increasing the capacitance within a limited chip area. To reduce the device area, this paper presents a modified fractal algorithm. This proposed algorithm uses various initiators to perform chord iteration on the unit cell. The iteration procedure automatically generates an area-saving fractal layout of IC capacitor. To verify the proposed algorithm, an area-saving device of chord-fractal is fabricated using UMC 0.18- \mu \textm CMOS technology. [ABSTRACT FROM PUBLISHER]

In this paper, a novel design approach is proposed for on-chip bandpass filter (BPF) design with improved passband flatness and stopband suppression. The proposed approach simply uses a combination of meander-line structures with metal–insulator–metal (MIM) capacitors. To demonstrate the insight of this approach, a simplified equivalent LC-circuit model is used for theoretical analysis. Using the analyzed results as a guideline along with a full-wave electromagnetic (EM) simulator, two BPFs are designed and implemented in a standard 0.13- $\mu \text{m}$ (Bi)-CMOS technology. The measured results show that good agreements between EM simulated and measured results are achieved. For the first BPF, the return loss is better than 10 dB from 13.5 to 32 GHz, which indicates a fractional bandwidth (FBW) of more than 78%. In addition, the minimum insertion loss of 2.3 dB is achieved within the frequency range from 17 to 27 GHz and the in-band magnitude ripple is less than 0.1 dB. The chip size of this design, excluding the pads, is 0.148 mm2. To demonstrate a miniaturized design, a second design example is given. The return loss is better than 10 dB from 17.3 to 35.9 GHz, which indicates an FBW of more than 70%. In addition, the minimum insertion loss of 2.6 dB is achieved within the frequency range from 21.4 to 27.7 GHz and the in-band magnitude ripple is less than 0.1 dB. The chip size of the second design, excluding the pads, is only 0.066 mm2. [ABSTRACT FROM AUTHOR]

In this paper, a through-silicon via (TSV) array under Gaussian pulse is studied comprehensively with a rigorous consideration of its electrothermal characteristics. To enhance the computational efficiency and reduce the memory cost, we develop a unified radial point interpolation method (RPIM) to handle these TSV electrothermal coupling problems. The comparison between the results of the proposed formulas and fine-grid finite-element method (FEM) shows that the RPIM has a very high accuracy and reduces computational time by up to 88% in comparison with the fine-grid FEM. The transient temperature responses are studied in detail for three layouts of single-layered TSV arrays with different silicon dioxide layer thicknesses and areas enclosed by TSVs. Furthermore, the two-layered TSV array structure including microbumps and RDLs is simulated electrothermally to verify the scalability of this method. Our work demonstrated the capability of addressing a large number of TSV arrays and the proposed method enables faster and more accurate electrothermal design of TSV-based 3-D ICs. [ABSTRACT FROM AUTHOR]

In this paper, we will focus on the problem of modeling global or die-to-die variation in semiconductor devices. We will demonstrate that the process corner-based approach for modeling global variation, which has been the dominant approach for design validation, has fundamental limitations in predicting the circuit performance variation. We will then show how a full statistical model of variation can accurately predict circuit behavior and discuss some of the challenges in moving from a corner-based design to statistical simulations. [ABSTRACT FROM AUTHOR]

This paper presents a partially pixel-parallel digital readout integrated circuit that overcomes the limitation of achievable digital resolution seen in megapixel-format infrared digital focal plane arrays (IR-DFPAs). It incorporates 5-bit in-pixel pulse frequency modulation (PFM)-based charge-to-digital converters and 10-bit successive approximation register (SAR) column analog-to-digital converters (ADCs). To increase the readout resolution, the residue charge at the end of the integration phase is fine converted to a 10-bit digital word and combined with the in-pixel data. This method is a compromise between fully pixel-parallel and fully column-parallel conversion approaches and favors the ever-growing trend toward small pitch FPAs by allowing a compact pixel size. A prototype consisting of a $32\times32$ array of pixels, 32 column SAR ADCs, and a timing controller block is designed and fabricated in a 90-nm bulk CMOS process. A modified version of the conventional PFM-based pixel is designed to help hold the residue charge. The design is targeted at medium-wave IR-DFPAs with frame rates up to 400 Hz. A signal-to-noise ratio of 79 dB is achieved with a full-well capacity of 2.4 Me-. [ABSTRACT FROM AUTHOR]

In this paper, a new continuous multilevel compact model for phase-change memory (PCM) is proposed. It is based on the modified rate equations with the introduction of a variable related to material melting. The model is evaluated using a large set of dynamic measurements and shows a good accuracy with a single model card. All fitting parameters are discussed, and their impacts are detailed. Full circuit simulation is performed. Good convergence and fast simulation time suggest that this new compact model can be exploited for PCM circuit design. [ABSTRACT FROM AUTHOR]

Full-band atomistic quantum transport simulations based on first principles are employed to assess the potential of band-to-band tunneling FETs (TFETs) with a 2-D channel material as future electronic circuit components. We demonstrate that single-layer (SL) transition metal dichalcogenides are not well suited for TFET applications. There might, however, exist a great variety of 2-D semiconductors that have not even been exfoliated yet; this paper pinpoints some of the most promising candidates among them to realize highly efficient TFETs. SL SnTe, As, TiNBr, and Bi are all found to ideally deliver ON-currents larger than 100 $\mu \text{A}/\mu \text{m}$ at 0.5-V supply voltage and 0.1 nA/ $\mu \text{m}$ OFF-current value. We show that going from single to multiple layers can boost the TFET performance as long as the gain from a narrowing bandgap exceeds the loss from the deteriorating gate control. Finally, a 2-D van der Waals heterojunction TFET is revealed to perform almost as well as the best SL homojunction, paving the way for research in optimal 2-D material combinations. [ABSTRACT FROM AUTHOR]

Aggressively scaled devices with high power density wrapped around the low thermal conductivity material in narrow space are susceptible to self-heating effect, which includes serious mutual-heating due to proximity effect in multifinger/fin FETs. Obtaining local temperature instead of equivalent lumped temperature at device/circuit level quickly is crucial for designers to accurately predict front-end-of-line reliability (i.e., hot carrier injection, bias temperature instability, and time dependent dielectric breakdown) and achieve better thermal management. In this paper, we: 1) first propose an analytical model based on multistage thermal network to address effectively the self- and mutual-heating within the device; 2) validate the multistage network and proposed analytical model by COMSOL and SPICE simulation, respectively; and 3) utilize the model to investigate local temperature rise in multifinger and multifin FETs-based inverter and ring oscillator as well as provide thermal-aware IC design guideline for self-heating and reliability optimization. The results show that the analytical multistage thermal model can predict local temperature rise and quantify nonuniform temperature difference in full-frequency range, superior to the lumped thermal model. Moreover, the model can offer quick thermal analysis at the pre-Si stage for reliability prediction and thermal-aware design. [ABSTRACT FROM AUTHOR]

In this paper, the feasibility of a low-temperature polysilicon (LTPS) microscale energy harvester for a wireless sensor node is investigated. For that purpose, two device-level models for the LTPS solar cell and thin-film transistors are proposed and employed in system-level evaluation of an energy harvesting system. The results of our analysis indicate that: 1) the maximum power operating point for the solar cell is different when connected to a lossy power converter; 2) increasing the average grain size of the LTPS film can reduce the circuit area by 20 times, while increasing the output power by 6%; and 3) the proposed bottom–up approach enables the designers to identify system bottlenecks and improve the performance accordingly. [ABSTRACT FROM AUTHOR]

The effects of the internal gain originated from the trapping of minority carriers and illumination-induced stored charges have been investigated systematically in MgZnO metal–semiconductor–metal (MSM) photodetectors (PDs) by a proposed semianalytical equivalent circuit model with the basic semiconductor equations and the external parasitic elements taken into account. To verify the accuracy and effectiveness of this model, the simulated steady and transient results are compared with the reported experimental data. It is found that a fall time of 400 ns, much longer than the response time with no internal gain, is attributed to the hole trapping process, inducing an internal gain with a value of 181. In addition, for the high input optical pulse energy (above 10 pJ), the time-delay of the response is caused by the stored charges. This paper indicates that it is very important to improve the MgZnO thin-film quality and balance the optical gain with the response speed. Meanwhile, a reasonable compromise should be found between the energy level of the optical pulse and the bias voltage to minimize the stored charges effect for practical applications. This paper is helpful for the design of high-speed and high-power MgZnO MSM PDs. [ABSTRACT FROM AUTHOR]

This paper analyzes the impact of liquid cooling on the electrical characteristics of through-silicon vias (TSVs) using a microfluidic cooling testbed containing TSVs. The microfabrication of TSVs in a silicon micropin-fin heat sink is presented, and the high-frequency characterization of TSVs within a micropin-fin heat sink using distilled water is performed from 10 MHz to 20 GHz. TSV capacitance and conductance are extracted from measurements; TSVs within distilled water have larger capacitance and conductance than TSVs in silicon due to the lossy characteristics of distilled water at high frequencies. A coaxial-like TSV configuration, which consists of multiple ground TSVs surrounding a center signal TSV, is proposed and demonstrated to shield signal TSVs from the coolant. [ABSTRACT FROM PUBLISHER]

This paper presents a systematic methodology to design efficient sub-90-nm split-gate Flash-memory cells and optimize the cell performance within the presently known scaling constraints. The device-simulation results show that the high-performance sub-90-nm split-gate cells can be realized by a proper optimization of the channel and asymmetric halo-doping profiles and shallow source/drain junctions. In this paper, the halo- and channel-doping profiles were optimized to achieve the target drain-programming voltage Vsp = 6.5 V for an efficient cell programming, whereas keeping the breakdown voltage BV > Vsp with tolerable leakage currents. It is shown that, using the properly optimized technology parameters, 65-nm split-gate Flash memory can be achieved with cell-read current, Ir1 ≈ 235 μA/μm, programmed cell-leakage current, Ir0 < 2.2 nA/μm at the read condition, time-to-program ≈30 μs, and time-to-erase ≈40 μs. This paper clearly demonstrates the feasibility of high-performance 65-nm split-gate Flash-memory cells. [ABSTRACT FROM AUTHOR]

In this paper, bias modulated synapse transistor based on ultrathin molybdenum disulfide (MoS2) was fabricated. By applying positive and negative pulses, the device can imitate the excitation and inhibition behaviors of natural synapse, respectively. The baseline and change percentage of postsynaptic current (PSC) can be tuned by the back-gate bias, enabling the reconfiguration of the weight profile in machine learning. The PSC change tendency between single pulse and multiple pulse tests is opposite, which is very useful to mimic natural synapse recovery feature. Besides, as MoS2 is utilized as channel materials, the device can be vertically scaled down to 2 nm, which is very hard for traditional materials. [ABSTRACT FROM AUTHOR]

Power consumption of today’s integrated circuit is very difficult to reduce because the MOSFET is subjected to the thermal limit of 60 mV/decade for the subthreshold swing (SS). In this paper, we show that this SS limit of thermionic current can be conquered—thus power consumption drastically reduced by density of states (DOS) engineering at the source. Specifically, the linear DOS of Dirac electrons at the source concomitant with an efficient gate control brings the SS limit down to 37 mV/decade, and further down to very small values by suppressing the thermal tail contribution with a small bandgap in the injected DOS. Using the first principles analysis, we demonstrate that FETs with Dirac source to possess extremely promising device performance in both energy dynamic power and switching speed at the ultralow operating voltage regime of 0.3 V compared with ultrathin-body Si FETs. [ABSTRACT FROM AUTHOR]

In this paper, the first demonstration of a bow-tie antenna integrated with a metal–insulator–metal (MIM) diode for electromagnetic energy harvesting in the ${V}$ -band (i.e., 40–75 GHz) is presented. We have designed, simulated, fabricated, and fully characterized a 60-GHz rectifying antenna (rectenna) based on a vertical Au-HfO2-Pt MIM diode with reduced differential resistance. The dielectric used for the MIM structure is a 6-nm-thick amorphous HfO2 grown by atomic layer deposition. For the fabricated MIM device, we report here a current density of ${3} \times {10}^{ {4}}$ A/cm2 that exceeds the previous values presented in the literature. The vertical MIM-based rectenna is able to efficiently harvest up to $250~\mu \text{V}$ from an impinging modulated millimeter-wave signal with −20 dBm of available power, thus offering a voltage responsivity of over 5 V/W. The reported results indicate that the proposed approach is well suited for future low-power solutions much sought after for the energetically autonomous 5G terminal equipment. [ABSTRACT FROM AUTHOR]

In this paper, we report about the derivation of a physics-based compact model of random telegraph noise (RTN) in HfO2-based resistive random access memory (RRAM) devices. Starting from the physics of charge transport, which is different in the high resistive states and low resistive states, we explore the mechanisms responsible for RTN exploiting a hybrid approach, based on self-consistent physics simulations and geometrical simplifications. Then, we develop a simple yet effective physics-based compact model of RTN valid in both states, which can be steadily integrated in state-of-the-art RRAM compact models. The RTN compact model predictions are validated by comparison with both a large experimental data set obtained by measuring RRAM devices in different conditions, and data reported in the literature. In addition, we show how the model enables advanced circuit simulations by exploring three different circuits for memory, security, and logic applications. [ABSTRACT FROM AUTHOR]

With shrinking transistor dimensions into sub-50-nm regime, statistical variability (SV) causes a great impact on the drain current and threshold voltage of nano-MOSFETs. In this paper, with emphasis on the propagation delay time of an inverter in 35-nm technology node, we have first introduced a strategy to take SV into account in four existing compact models using different number of statistical sets. For each model under study, we identified effective parameters of analytical equations which can be utilized to replicate the impact of SV. Moreover, we analyzed the statistical distribution and correlation of those effective parameters and their impact on the propagation delay time in each model. The results of these statistical CMs are compared with the accurate “atomistic” model, and it is shown that using this approach we can predict the propagation delay time standard deviation with less than 0.2%, 4.1%, 4.8%, and 4.7% errors in different models. However, the mean values of the propagation delay time stay almost constant even by employing statistical sets of single parameters. Furthermore, we study the impact of changing the load capacitance and the supply voltage on the statistical behavior of four models in the presence of SV. [ABSTRACT FROM AUTHOR]

In the double-drain multistate electrostatically formed nanowire transistor (MSET), the electrostatically formed conduction channel shifts laterally by properly biasing the two side gates that enclose the bulk area. This current switching mechanism enhances functionality within a single device and sets the stage for a family of integrated circuit building blocks that facilitate the implementation of ultralow-power Internet-of-Things applications. This paper establishes a conceptual framework for the MSET-based nand gate whose speed and power consumption are analyzed via TCAD simulations. [ABSTRACT FROM AUTHOR]

The diode operated under forward-biased condition has been widely used as an on-chip electrostatic discharge (ESD) protection device for high-speed circuits to sustain high ESD robustness, but the parasitic capacitance of diode may bring a negative impact to the circuits operating at higher speed. The ESD protection design with low parasitic capacitance has been strongly requested in high-speed I/O applications. The traditional methods to reduce parasitic capacitance were using a stacked diode or a stacked diode with embedded silicon-controlled rectifier (SCR). The stacked diode or the stacked diode with embedded SCR would have larger turn-on resistance to cause a higher clamping voltage. It should be further improved to achieve good ESD protection effectiveness for the high-speed I/O applications. In this paper, a new ESD protection device with reduced parasitic capacitance and smaller turn-on resistance to improve ESD protection effectiveness is proposed. The measurement results from the silicon chip have demonstrated that the proposed ESD device can achieve smaller parasitic capacitance, lower turn-on resistance, and higher ESD robustness, compared with the conventional devices. The proposed ESD protection device is very suitable to protect the high-speed I/O circuits in nanoscale CMOS technology. [ABSTRACT FROM PUBLISHER]

In this paper, the use of HfO2-based oxide-based resistive memory (OxRAM) devices operated in binary mode to implement synapses in a convolutional neural network (CNN) is studied. We employed an artificial synapse composed of multiple OxRAM cells connected in parallel, thereby providing synaptic efficacies. Electrical characterization results show that the proposed HfO2-based OxRAM technology offers good electrical properties in terms of endurance ( > 10^8 cycles), speed (<10 ns), and low energy (<10 pJ), and thus being well suited for neuromorphic applications. A device physical model is developed in order to study the variability of the resistance as a function of the stochastic position of oxygen vacancies in 3-D. Finally, the proposed binary OxRAM synapse has been used for CNN system-level simulations. High accuracy (recognition rate > 98%) is demonstrated for a complex visual pattern recognition application. We demonstrated that the resistance variability and the reduced memory window of the OxRAM cells when operated at extremely low programming conditions (<10 pJ per switching event) have a small impact on the performances of proposed OxRAM-based CNN (recognition rate 94%). [ABSTRACT FROM AUTHOR]

In this paper, a model of gate capacitance is proposed for ultrathin-body-BOX and double-gate MOSFETs with light mass channel materials. First, the model is derived by making the assumption that only one subband is occupied and using quantum perturbation theory to compute the corresponding energy level. Next, this model is confirmed with Poisson–Schrödinger simulations. Finally, the impacts in terms of performance and scaling are discussed. [ABSTRACT FROM AUTHOR]

Self-heating effect is the main contribution to the junction temperature in bipolar junction transistors. In this paper, the dc temperature-variation measurement and extraction method, including thermal-electric feedback coefficient of an InGaP/GaAs light-emitting transistor (LET), are presented. The thermal-electric feedback coefficient of the LET is −2.07 mV/K at collector current of 2 mA and the thermal resistance is 993.3 °C/W when the corresponding power dissipation is 44.19 mW. The thermal properties of the conventional heterojunciton bipolar transistor is also demonstrated and compared. The differences can be attributed to the quantum-well thermionic emission mechanisms and enhanced radiative recombination in the LET. [ABSTRACT FROM AUTHOR]

In thin-film transistor (TFT) logic circuit applications, propagation delay and power dissipation are two key constraints to be considered in optimal circuit design and synthesis. The unipolar zero- \(\textit {V}_\mathbf {GS}\) -load logic design is widely used for implementation of TFT digital circuits, because of the simple structure, easy processing, and relatively high gain. In this paper, the analytical models for delay and power were developed for zero- \(\textit {V}_\mathbf {GS}\) -load inverters, which clarify the relationships between device and design parameters and the two key design constraints. The proposed models were verified by circuit simulations, and could serve as a guideline for optimal design of unipolar zero- \(\textit {V}_\mathbf {GS}\) -load logic circuits. [ABSTRACT FROM AUTHOR]