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A fabrication and characterization of EEPROM devices with N-type or P-type floating gate was carried out. Program/erase speeds and stress-induced leakage current-related retention characteristics for both types of devices are explained.

A capacitorless, asymmetric double gate DRAM (DG-DRAM) technology is developed. The problems in the dopant fluctuation effects and off-state leakage are reduced due to the thin body structure of its double gate.

Scaling limits of alternative gate dielectrics are investigated and reported.

The impact of energy quantization on gate tunneling current for double-gate and ultrathin body MOSFETs is described. There is a discussion on the future gate dielectric thickness scaling and the use of high-k gate dielectrics.

The breakdown characteristics of the 3-D abrupt p-n junctions are modeled by an equivalent junction method. The work provided by the analytical model and its advantages are mentioned.

An analytical solution for a breakdown of the 6H-SiC parallel-plane junctions is presented. It is then used to optimize base width and based doping of punch-through junctions used in both unipolar and bipolar high voltage power devices.

A spacer patterning technology was developed for defining narrow-width silicon fins. This spacer technology provides high device density, shorter channel length and more uniform pattern size than optical and e-beam lithography.

Research into the measurement of tunneling currents through gate oxides is presented. A model which predicts electron tunneling from the conduction and valence band and hole tunneling from the valence band in CMOS systems is proposed.

A study of high performance PMOSFETs having sub-50-nm gate-length is reported.

The high-frequency noise characteristics of SOI low-noise amplifiers operating at 1.8-GHz under 1.5-V power supply are considered. It is concluded that floating-body SOI devices are more suitable for front-end amplifiers in RF receivers.

A characterization method for the self-heating effect in SOI MOSFET is presented. Rth and Cth are extracted using drain output conductance data at a chosen bias point and several frequencies.

A novel method of producing a germanium nanocrystal quasinonvolatile memory device is presented. This method has very good flexibility in oxide thickness control.

MOSFETS with gate length of 17 nm are described, and a novel self-aligned double gate FinFET is proposed.

A study was conducted on the use of shallow trench isolation in relation to hot-carrier reliability in metal oxide semiconductor field effect transistors (MOSFET). The experiment presents the channel width dependence of the hot-carrier reliability of pMOSFET with shallow trench isolation structure. Experimental methodology and results are discussed. A possible mechanism to account for the experimental results is also suggested.

A novel Ti-self-aligned silicide (SALICIDE) process for use in a sub-0.2 submicron complementary metal oxide semiconductor (CMOS) device and beyond using preamorphization implantation with antimony and germanium, instead of As, before Ti film sputtering, is described. Phase transformation is enhanced by preamorphization from C(sub 49)Ti(sub x)Si(sub x) to C(sub 54)TiSi2. Preamorphization also lowers the transformation temperature by 80 degrees C so that it takes place before agglomeration in narrow lines.

The role of gate engineering has become increasingly important in designing deep-submicron complementary metal oxide semiconductor (CMOS) transistors, thus, the increase in the number of issues concerning this matter. These include the effect of gate nitrogen implantation on the behavior and reliability of deep-submicron CMOS field effect transistors (CMOSFET's), the impact of gate microstructure on the performance of CMOSFET's and SiGe as a superior alternative gate material.

A robust physical non-quasi-static (NQS) metal oxide semiconductor field effect transistor model that can be used for small-signal ac and large-signal transient analysis is formulated. This model, which can be applied to existing simulators, utilizes a physical relaxation time approach. This model requires less time in predicting NQS behavior compared with common SPICE models and the PISCES numerical device simulator.

Delta-doped metal oxide semiconductor field effect transistors (MOSFETs) were developed using post-low-energy implanting selective epitaxy technology. In this study, MOSFETs characterized by a gate length of 0.1 micrometer were achieved by suppressing short-channel effects via the optimization of the channel doping level and epi-layer thickness. A significant reduction in junction capacitance at zero bias can be observed.

Mathematical analysis of gate oxide and voltage scaling in complementary metal oxide semiconductor (CMOS) has been performed to model and forecast ring oscillator propagation delay t(sub pd). Accurate drain saturation current I(sub dsat) predictions can be made using parasitic series resistance and velocity saturation studies. The relationships between I(sub dstat), CMOS gate speed, gate voltage, body bias, gate oxide thickness and channel doping concentration are established.

Plasma etching and ion implantation pose a problem to circuit reliability due to its damaging effect to gate oxides of MOS devices. A simulator was developed to predict oxide failure rates during and after processing and to locate strong charging current locations in the layout which allow changes to improve circuit hot-carrier reliability. The oxide reliability of a differential pair was also simulated.

The impact of a wide range of parameters on the high-field transport of inversion-layer electrons and holes was experimentally investigated. The studied parameters include substrate doping level, surface micro-roughness, vertical field strength, nitridation of the gate oxide and device channel length. Results indicated electron velocity overshoot at room temperature, dependence of electron and hole saturation velocities on nitridation of the gate oxide, dependence of the high-field drift velocity on the effective vertical field, and relative insensitivity of electron and hole mobility and saturation velocity to moderate surface roughness.