225 results on '"Hu, Chenming"'
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2. Symmetric BSIM-SOI—Part I: A Compact Model for Dynamically Depleted SOI MOSFETs
3. An All-Region BSIM Thin-Film Transistor Model for Display and BEOL 3-D Integration Applications
4. Extending Standard BSIM-BULK Model to Cryogenic Temperatures
5. Corrections to “Low-Temperature Microwave Annealing Processes for Future IC Fabrication—A Review” [Mar 14 651-665]
6. Compact Modeling of Impact Ionization in High-Voltage Devices
7. Compact Modeling of Impact Ionization and Conductivity Modulation in LDMOS Transistors
8. Comprehensive High-Voltage Parameter Extraction Strategy for BSIM-BULK HV Model
9. A Compact Model of Perpendicular Spin-Transfer-Torque Magnetic Tunnel Junction
10. Comprehensive High-Voltage Parameter Extraction Strategy for BSIM-BULK HV Model
11. Neural Network-Based BSIM Transistor Model Framework: Currents, Charges, Variability, and Circuit Simulation
12. A Compact Model of Perpendicular Spin-Transfer-Torque Magnetic Tunnel Junction
13. Neural Network-Based and Modeling With High Accuracy and Potential Model Speed
14. Critical Importance of Nonuniform Polarization and Fringe Field Effects for Scaled Ferroelectric FinFET Memory
15. A Compact Model of Nanoscale Ferroelectric Capacitor
16. Deep Learning-Based BSIM-CMG Parameter Extraction for 10-nm FinFET
17. A Compact Model of Metal–Ferroelectric-Insulator–Semiconductor Tunnel Junction
18. A Compact Model of Polycrystalline Ferroelectric Capacitor
19. Single-Crystal Islands (SCI) for Monolithic 3-D and Back-End-of-Line FinFET Circuits
20. S-Curve Engineering for ON-State Performance Using Anti-Ferroelectric/Ferroelectric Stack Negative-Capacitance FinFET
21. Compact Modeling of Temperature Effects in FDSOI and FinFET Devices Down to Cryogenic Temperatures
22. Energy Storage and Reuse in Negative Capacitance
23. Electric Field-Induced Permittivity Enhancement in Negative-Capacitance FET
24. Modeling of Current Mismatch and 1/f Noise for Halo-Implanted Drain-Extended MOSFETs
25. Analysis and Modeling of Polarization Gradient Effect on Negative Capacitance FET
26. Design Optimization Techniques in Nanosheet Transistor for RF Applications
27. Bias polarity dependent effects of P+ floating gate EEPROMs
28. A capacitorless double gate DRAM technology for sub-100-nm embedded and stand-alone memory applications
29. MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations
30. Direct-tunneling gate leakage current in double-gate and ultrathin body MOSFETs
31. Equivalent junction method to predict 3-D effect of curved-abrupt p-n junctions
32. A simple method for optimization of 6H-SiC punch-through junctions used in both unipolar and bipolar power devices
33. A spacer patterning technology for nanoscale CMOS
34. Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling
35. Sub-50 nm P-chennel FinFET
36. Noise modeling and characterization for 1.5-V 1.8-GHz SOI low-noise amplifier
37. SOI thermal impedance extraction methodology and its significance for circuit simulation
38. Charge-trap memory device fabricated by oxidation of Si1-xGex
39. Optimization of Negative-Capacitance Vertical-Tunnel FET (NCVT-FET)
40. Improved TDDB Reliability and Interface States in 5-nm Hf0.5Zr0.5O2 Ferroelectric Technologies Using NH3 Plasma and Microwave Annealing
41. BSIM Compact Model of Quantum Confinement in Advanced Nanosheet FETs
42. FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
43. Channel width dependence of hot-carrier induced degradation in shallow trench isolated PMOSFET's
44. New Ti-SALICIDE process using Sb and Ge preamorphization for sub-0.2 submicron CMOS technology
45. Gate engineering for deep-submicron CMOS transistors
46. A robust and physical BSIM3 non-quasi-static transient and AC small-signal model for circuit simulation
47. A 0.1-micrometer delta-doped MOSFET fabricated with post-low-energy implanting selective epitaxy
48. Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects
49. Simulating process-induced gate oxide damage in circuits
50. High-field transport of inversion-layer electrons and holes including velocity overshoot
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