20 results on '"Tsui, Bing-Yue"'
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2. A Study on the Isolation Ability of LOCal Oxidation of SiC (LOCOSiC) for 4H-SiC CMOS Process
3. 1100 V, 22.9 mΩcm2 4H-SiC RESURF Lateral Double-Implanted MOSFET With Trench Isolation
4. A Study on the Isolation Ability of LOC al O xidation of SiC (LOCOSiC) for 4H-SiC CMOS Process.
5. Electrical instability of low-dielectric constant diffusion barrier film (a-SiC:H) for copper interconnect
6. Degradation Mechanism of Ge N+-P Shallow Junction With Thin GeSn Surface Layer
7. 1100 V, 22.9 mΩcm 2 4H-SiC RESURF Lateral Double-Implanted MOSFET With Trench Isolation.
8. Series resistance of self-aligned silicided source/drain structure
9. Effect of fluorine incorporation on the thermal stability of PtSi/Si structure
10. Effect of Ion-Implantation Temperature on Contact Resistance of Metal/n-Type 4H-SiC With Ar Plasma Treatment
11. Effects of Rapid Thermal Annealing on Ar Inductively Coupled Plasma-Treated n-Type 4H-SiC Schottky and Ohmic Contacts
12. Degradation Mechanism of Ge N+-P Shallow Junction With Thin GeSn Surface Layer.
13. Investigation Into Gate-to-Source Capacitance Induced by Highly Efficient Band-to-Band Tunneling in p-Channel Ge Epitaxial Tunnel Layer Tunnel FET
14. A Novel Approach Using Discrete Grain-Boundary Traps to Study the Variability of 3-D Vertical-Gate NAND Flash Memory Cells
15. Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D NAND Flash Memory Devices
16. ${\rm Si}_{\rm x}{\rm Ge}_{1\hbox{-}{\rm x}}$ Epitaxial Tunnel Layer Structure for P-Channel Tunnel FET Improvement
17. Process and Characteristics of Fully Silicided Source/Drain (FSD) Thin-Film Transistors
18. Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D <sc>NAND</sc> Flash Memory Devices.
19. Six\rm Ge1\-{\rm x} Epitaxial Tunnel Layer Structure for P-Channel Tunnel FET Improvement.
20. A Comprehensive Study on the FIBL of Nanoscale MOSFETs.
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