177 results on '"Wong, H.-S. Philip"'
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2. Forming-Free Selectors Based on Te in an Insulating SiO xMatrix
3. Effect of Back-Gate Dielectric on Indium Tin Oxide (ITO) Transistor Performance and Stability
4. Forming-Free Selectors Based on Te in an Insulating SiOx Matrix
5. Comprehensive Study of Contact Length Scaling Down to 12 nm With Monolayer MoS2 Channel Transistors
6. Comprehensive Study of Contact Length Scaling Down to 12 nm With Monolayer MoS$_{\text{2}}$ Channel Transistors
7. Ab Initio Computational Screening and Performance Assessment of van der Waals and Semimetallic Contacts to Monolayer WSe$_{\text{2}}$ P-Type Field-Effect Transistors
8. Extended Scale Length Theory for Low-Dimensional Field-Effect Transistors
9. SAPIENS: A 64-kb RRAM-Based Non-Volatile Associative Memory for One-Shot Learning and Inference at the Edge
10. RADAR: A Fast and Energy-Efficient Programming Technique for Multiple Bits-Per-Cell RRAM Arrays
11. Ab Initio Computational Screening and Performance Assessment of van der Waals and Semimetallic Contacts to Monolayer WSe2 P-Type Field-Effect Transistors
12. Effect of parasitic resistance and capacitance on performance of InGaAs HEMT digital logic circuits
13. Measurement of subnanosecond delay through multiwall carbon-nanotube local interconnects in a CMOS integrated circuit
14. Integrating phase-change memory cell with Ge nanowire diode for crosspoint memory-experimental demonstration and analysis
15. An analytical derivation of the density of states, effective mass, and carrier density for achiral carbon nanotubes
16. A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application - part II: full device model and circuit performance benchmarking
17. A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application - part I: model of the intrinsic channel region
18. Schottky-barrier carbon nanotube field-effect transistor modeling
19. Metrics for performance benchmarking of nanoscale Si and Carbon nanotube FETs including device nonidealites
20. Bidirectional Analog Conductance Modulation for RRAM-Based Neural Networks
21. Fabrication of metal gated FinFETs through complete gate silicidation with Ni
22. Design Space Analysis for Cross-Point 1S1MTJ MRAM: Selector–MTJ Cooptimization
23. Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS2 Channel Directly Grown on SiO$_{{x}}$ /Si Substrates Using Area-Selective CVD Technology
24. Next-Generation Ultrahigh-Density 3-D Vertical Resistive Switching Memory (VRSM)—Part II: Design Guidelines for Device, Array, and Architecture
25. Next-Generation Ultrahigh-Density 3-D Vertical Resistive Switching Memory (VRSM)—Part I: Accurate and Computationally Efficient Modeling
26. Resistive RAM With Multiple Bits Per Cell: Array-Level Demonstration of 3 Bits Per Cell
27. Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS2 Channel Directly Grown on SiOx/Si Substrates Using Area-Selective CVD Technology.
28. Dual-Layer Dielectric Stack for Thermally Isolated Low-Energy Phase-Change Memory
29. Phase-Change Memory—Towards a Storage-Class Memory
30. A Compact Model for Metal–Oxide Resistive Random Access Memory With Experiment Verification
31. 3-D Resistive Memory Arrays: From Intrinsic Switching Behaviors to Optimization Guidelines
32. 1D Selection Device Using Carbon Nanotube FETs for High-Density Cross-Point Memory Arrays
33. Compact Model for Carbon Nanotube Field-Effect Transistors Including Nonidealities and Calibrated With Experimental Data Down to 9-nm Gate Length
34. Low-Energy Robust Neuromorphic Computation Using Synaptic Devices
35. Electrothermal Modeling and Design Strategies for Multibit Phase-Change Memory
36. On the Switching Parameter Variation of Metal-Oxide RRAM—Part I: Physical Modeling and Simulation Methodology
37. An Ultra-Low Reset Current Cross-Point Phase Change Memory With Carbon Nanotube Electrodes
38. On the Switching Parameter Variation of Metal Oxide RRAM—Part II: Model Corroboration and Device Design Strategy
39. Low-Resistance Electrical Contact to Carbon Nanotubes With Graphitic Interfacial Layer
40. Integration of Nanoelectromechanical Relays With Silicon nMOS
41. Investigation of Trap Spacing for the Amorphous State of Phase-Change Memory Devices
42. Nanoscale Bipolar and Complementary Resistive Switching Memory Based on Amorphous Carbon
43. Fabrication and Characterization of Nanoscale NiO Resistance Change Memory (RRAM) Cells With Confined Conduction Paths
44. Technology Assessment Methodology for Complementary Logic Applications Based on Energy–Delay Optimization
45. An Electronic Synapse Device Based on Metal Oxide Resistive Switching Memory for Neuromorphic Computation
46. Noniterative Compact Modeling for Intrinsic Carbon-Nanotube FETs: Quantum Capacitance and Ballistic Transport
47. Physics-Based Compact Model for III–V Digital Logic FETs Including Gate Tunneling Leakage and Parasitic Capacitance
48. Resistance and Threshold Switching Voltage Drift Behavior in Phase-Change Memory and Their Temperature Dependence at Microsecond Time Scales Studied Using a Micro-Thermal Stage
49. High-Mobility Ge N-MOSFETs and Mobility Degradation Mechanisms
50. Fully Integrated Graphene and Carbon Nanotube Interconnects for Gigahertz High-Speed CMOS Electronics
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