Search

A new vertical double-diffused metal oxide semiconductor field effect transistor (MOSFET) is presented based on the high- ${k}$ (Hk) MOSFET concept in this article with the step high- ${k}$ insulator, named as step Hk vertical double-diffused metal oxide semiconductor (VDMOS), to improve the electric field modulation effect. For step Hk VDMOS, the depletion is increased by the electric field modulation effect of step Hk insulator, which decreases the specific on-resistance of step Hk VDMOS compared to the conventional Hk VDMOS. The various thickness of the Hk insulator modulates the vertical electric field distribution in the drift region, which increases the breakdown voltage (BV) of the step Hk VDMOS. Meanwhile, an analytical model for novel step Hk VDMOS is obtained by solving the 2-D Poisson equation in an N-type drift region, and the 2-D Laplace equation in the step Hk region, which can reasonably explain the modulation effect of the step Hk region on the electric field distribution. The results show that the BV of the step Hk VDMOS is increased from 639 V of the conventional Hk VDMOS to 736 V with the same drift length of $42~\mu \text{m}$ . The theoretical results of the electrical characteristics are in good agreement with the results from numerical simulations.

Planar-gate 2.3 kV 4H-SiC power MOSFETs were successfully fabricated in a commercial foundry with the gate oxide thickness reduced from 55 to 27 nm for the first time. Results of numerical simulations demonstrate acceptable gate oxide electric field despite the increased blocking voltage. For a gate bias of 15 V, the measured specific ON-resistance ( ${R}_{\mathrm {ON},\text {sp}}$ ) and high-frequency figures-of-merit (FOM[ ${R}_{\mathrm {ON}} \times {C}_{\text {gd}}$ ], FOM[ ${R}_{\mathrm {ON}} \times {Q}_{\text {gd}}$ ]) were improved by a factor of $1.3\times $ by reducing the gate oxide thickness even at the larger blocking voltage. Analytical modeling shows that the channel and accumulation layer resistances are still important contributors even at this larger blocking voltage capability. Operating the 27 nm gate oxide devices with the commonly accepted ON-state gate oxide electric field of 4 MV/cm for reliable operation makes the ${R}_{\mathrm {ON},\text {sp}}$ and FOMs for the 27 nm gate oxide case 10% worse than the 55 nm gate oxide case. However, the reduced gate bias of 11 V for the 27 nm gate oxide case reduces input switching power loss in half from a gate drive perspective. In addition, operation at this gate bias makes the saturation current for the 27 nm gate oxide devices three times smaller than for the conventional devices operating at a gate bias of 20 V, which will proportionally increase short-circuit withstand time.

We introduce the concept of constant-gate-charge scaling to increase the short-circuit withstand time of SiC power MOSFETs without increasing their ON-state resistance, gate charge, or oxide field. In gate-charge scaling, we scale the oxide thickness and gate drive voltage, keeping the oxide field constant. Short-circuit measurements on 1200 V SiC double-implanted MOSFETs (DMOSFETs) confirm that short-circuit withstand times can be increased by 2– $4\times $ without increasing ON-resistance, simply by reducing the oxide thickness and the gate drive voltage.

It is highly desirable to monolithically integrate a high-performance freewheeling diode (FWD) in both Si and SiC power MOSFETs for power electronic applications. This is especially true for a SiC MOSFET since its inherent body diode has a very large turn-on knee voltage (~2.7 V). The purpose of this numerical study is to investigate a new 1200 V SiC MOSFET structure with an integrated heterojunction diode formed between n-type polysilicon and n-type SiC (termed HJD-MOSFET). The proposed HJD-MOSFET uses a mesa structure to accommodate the heterojunction FWD without sacrificing any active area while leaving the split-gate planar MOSFET cells in the trench. A p-shield region surrounding the heterojunction, along with the p-base of the MOS cells, shields high electric fields and maintains a high breakdown voltage. Three key HJD-MOSFET device parameters are identified and optimized in this article. The HJD-MOSFET offers a turn-on knee voltage of 0.5 V, roughly five times lower than the intrinsic SiC body diode or two times lower than a typical SiC Schottky barrier diode due to the low barrier height of the n/n heterojunction (~0.68 eV). Finally, the gate charge of HJD-MOSFET is reduced by 42% compared with conventional MOSFET since the poly-Si gate electrode is significantly reduced to accommodate the heterojunction FWD.

The phenomenon of reduced energy capability of power metal–oxide–semiconductor field-effect transistors (MOSFETs) at high avalanche currents is investigated in commercial 1.2-kV 4H-SiC MOSFETs. Unclamped inductive switching (UIS) measurements as well as electrical transport simulations are used to identify the current paths and maximum avalanche currents, providing insight into the design limits. The investigated devices show a reduced energy capability for avalanche current above 52 A due to the latching of the parasitic bipolar junction transistor (BJT). The BJT also limits the maximum switchable current to ≤102 A. Based on the measurements and simulations, a procedure utilizing UIS measurements for identification of design limits is presented.

This article presents design for a 650-V super-junction (SJ) power metal–oxide–semiconductor field effect transistor (MOSFET) which improves tolerance to both single-event burnout (SEB) and single-event gate rupture (SEGR). Experimental measurements of SEGR in a generic commercial planar gate SJ device are used to validate the accuracy of the design. In an SJ device with a planar gate, reducing the neck width improves the tolerance to gate rupture but significantly changes the electrical device characteristics. The trench gate SJ device design is shown to overcome this problem. A buffer layer and larger P+-plug are added to the trench gate SJ power transistor to improve SEB tolerance. The proposed trench gate structure improves the SEGR survivability by a factor of 10.

This brief presents 2-D numerical simulation results of a single-event burnout (SEB) in a 4H-silicon carbide (SiC) junction termination extension (JTE) termination structure of a power metal–oxide–semiconductor field-effect transistor (MOSFET). Using the rated 1.5-kV JTE termination structure, the most sensitive ion’s strike position to SEB is proved to be the edge of the P+/P− JTE region. Due to the severe punchthrough of the electric field, the source contact region is found to the most sensitive region to induce an SEB event. The SEB performance of the JTE termination structure with a single buffer layer or multilayer buffer is evaluated. The results show that the electric field distribution in four buffer layers (FBLs) is the most uniform to achieve the best SEB performance. Therefore, by adding an optimal FBL design to the termination region, the SEB threshold voltage can be increased to 1210 V instead of the common structure’s 250 V. The SEB safe operating area of the power MOSFET with an optimal FBL can increase more than three times compared with the common one.

Diamonds are highly favored materials in high-temperature and high-power operations owing to their excellent characteristics, and diamond p-channel field-effect transistors (p-FETs) considerably aid in the improvement of CMOS technology, providing high performance, which is essential for inverter operations. This study demonstrates a low ON-resistance (001) vertical-type two-dimensional hole gas (2-DHG) diamond metal–oxide–semiconductor field-effect transistor (MOSFET) with a trench gate structure. The active area of the device reduced after introducing a trench gate structure that can significantly improve the device integration and high-current operation. The maximum drain current density ( ${I}_{\text{D}}$ ) exceeds 20 kA/cm2 at ${V}_{\text{DS}} = -50$ V and ${V}_{\text{GS}} = -20$ V, which is the highest value obtained for (001) vertical-type diamond MOSFETs. This vertical-type diamond trench MOSFET can obtain the lowest ON-resistance ( ${R}_{\mathrm{\scriptstyle{ON}}}\text{S}$ ) of 2.5 $\text{m}\Omega \cdot \text{cm}^{2}$ , which is comparable to that of SiC and GaN vertical-type n-channel FETs (n-FETs). It can be potentially used as a p-channel power FET in a complementary inverter. Furthermore, this study demonstrates that the trench contact depth to the p+ diamond substrate significantly impacts the static characteristics of a device using the ATLAS device simulation. This result significantly contributes to the improvement of the rising drain current in the low-voltage region of the vertical-type diamond FET, which can be used in the future as p-channel power devices for the next generation of complementary inverters using GaN or SiC MOSFETs as n-channels.

In this article, the degradation behavior of the commercial 1.2-kV SiC power MOSFETs was investigated under repetitive power-cycling stress, and defect analysis based on low-frequency noise (LFN) was carried out. The experimental results show that increasing power-cycling stress results in a forward shift of threshold voltage and increasing ON-resistance. Meanwhile, the drain-to-source current significantly decreases with the increase of the cycles. Furthermore, the gate–source leakage current of the device became larger and the blocking characteristics deteriorated after 10-k cycles. The negative shift of the gate-capacitance versus gate-voltage curve was analyzed. Trap characterization was performed by using the LFN method, and it was found that the trap density of the device increased 5.47 times after 10-k cycles. The physical mechanism could be attributed to electrically active trapped charges generated at the SiC/SiO2 interface during power-cycling stress. This article may be helpful for degradation detection and fault analysis of SiC power MOSFETs in the electronic system.

The short-circuit (SC) failure mechanism of double-trench silicon carbide (SiC) power metal–oxide–semiconductor field-effect transistors (MOSFETs) is comprehensively studied and analyzed. Unlike traditional planar-gate devices which die from thermal runaway, the double-trench ones exhibit a different SC failure phenomenon. After enduring an ultimate SC stress cycle, the gate of the double-trench device breaks down while the conducting and blocking characteristics of the body diode remain stable. During the SC process, a substantial negative gate current from the semiconductor side to the poly gate side is observed. Silvaco TCAD simulations demonstrate that ultrahigh current density and impact ionization appear at the gate trench corners simultaneously, driving the generated hot holes through the oxide, forming the negative gate current. The sustained action of this gate current component on the oxide finally results in the failure. Moreover, the influence that bias voltages have on the SC endurance capability of the device is analyzed. In general, the higher the ${V}_{\text {ds}}$ and ${V}_{\text {gs}}$ are the shorter the SC endurance time will be. It is also found that the double-trench device fails with a higher junction temperature when stressed under a lower ${V}_{\text {ds}}$ condition, implying that the temperature rarely affects the failure, proving the correctness of the proposed SC failure mechanism.

In this article, a method of single-event burnout (SEB) hardening at high linear energy transfer (LET) value range is proposed and investigated by the 2-D numerical simulations. The improved MOSFET using this method and the conventional MOSFET are analyzed and compared to evaluate the effectiveness of this method. Simulation results show that, compared with the conventional MOSFET, the improved MOSFET using this method can effectively and quickly reduce the internal high electric field, thereby reducing the temperature. Under the condition of a LET value of 0.5 pC/ $\mu \text{m}$ and a drain voltage of 1200 V, the maximum drain current is 0.168 A, and the maximum global device temperature is 1724 K, which is much lower than the melting down temperature of silicon carbide (SiC) (3100 K). The hardening method in this article can be applied to different breakdown voltages by adjusting structure parameters.

In this article, the single-event response of the 1.2-kV silicon-carbide (SiC) power MOSFETs with varied buffer layer designs is investigated by the 2-D numerical simulations. The structural parameters of the buffer layers are compared and analyzed to understand the transient response after the heavy ion strike and the related physical mechanisms comprehensively. Simulation results reveal that an optimized single buffer structure can be acquired by using a relatively thicker buffer layer (T $\mu \text{m}$ ) and a moderate doping concentration (D cm−3). It demonstrates that the single-event-burnout (SEB) performance can be improved significantly under the worst case bias conditions [a drain bias voltage of 1.2 kV and a linear energy transfer (LET) of 1 pC/ $\mu \text{m}$ ]. In addition, the optimized structural combinations adopted in the dual or triple buffer layers can strengthen the SEB performance further. The simulation results show that a step electric field distribution is established inside the optimized dual or triple buffers, where the electric field peak is mitigated from 3 to 2.2 MV/cm. Moreover, the excess carrier generation is suppressed and the local temperature rise is weakened during the transient electrothermal process. Consequently, the structure with the optimal buffer layer designs can enlarge the SEB safe operating area (SOA) from 30%–50% to 100% rated breakdown voltage at high LET bias, which makes the SiC power MOSFETs used in aerospace and aviation power electronic systems become possible.

In this article, a trench-field-plate (TFP) high-voltage power MOSFET is proposed. Instead of using a conventional n− drift region, the TFP power MOSFET features benzocyclobutene dielectric in the sidewall of deep trenches in the drift region and a sloped field plate (FP) inside each of the trenches. The TFP structure employed in the drift region modulates the electric field in the OFF-state, resulting in a higher breakdown voltage (BV) than that of conventional power MOSFETs. Simulation results show that the specific ON-resistance of the TFP power MOSFET is approximately one-third that of the conventional power MOSFET and about 50% lower than that of the silicon limit for the same BV. In addition, compared with superjunction devices, the TFP power MOSFET is able to provide better reverse recovery characteristics, including a reduction in peak reverse recovery current ( ${I}_{{\text {RRM}}}{)}$ and reverse recovery charge ( ${Q}_{{\text {RR}}} {)}$ by 24% and 37%, respectively. Moreover, a p-i-n diode employing the TFP structure is fabricated, which is essentially identical to a power MOSFET in the OFF-state, to demonstrate the BV characteristics. The fabricated TFP p-i-n diode has a BV of 522 V, which is 2.3 times that of a conventional p-i-n diode fabricated on the same substrate.

In this article, new structures are proposed with an extra electrode for accumulation-mode vertical double-diffused metal-oxide semiconductor (VDMOS) (EA VDMOS) and a gate electrode for accumulation-mode VDMOS (GA VDMOS). For accumulation-mode VDMOS, the drift region is lightly doped to support drain voltage in the OFF-state. A large density of electrons is accumulated to modulate the conductivity of the drift region in the ON-state. It is contradictory to obtain high breakdown voltage (BV) and low specific ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ ) in the conventional VDMOS, because both of them depend on the doping concentration of the drift region. This contradictory relationship between the BV and ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ is eliminated for EA and GA VDMOS, thereby breaking the superjunction (SJ) silicon limit. Simulation results indicate that ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of the accumulation-mode VDMOS devices are significantly reduced. The ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of EA and GA VDMOS can be reduced by 60% (0.85 $\text{m}\Omega ~ \cdot $ cm2) and 30% (1.68 $\text{m}\Omega ~ \cdot $ cm2) compared with the SJ VDMOS (2.41 $\text{m}\Omega ~ \cdot $ cm2) at the BV of 600 V, respectively. In addition, the performance of the accumulation-mode VDMOS is independent of charge balance which is necessary for the SJ VDMOS.

The behavior of the barrier height of the SiC/SiO2 interface has been investigated over a wide temperature range, from 173 K to 523 K. These data complement the literature, providing a better knowledge of this parameter, which was studied only over a more restricted temperature range, and never before for low temperatures. It is highlighted that the measured samples exhibit a barrier height temperature dependence very near to the theoretical one (≈−0.7 meVK−1). Beyond 473 K, the barrier height seems to drop faster for some samples, reaching ≈−1.4 meVK−1. If this faster decreasing rate is maintained for higher temperatures, it could limit 4H-SiC MOSFETs performances or reliability for high-temperature applications. It is expected that the data provided here will allow for more accurate modeling of the gate current and the charge injection in the oxide layer of power MOSFETs, leading to more reliable predictions of the oxide lifetime for 4H-SiC MOSFETs.

An overview over issues and findings in SiC power MOSFET reliability is given. The focus of this article is on threshold instabilities and the differences to Si power MOSFETs. Measurement techniques for the characterization of the threshold voltage instabilities are compared and discussed. Modeling of the threshold voltage instabilities based on capture–emission-time (CET) maps is a central topic. This modeling approach takes the complete gate bias/temperature history into account. It includes both gate stress polarities and is able to reproduce the short-term threshold variations during application-relevant 50-kHz bipolar ac-stress. In addition, the impact on circuit operation is discussed.

This article presents the results of a 2-D finite element simulation study of the gate damages induced by heavy-ion irradiation in SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs). The time evolution of the electric field in the gate oxide is studied. Two effects are investigated: the first is associated with the charge deposition in the SiC portion of the MOSFET, with the time evolution studied using the 2-D finite element simulator; the second one results from holes generated during the ion transit, trapped in the gate oxide after the fast electrons have been quickly swept away by the electric field. Two different techniques have been combined for estimating the hole concentration in the gate oxide: the well-known recombination rate was modified to consider the trapped charge yield, as was recently done to better interpret single event gate rupture (SEGR) failure of silicon power MOSFETs. Under ion irradiation test conditions at which the gate damage experimentally starts to be observed, we demonstrate that, because of the ion impact, regardless of the ion linear energy transfer (LET), the peak value of the electric field in the gate oxide becomes practically equal to the oxide breakdown field (~12–15 MV/cm). Moreover, we show that simulations can be used to predict the test conditions at which gate damage starts to appear as a function of LET and the range of heavy ions used in the irradiation experiments.

Detailed physics of the third quadrant electrical characteristics of 1.2-kV rated 4H-SiC accumulation (Acc) and inversion (Inv) channel MOSFETs, based on experimentally measured data and TCAD numerical simulations, are described in this paper for the first time. The power MOSFETs with various channel lengths (0.3, 0.5, 0.8, 1.1 $\mu \text{m}$ ) used in this paper were fabricated in a 6-in commercial foundry. Numerical simulations verified that there are two current paths in the third quadrant: 1) through the base region and 2) through the p-n body diode. This paper demonstrates that the Acc MOSFETs have a smaller third quadrant knee voltage ( ${V}_{{\text {knee}}})$ of −1.2 V compared with −1.9 V for the Inv MOSFETs (at ${V}_{g} = {0}$ V and room temperature). Numerical simulations show that this difference is due to a smaller potential barrier for electron transport from the drain to the source in the base region for accumulation channel devices than inversion channel devices. Acc devices are shown to have a lower voltage drop in the third quadrant.

Silicon carbide (4H-SiC) devices experiencing avalanche conditions can reach temperatures above 1500 K. Simulation of impact ionization in devices should, therefore, include models valid up to such high temperatures. However, calibrations of impact ionization coefficients are available only up to 580 K, and simulations of switching show deviations from measurements at higher temperatures. In this paper, a more accurate model based on the underlying physics of high temperature and anisotropic avalanche generation is proposed. This model enables calibrations performed at room temperature along the ${c}$ -axis to be more precisely extrapolated to any temperature of interest in 2-D device simulations. The model provides an excellent fit to the measurements of breakdown voltages during unclamped inductive switching tests of power MOSFETs, enabling a more accurate prediction of ruggedness. The more comprehensive physics included in the model makes it also applicable to other wide bandgap semiconductors such as GaN, diamond, and Ga2O3, which also exhibit a high critical electric field.

Small-signal measurements of output capacitance ( ${C_{\textsf {OSS}}}$ ) are ubiquitous in power semiconductor datasheets and determine critical features of power converters. For silicon superjunction power MOSFETs (SJs), we report ${C_{\textsf {OSS}}}$ measurements with two key anomalies: variation with ac perturbation frequency and hysteresis with dc sweep direction. Using mixed-mode simulations, we attribute the frequency shift to the fundamental SJ structure and find that dc hysteresis is caused by charge trapping from uneven depletion fronts. We show that ${C_{\textsf {OSS}}}$ measurements on SJs do not accurately characterize large-signal operation, underestimating stored energy by up to four times and giving no indication of ${C_{\textsf {OSS}}}$ losses.

The degradations of electrical parameters for double-trench silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) under repetitive avalanche stress are investigated in this paper. The injection of hot holes into the bottom oxide of the gate trench during avalanche process is demonstrated to be the dominant degradation mechanism, while the channel is rarely influenced by the stress. The injected holes attract extra electrons in the SiC layer along the SiC/SiO2 interface, decreasing the ON-state drain–source resistance ( ${R}_{{dson}}$ ). Due to this reason, the threshold voltage ( ${V}_{{th}}$ ) of the device also reduces slightly. Moreover, other than static electrical parameters, dynamic characteristics including the gate–drain capacitance ( ${C}_{{gd}}$ ) and the switching characteristics of the device also degrade. After being stressed by repetitive avalanche stress, the depletion region beneath the bottom of the gate trench gets thinner, leading to the increase in ${C}_{{gd}}$ , which further influences the switching behaviors. The turn- ON and turn- OFF switching times of the device are calculated. It illustrates that the repetitive avalanche stress results in an obvious delay in the turn- OFF procedure, but hardly influences the turn- ON behaviors of the double-trench SiC MOSFET.

The degradations of electrical parameters for silicon carbide power MOSFETs under repetitive short-circuit (SC) stress are investigated in detail in this paper. It demonstrates that the generation of negative charges along the gate–oxide interface of the channel region is the dominant degradation mechanism, which results in the increase in the threshold voltage ( ${V}_{\text {th}}$ ) and the rise of ON-state resistance ( ${R}_{\text {dson}}$ ) under low gate voltage bias condition. Furthermore, degradations of dynamic characteristics including gate charge ( ${Q}_{\text {g}}$ ) and switching behaviors of the device after the repetitive SC stress are extracted and analyzed for the first time. It illustrates that the increased ${V}_{\text {th}}$ contributes to the rise of the Miller plateau voltage ( ${V}_{\text {gp}}$ ), which further leads to the increase in gate–source charge ( ${Q}_{\text {gs}}$ ). Meanwhile, the increase in the turn-ON time and the reduction of turn-OFF time are observed, which are also resulted from the positive shifts of ${V}_{\text {th}}$ and ${V}_{\text {gp}}$ , leading to the rise of turn-ON switching energy ( ${E}_{{ \text {on}}}$ ) and the decline of turn-OFF switching energy ( ${E}_{\text {off}}$ ), respectively.

The figure of merit (FOM) of a semiconductor device represents an important quality as it pertains to its performance limits and is often used to drive the technology development in a specific direction. Comparing the performances of switching power MOSFETs using their FOMs has become ubiquitous practice in power semiconductor and power electronics industries. In this paper, a critical review of the proposed power MOSFET FOMs is presented, and key limitations are discussed. It is shown that the quality factor ${Q}_{F2}={(}{\lambda {E}_{c}}/{R_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}}{)}$ along with ${Q}_{G}$ and ${T}_{j\textsf {max}}$ may be used to guide the development of future generations of power semiconductor device technologies for power electronics switching applications, where $\lambda $ and ${E}_{c}$ are the thermal conductivity and critical electric field strength for the avalanche breakdown of the semiconductor material, respectively, ${R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ is the specific on-state electrical resistance, ${Q}_{G}$ is the gate charge, and ${T}_{j\textsf {max}}$ is the maximum junction temperature of the semiconductor power device, respectively.

Silicon carbide (SiC) power MOSFETs are available only for high-power and medium-to-high-voltage applications, generally above 600 V, because for lower blocking voltages, they comparatively provide lower advantages in terms of efficiency. There are applications, however, for which ruggedness and reliability are as important as efficiency, such as power optimizers for photovoltaic (PV) modules, which fall within the low power, low voltage category of dc–dc converters. These circuits, which maximize the energy produced by each single PV module, operate in continuously changing and stressing conditions yet having to assure high performances in terms of efficiency as well as of temperature insensitivity and long-term reliability. The aim of this paper is to predict the basic characteristics of a 4H-SiC MOSFET tailored for this kind of applications and, therefore, characterized by a breakdown voltage BVDS of 150 V and currents of the order of 10 A. The study, based on numerical simulations, shows that, besides the expected higher ruggedness, the static characteristics would be comparable to those of silicon MOSFETs rated for a comparable BVDS, with $R_{\mathrm{\scriptscriptstyle ON}}$ in the order of 100 $\text{k}\Omega {\cdot} \mu \text{m}^{2}$ , while advantages would result in terms of dynamic characteristics, and in particular in terms of switching times.

The novel SiC/Si heterojunction power MOSFET has been advanced to improve the tradeoff between the breakdown voltage (BV) and specific on-resistance ( ${R}_{ \mathrm{ON},\textsf {sp}}$ ). The innovative terminal technology of breakdown point transfer has been applied to SiC/Si MOSFET, which transfers the breakdown point from the high electric field points to the low electric field areas and improves the BV compared with the conventional Si power MOSFET. The results have been shown by technology computer aided design simulation that the BV has been improved for SiC/Si U-MOSFET due to PBT technology. The BV of the proposed SiC/Si U-MOSFET is increased to 358 V compared with the Si U-MOSFET of 107 V with the same device parameters. The simulated ${R}_{ \mathrm{ON},\textsf {sp}}$ of the SiC/Si U-MOSFET is $0.51~\textsf {m}\Omega \cdot \textsf {cm}^{2}$ with the BV of 358 V, which is lower than that of $1.12~\textsf {m}\Omega \cdot \textsf {cm}^{2}$ with the BV of 107 V for the conventional Si U-MOSFET. The important law is discovered that the high BV and low ${R}_{ \mathrm{ON},\textsf {sp}}$ can be obtained simultaneously for SiC/Si U-MOSFET when the depth of the trench oxide layer is increased, which cannot be taken into account in the conventional Si U-MOSFET. Therefore, the silicon and superjunction VDMOS (double-diffused MOSFET) limits had been broken for SiC/Si U-MOSFET. The influences of the different interface charge (acceptorlike and donorlike) have been analyzed for SiC/Si VDMOS and SiC/Si U-MOSFET.