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A space vector modulation (SVM) technique of a dual-inverter system for an open-end winding motor drive is described in this paper, where one inverter has a battery power source and the other has an only capacitor across the dc bus. The SVM must be achieved to operate the motor with field-oriented control and simultaneously to control the capacitor voltage at a constant value by using redundant switching states of the dual-inverter system. The control of the capacitor voltage is carried out by selecting a charging or a discharging mode in each redundant switching state, taking the instantaneous motor power factor into account. In addition, it is also required to reduce the error voltage pulses, which are generated in output multilevel voltage waveforms during the dead time. The compensation method of the existing dead-time scheme and the improved SVM sequence to reduce the error voltage vectors are proposed in this paper. The proposed methods are examined through several experimental tests and are confirmed to generate superior output voltage waveforms from the viewpoint of the measured total harmonic distortion and dv/dt. [ABSTRACT FROM AUTHOR]

The conventional three-level inverter only has voltage buck capability. The quasi-Z-source three-level T-type inverter (QZS 3LT $^2$ I) has been proposed to realize voltage buck–boost operation. In this paper, we further propose a novel modulation scheme for the QZS 3LT $^2$ I to realize voltage boosting, reduce the common-mode voltage (CMV), and control the neutral-point voltage balance simultaneously. The proposed scheme adopts a large vector, a medium vector, a small vector with low CMV magnitude, a zero vector, and a shoot-through vector to generate the output voltage. According to sector number and neutral-point voltage difference, a p-type or n-type small vector with low CMV magnitude is properly selected to balance the neutral-point voltage. Shoot-through states are inserted within zero vector to boost the dc input voltage without affecting the ac output voltage. Dwell times of basic vectors are calculated through the revised volt–second balance equation. Furthermore, a coordinate control strategy between neutral-point voltage balance and voltage boosting is proposed. Doing so, the CMV magnitude can be restricted within one-sixth of dc-link voltage and neutral-point voltage imbalance can be effectively mitigated. The effectiveness of the proposed scheme is verified by simulations and experiments. [ABSTRACT FROM AUTHOR]

This paper presents a model predictive control technique applied to a dual-active bridge inverter where one of the bridges is floating. The proposed floating bridge topology eliminates the need for isolation transformer in a dual inverter system and therefore reduces the size, weight, and losses in the system. To achieve multilevel output voltage waveforms, the floating inverter dc-link capacitor is charged to the half of the main dc-link voltage. A finite-set model predictive control technique is used to control the load current of the converter as well as the floating capacitor voltage. Model predictive control does not require any switching sequence design or complex switching time calculations as used for space vector modulation; thus, the technique has some advantages in this application. A detailed analysis of the converter as well as the predictive control strategy is given in this paper. Simulation and experimental results to validate the approach are also presented. [ABSTRACT FROM PUBLISHER]

To reduce the common-mode voltage (CMV) and eliminate the CMV spikes for two-level voltage source inverters (2L-VSIs), an improved model predictive control (MPC) based CMV reduction method is proposed in this paper considering dead-time effects. First, an improved voltage vector (VV) preselection strategy is proposed to reduce the CMV spikes caused by the dead time. Second, a new hybrid VV preselection strategy based on a delay compensation strategy and a modified current sector division strategy is proposed to completely eliminate the CMV spikes. As the proposed hybrid VV preselection based MPC strategy makes full use of the six nonzero VVs of the 2L-VSI, the current total harmonic distortions and ripples are reduced. The simulation and experiments are carried out to verify the effectiveness of the proposed strategy. [ABSTRACT FROM AUTHOR]

In this paper, performances on two kinds of aggregated flyback microinverters are compared in aspect of harmonic resonances, which are controlled by current feedback control and peak current control. Based on the Norton models of flyback microinverters obtained by a small-signal modeling approach, potential harmonic resonances with the grid are analyzed. Following that, an impedance-based stability criterion is proposed, where the resonance frequency can be calculated and predicted based on the derived Norton models and the system admittance matrix of aggregated microinverters. After comprehensive analysis and comparisons, it is found that the peak-current-control-based flyback microinverters has better performance on damping the harmonic resonances than the current feedback controlled one. Simulations and experiments are carried out for verifying the effectiveness of the presented models and the correctness of the analysis results. [ABSTRACT FROM AUTHOR]

A new pulsewidth modulation (PWM) strategy which is an alternative approach of the discontinuous PWM (DPWM) for a three-level neutral-point-clamped (NPC) inverter is proposed in this paper. A three-level NPC inverter is completely mature and very well-established topology in high-power applications. However, the three-level NPC inverter has an inheritance problem of the neutral-point voltage unbalancing due to the split dc-link capacitors. This structure can cause large neutral-point voltage ripple. Furthermore, output currents of the three-level NPC inverter are distorted by the neutral-point voltage ripple. Therefore, the neutral-point voltage must be controlled. In this paper, a new DPWM method using two different offsets for the neutral-point ripple reduction is proposed and the effectiveness of the proposed DPWM method is verified by using the simulation and the experimental results. [ABSTRACT FROM PUBLISHER]

In this paper, the remedial operation of switch faults will be investigated comprehensively for T-type-three-level-inverter-fed dual three-phase motor drives. The open-circuit switch faults in multiple phase legs are discussed at first. The faulty conditions are classified into five categories. Different remedial strategies, namely Type-I to Type-V schemes, are proposed for different faulty conditions. In particular, three kinds of Type-III fault-tolerant control schemes are proposed by using medium-voltage vectors to synthesize small-voltage vectors, in such a way that the mid-point voltage in a dc link can be stabilized well. Then, the short-circuit faults in both clamping switches and half-bridge switches are investigated. By analysis, their operation conditions are equivalent to conditions loss of both P and N voltage levels and open-phase faults, respectively. Thus, the corresponding remedial strategies can be applied accordingly. Particularly, a voltage compensation control method is proposed for conditions, where open-switch faults coexist with open-phase operation induced by short-circuit faults in half-bridge switches. The validity of all of theoretical analysis and the proposed remedial strategies has been verified by experiments. [ABSTRACT FROM PUBLISHER]

Several applications such as power supplies for electric precipitators, ozone generation, partial discharge, etc., require ac superimposed dc (ACsDC) voltage supply. Most of such applications use intransigent systems for producing ACsDC voltages. In this paper, three different kinds of flexible power electronic converters are proposed for producing ACsDC voltages. These converters have two power conversion stages: input and output. In the input stage, two isolated dc voltages are obtained by using an isolated three-port dc–dc converter or two isolated two-port dc–dc converters. In the output stage, one of the input-stage dc voltages is used to generate an ac voltage and the obtained ac voltage is added to the remaining input-stage dc voltage to obtain an ACsDC voltage. Based on the converters used in the input stage, the proposed ACsDC converters are named as a dual active bridge (DAB) converter-based ACsDC converter (DAB-ACsDC), triple port active bridge (TAB) converter-based ACsDC converter (TAB-ACsDC), and dual transformer-based asymmetrical triple port active bridge (DT-ATAB) converter-based ACsDC converter (DTATAB-ACsDC). A detailed analysis of these ACsDC converters and their verifications using simulations and experimental studies are presented, which depict that the proposed converters can be used effectively for producing ACsDC voltages. [ABSTRACT FROM AUTHOR]

In the paper by Chen et al. (IEEE Trans. Ind. Electron., vol. 66, no. 4, pp. 2837–2846, Apr. 2019), the authors proposed two fault-tolerant control strategies for T-type three-level inverters considering neutral-point (NP) voltage oscillations. However, some basic problems are worth being discussed about the proposed fault-tolerant control methods. This letter presents some comments and results concerning the paper by Chen et al. [ABSTRACT FROM AUTHOR]

This paper proposes a unique carrier-based pulse width modulation strategy for a three-level neutral-point-clamped inverter that works satisfactorily and with uniform convergence time over the full power factor (PF) range of the load variation. It has excellent control over capacitor voltages and mitigates low-frequency oscillations in the neutral point for the full PF range. First, an investigation is made to see how the load currents get modulated to generate compensating neutral current causing charging and discharging of dc-link capacitors. It is observed that when an additional modulating voltage signal that is in phase with the corresponding phase current is added in each phase, a neutral current is produced in the right direction which can be used to compensate for any prior unbalance in capacitor voltages. It is demonstrated that the performance of this scheme is insensitive to the load PF variation (full range from zero to unity). It performs satisfactorily throughout the entire linear modulation range and eliminates any undesirable low-frequency harmonic component in the compensating neutral current. The effectiveness of the proposed scheme is verified through simulation and experimental results by varying load PF as well as modulation index with both passive and motor loads. [ABSTRACT FROM PUBLISHER]

Compensation of nonlinear effects generated by dead-time and semiconductors voltage drop has been widely studied in the literature about two-level converters. This paper takes a closer look at those analyses for multilevel converters, specifically for a cascaded H-bridge (CHB) converter modulated with phase-shifted pulse width modulation. The interaction between the cells is analyzed for a generic $n$ -cell converter, from which a general expression for the distortion generated by the nonlinearities has been obtained. Based on this expression, a compensation signal for the overall converter is calculated on each sample time, which is a fraction of the triangular carrier used to modulate each cell, thus significantly improving the quality of the output voltage signals. Experimental validation of the proposed compensation method is presented using a three-phase four-cell CHB converter prototype of 5.5 kW. [ABSTRACT FROM AUTHOR]

In this paper, a novel topology of six-level inverters for a medium-voltage high-power applications is proposed, which consists of inner flying-capacitor inverter (FCI) units and outer two-level inverter units. The proposed topology can reduce the number of devices, components, and isolated sources compared with the existing ones in the case of the same number of output voltage steps, which result in a reduction of the size and weight of the inverters. Also, the total power loss of the proposed topology is lower than that of the diode-clamped inverter (DCI) and FCI. Besides, the estimated cost of the proposed topology is about 60.5% and 81.3% compared with the DCI and FCI, respectively. In addition, the modulation technique and the control strategy for the dc-link capacitor and flying-capacitor voltages are developed for the proposed topology. The effectiveness of the proposed six-level inverter for the medium-voltage applications has been verified by simulation results. Also, the feasibility of the proposed inverter has been proved by experimental results for the prototype at the laboratory. [ABSTRACT FROM AUTHOR]

In this paper, a model-predictive control (MPC) has been designed and implemented on the packed U-cell (PUC) inverter, which has one isolated dc source and one capacitor as an auxiliary dc link. The MPC is designed to regulate the capacitor voltage at the desired magnitude to have seven voltage levels at the output of the inverter. Since grid-connected application is targeted by this application, the inverter should be capable of supplying requested amount of active and reactive power at the point of common coupling (PCC) as well. Therefore, MPC should also consider the line-current control to monitor the exchange of reactive power with the grid while injecting appropriate active power at low total harmonic distortion (THD). Various experimental tests including change in dc-source voltage, active power variation, and operation at different power factor (PF) have been performed on a laboratory prototype to validate the good performance obtained by the proposed MPC. The dynamic performance of the controller during sudden changes in dc capacitor voltage, supply current, and PF demonstrates the fast and accurate response and the superior operation of the proposed controller. [ABSTRACT FROM PUBLISHER]

The flying capacitor multilevel inverter (FCMLI) is one of the well-known structures of multilevel inverters having attracted considerable attention because of its merits. In spite of its many advantages, it has some limitations such as high volume and complicated control method because of its bulky capacitors and their voltage balancing requirement. Moreover, the high number of power semiconductors required makes this structure susceptible to failure. To increase the ratio of the number of levels to the number of components, an uneven distribution of capacitor voltages has been suggested in previous reports; however, this approach complicates the control method. Up to now, almost all presented methods suffer from high computational load and/or structure-dependent algorithm. In this paper, a simple state-based and structure-independent method is proposed for capacitor voltage regulation. The proposed method is straightforward and can perform online computation of switching sequences in a computationally efficient manner without any need for stored information or look-up tables. The method is conveniently extendible to any number of cells and levels in an FCMLI structure with arbitrary dc link voltage distribution schemes. Simulation and experimental results show the effectiveness and simplicity of this method. [ABSTRACT FROM PUBLISHER]

The quasi-Z-source cascaded multilevel inverter (qZS-CMI) presented many advantages over conventional CMI when applied in photovoltaic (PV) power systems. For example, qZS-CMI provides the balanced dc-link voltage and voltage boost ability, saves one-third modules, etc. However, current research studies only disclosed control of single-phase qZS-CMI-based PV power systems, and there was no literature related to control of three-phase qZS-CMI-based PV power systems. In this paper, for the first time, three-phase qZS-CMI's control is proposed and demonstrated for application to PV power systems. The models of PV-panel-fed qZS H-bridge module and qZS-CMI-based PV power system are built to accurately design control algorithms for each module and the whole system. The proposed control method includes the distributed maximum power point tracking for each module, dc-link peak voltage balance control for all modules, and grid-tie control for the whole system; moreover, a new multilevel space vector modulation method is proposed for the three-phase qZS-CMI. Simulation and experimental results on a test bench with a three-phase seven-level qZS-CMI-based PV power system verify the proposed control and modulation methods. [ABSTRACT FROM PUBLISHER]

In this paper, a predictive control scheme is proposed for the low-voltage ride-through (LVRT) enhancement of direct-driven permanent-magnet-synchronous-generator-based megawatt-level wind turbines. The proposed method uses the turbine–generator rotor inertia to store the surplus energy during the grid voltage dips. The power conversion system is realized using a three-phase diode-bridge rectifier, a three-level-boost converter, and a neutral-point-clamped (NPC) inverter. The wind turbine requirements, such as maximum power point tracking, net dc-bus voltage control, balancing of the dc capacitor voltages, and reactive power generation, are modeled as the reference control variables. The generator- and grid-side cost functions are defined to deal with these control objectives. During each sampling interval, the control goals are achieved based on the minimization of cost functions. The coordination of boost and NPC converters and the exchange of reference control variables during normal and LVRT operation are formulated such that the power converters operate in a safe mode while meeting the grid code requirements. Simulation and experimental results are presented to validate the proposed strategy. [ABSTRACT FROM PUBLISHER]

In a six-switch three-phase inverter, the conventional pulsewidth modulation (PWM) has six switching times in every switching period based on the average concept. The used multidimensional feedback quantized modulation (MDFQM) strategy selects one switching state and keeps it in every sampling period based on the minimization of filtered voltage errors between the desired voltage commands and the output voltages. The widths of the output voltage pulse are integer times the fixed sampling time in MDFQM. In this paper, two high-efficiency current control methods based on MDFQM are proposed. They integrate the MDFQM strategy and the current control function to minimize the filtered current errors between the desired current commands and the inverter current. Due to the main advantages of less switching numbers and more closed fundamental current, a high-efficiency performance is achieved. The proposed methods are applied to the current control of a three-phase permanent-magnet synchronous motor. The simulation results and experimental results verify the effectiveness of the proposed methods. [ABSTRACT FROM PUBLISHER]