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This paper presents a neutral-point deviation and ripple compensating control method applied to a three-level neutral-point-clamped (NPC) converter. The neutral-point deviation and its harmonic components are analyzed with a focus on the average current flowing through the neutral-point of the dc link. This paper also proposes a control scheme compensating for the neutral-point deviation and dominant harmonic components under generalized unbalanced grid operating conditions. The positive and negative sequence components of the switching functions and ac input currents are employed to accurately explain the behavior of three-level NPC converter. Simulation and experimental results are presented to verify the validity of the proposed method. [ABSTRACT FROM AUTHOR]

The switching speeds of next-generation power semiconductor devices, such as those made of silicon carbide and gallium nitride are roughly ten times those of conventional devices (e.g., silicon insulated-gate bipolar transistors). This increases the frequency range of the electromagnetic noise accompanying the switching operations of pulsewidth modulated (PWM) converters and worsens the influence of radiated noise. The authors have previously proposed an active common-mode filter (ACF) that reduces the radiated noise from the power cables connected to a PWM converter and evaluated its effect in reducing radiated noise by using a function generator as a common-mode (CM) noise source. In this paper, the ACF is applied to a motor drive system fed by a three-phase PWM inverter, and the attenuation characteristics of the CM voltage are evaluated. To avoid saturating the ACF, the combination of an active common-noise canceller and the ACF is discussed. The experimental results show that the system constructed in this paper can suppress the CM voltage produced by the PWM inverter over a wide frequency range from 100 to 100 MHz. [ABSTRACT FROM AUTHOR]

Grid-interactive inverters allow distributed generation units to provide various ancillary services in microgrids. As the linear modulation region of inverters is restricted by the dc-bus voltage, providing ancillary services may drive the fundamental positive-sequence inverter voltage to the overmodulation region. Therefore, to operate in the linear modulation region the maximum active- and reactive-power of the inverter may have to be reduced unless pulsewidth modulation (PWM) references are adjusted. In this paper, an atypical PWM method is proposed for maximizing dc-bus utilization of grid-interactive two-level voltage source inverters (2L-VSI) providing ancillary services. Two important ancillary services, i.e., negative-sequence compensation and harmonic compensation are considered in this paper. The proposed method increases the maximum active- and reactive-power that a 2L-VSI can deliver when providing ancillary services by injecting a common-mode component in the references computed based on instantaneous reference magnitudes. The validity of the proposed technique is verified through simulation, as well as experimental data obtained using a 208-V three phase grid-connected 2L-VSI. [ABSTRACT FROM AUTHOR]

The neutral-point voltage-balancing control is a critical issue of a neutral-point-clamped converter. The conventional control strategy is to inject the specific zero-sequence voltage to regulate the redundant vector, but it is unacceptable to the three-phase four-wire system. This paper provides a neutral-point voltage-balancing control by the dipolar modulation, and the control freedom of the zero-sequence voltage is flexible. Therefore, the proposed method is suitable for both three-phase three-wire and three-phase four-wire systems. Besides, the proposed method improves the control dynamic in a reactive power system. The proposed neutral-point voltage-balancing control is verified by the mathematical analysis and experimental results. The control dynamic, power loss estimation, and the output current performance are analyzed in this paper. [ABSTRACT FROM PUBLISHER]

An unidirectional single-phase three-wire rectifier is proposed in this paper. Such topology is composed of a noncontrolled leg, two controlled legs, and a capacitor bank. A suitable model, pulse-width modulation, and control strategies of the system are proposed as well. The control strategy includes the synchronization method, in which it imposes the grid currents with the same phase angle of the voltages generated by the rectifier. This method ensures sinusoidal grid currents and mitigates the zero-crossover distortions normally caused by the use of diodes. A comprehensive comparison with two conventional configurations is also presented in this paper. Simulation and experimental results are also presented for validation purposes. [ABSTRACT FROM AUTHOR]

In this paper, the zero sequence circulating current in open winding permanent magnet synchronous machine (OW-PMSM) drives with common dc bus is systematically analyzed for the first time. It is revealed that the zero sequence circulating current is affected by zero sequence back-electromotive force, cross coupling voltages in zero sequence from the machine side, pulse-width modulation induced zero sequence voltage, and inverter nonlinearity from the inverter side. Particularly, the influences from the cross coupling voltages in zero sequence and parasitic effect of inverter nonlinearity are investigated for the first time in this paper. Then, the synthetic model of the equivalent zero sequence circuit is proposed as well. Each cause is studied independently via analytical modeling, finite element analysis, and experiments. Meanwhile, to tackle this issue, the relevant suppression strategy using frequency adaptive proportional resonant controller is presented and tested on the 3 kW OW-PMSM platform. [ABSTRACT FROM AUTHOR]

This paper proposes a multilevel series compensator (MSC) to deal with voltage sags/swells, harmonic compensation, or reactive power compensation. Such a device can be considered as a dynamic voltage restorer or a series active power filter (Series-APF). The MSC can improve the power quality of loads located in stiff systems. The configuration is based on three-phase bridge (TPB) converters connected by means of cascaded single-phase transformers. This arrangement permits the use of a single dc-link. A generalization for $K$ -stages in which $K$ -transformers are coupled with $K$-TPB converters is presented. The topology permits generating a high number of levels in the voltage waveforms with a low number of power switches in comparison with a classic topology. The multilevel waveforms are generated by the converters through a suitable pulsewidth modulation (PWM) strategy that takes into consideration the transformer turns ratios. Modularity and simple maintenance make the proposed MSC an attractive solution compared with some conventional configurations. Model, PWM strategy, and overall control are discussed in this paper. Simulation and experimental results are presented as well. [ABSTRACT FROM PUBLISHER]

This paper presents the flexible dc capacitor voltages balancing control method for star-connected cascaded H-bridge converters. In this paper, the power flows are analyzed by investigating all the converter's control freedoms. Based on the analyses, users can accomplish the dc capacitor voltage balancing with both negative-sequence current and zero-sequence voltage. These two kinds of control options are further integrated together with the defined weighting factor $K$. The low-voltage ride-through operation of a proposed control method is also discussed in this paper. The control method is verified with a 220-V 1-kVA static synchronous compensators based on the star-connected cascaded H-bridge converters, and the experimental test results show that all the dc voltages are well regulated at the commanded value with different weighting factor $K$. [ABSTRACT FROM AUTHOR]

A modified-virtual-space-vector-based dc-link voltage balancing strategy is proposed in this paper for a three-level inverter. In the proposed strategy, the summation of the three-phase currents for virtual vector needs not to be zero and it also keeps the two capacitor voltages balanced with wider range of load variations. The duty cycles for all the power switches are also derived in this paper using a nearest three-voltage vector scheme. Due to the reduced use of the medium voltage vectors, the proposed control strategy can considerably decrease the neutral-point voltage fluctuation for lower power-factor-based loads as well. Detailed simulation and experimental studies are also carried out to show the effectiveness of the proposed system with a dc-link voltage balancing strategy with permanent magnet synchronous machine. Voltage and current harmonic distortions are also presented with change in modulation index. A Dspace-based real-time operating system is used for real-time implementation with a 6.0-kW surface permanent magnet synchronous motor. [ABSTRACT FROM PUBLISHER]

Three-phase voltage source pulsewidth modulation (PWM) rectifiers can achieve constant dc voltage and sinusoidal grid currents under ideal grid voltages. However, under unbalanced grid voltage conditions, there are ripples at twice the grid frequency in the dc voltage, and the grid currents become highly distorted. To address the aforementioned problems, control methods developed under ideal grid voltage conditions should be modified. Various techniques have been proposed in the literature to calculate the new current reference or power reference. However, most methods use conventional pq theory and only consider the grid-side power control. Hence, the dc voltage ripples are not completely eliminated. Furthermore, the derived mathematical expressions for reference calculations are usually very complicated. In contrast to current methods, this paper proposes a very simple yet effective direct power control (DPC) method based on extended pq theory. By analyzing the instantaneous extended power of the line inductance, a simple and concise power compensation is analytically derived and added to the original power references. As a result, the dc voltage ripples are significantly reduced, and the grid currents remain sinusoidal even under unbalanced grid voltage conditions. The proposed method is compared to conventional DPC methods, and its effectiveness is confirmed by the presented experimental results. [ABSTRACT FROM AUTHOR]

A switching-capacitor-based buck–boost converter (with common ground) for point of load applications is proposed in this paper. It is capable of operating in stand-alone buck or boost mode in addition to its primary operation of performing the buck–boost conversion. The striking feature of the proposed converter is low source current ripple content irrespective of its mode of operation (buck–boost, buck, or boost). First, feasible pulsewidth modulation schemes for the proposed converter are identified and thereafter the corresponding circuit performance analysis, steady-state analysis, and state-space modelling is established. Through steady-state analysis, voltage gain expressions are formulated and equations defining L-C components are derived in terms of their ripple quantities. The state-space models are used to formulate small-signal analysis and to obtain the relevant transfer functions required in the controller design. A voltage-mode/current-mode controller is designed, with a tradeoff in bandwidth, to control the proposed converter and transit it from buck to boost mode or vice versa seamlessly. A 30–55 W, 100 kHz, prototype point of load converter with 36-V input dc source is built to supply power at constant load voltage of either 48 or 28 V. The proposed converters’ effectiveness is demonstrated experimentally in terms of reduced source current ripple along with seamless transition from buck to boost mode and vice versa. [ABSTRACT FROM AUTHOR]

High speed permanent magnet synchronous motors (PMSMs) are used in electric vehicles because of their intense power density. The high speed implies a significant electromotive force and requires flux weakening. The usual control algorithms realize flux weakening by adding a negative $I_{d}$ current component when the voltage required by the current regulation exceeds the maximum voltage depending on the battery. If the magnet can be totally defluxed, then it is better to use a maximum torque per volt strategy. Furthermore, there is no speed regulation in the control and the driver gives a torque reference. This reference value has to be limited by the attainable operating points; therefore, the battery power limit has to be taken into account in addition to the voltage and current limits. The d–q current references are calculated to minimize the total current magnitude required to reach the reference torque. This paper proposes a strategy to control a PMSM operating continuously since the speed zero up to the maximum speed without the switching algorithm, in order to take into account the different limitations (current, voltage, and power) and to expand the overspeed zone. In order to validate the proposed strategy, experimental results are shown for a low power machine. [ABSTRACT FROM AUTHOR]

An adaptive control of DPWM implementable in clamped-three-level inverters with two strings of photovoltaic (PV) panels in cascaded connection is proposed in this paper. The proposed modulation is developed based on the so-called circuit-level decoupling concept. It is able to provide balance line voltage even under unbalanced dc links. The unequal dc voltages appeared due to asymmetric maximum point of power trackings (MPPTs) are controlled by proper injection of zero-sequence voltage to the common mode voltage, while the total dc voltage is regulated based on the voltage commands generated by the MPPT of each string. Thus, both PV strings are able to be operated based on their MPPTs while there is almost no low-order harmonic distortion at the inverter output current. Compared with the previous methods, the high capability of the proposed method is evaluated by simulation study and experimental tests. [ABSTRACT FROM AUTHOR]

This paper presents an improved analytical model for estimating the high-frequency current ripple of interior permanent magnet synchronous machines due to pulsewidth modulation (PWM) switching. The proposed model accounts for the impact of slotting effect, magnetic saturation, and cross-coupling between the $d$ - and $q$ -axis. The model is subsequently used to investigate several factors that influence the PWM-induced current ripple. These include the PWM switching frequency, fundamental frequency (i.e., machine speed), dc-bus voltage, current control angle (i.e., γ angle), and the excitation current amplitude (i.e., saturation level). Experiments have been conducted to verify the analytical prediction results. These results show that the analytical model can predict the PWM-induced current ripple waveshape very well for many operating conditions and accurately estimate its rms value over a complete fundamental period. [ABSTRACT FROM AUTHOR]

This paper describes the spatial mode, frequencies, the voltage reference update timing, and their interaction of pulsewidth modulation (PWM) harmonics, focusing on a distributed winding permanent magnet synchronous motor. We investigated the electromagnetic force generating the noise by using a couple of analyses between a circuit simulator and a two-dimensional finite element analysis. It was found that the electromagnetic noise and vibration result from a radial electromagnetic force spaced at the spatial zeroth mode of $f_{c}\pm 3f_{1},f_{c}$ , and ${{2}}f_{c}$ ($f_{c}$ : carrier frequency, $f_{1}$ : fundamental frequency of the current). We have shown that the radial electromagnetic force of frequency $f_{c}\pm 3f_{1}$ and ${{2}}f_{c}$ results from PWM harmonics. Also, the radial electromagnetic force of frequency $f_{c}$ evidently results from the voltage reference update timing of ${{1/ }}f_{c}$. The electromagnetic noise and the spatial mode are demonstrated in the experiment. [ABSTRACT FROM AUTHOR]

This paper investigates an ac–dc–ac multilevel power converter. The studied configuration is composed of two single-phase ac–dc–ac three-leg modules and series-connected H-bridges in the shared part of system. Because the proposed converter has shared legs between the input and output, it is employed in applications with same input and output frequency. Uninterrupted power supply and unified power quality conditioner are application examples for this converter. Such multilevel topology has lower dc-link voltage rating, which, consequently, presents low switch blocking voltages when compared to conventional topologies. System model, a space-vector pulsewidth modulation (PWM) strategy to symmetrical and asymmetrical dc-link voltages, and an overall control strategy to adjust the system variables are presented. A power flux analysis shows the operation zone in which the individual dc-link voltage balancing is possible. PWM and control strategies are developed to reduce the semiconductor total losses, harmonic distortion, and switching stress. Two ac–dc–ac multilevel conventional structures are used for comparison. Simulation and experimental results demonstrate the feasibility of the studied converter. [ABSTRACT FROM AUTHOR]

This paper investigates a multilevel inverter composed of series/parallel-connected H-bridges. The presented structure can be used for applications in which the use of semiconductor switches with low-voltage and low-current ratings is intended. A comprehensive system model, an overall control strategy to adjust the output voltage with constant magnitude and frequency, and a level-shifted PWM (LS-PWM) strategy based on a voltage vectors unidimensional analysis and a plane analysis are presented. The LS-PWM is capable of mitigating the low-frequency circulating current, thus generating multilevel voltage signals with low harmonic distortion, maximum number of levels, and low dv/dt. In addition, considering a wide range of values of voltages and currents and various power levels, the total converter losses are reduced compared with the conventional multilevel converters. Two multilevel conventional inverters with the same number of semiconductor switches are used for comparison. Simulation and experimental results demonstrate the feasibility of the studied converter. [ABSTRACT FROM AUTHOR]

This paper presents a nine-level transformer-based inverter requiring only eight switches. The envisaged structure consists of two standard H-bridges fed from a single dc source. Besides, a single-phase transformer is employed to aid the process of intermediate voltage level generation. An ad-hoc pulsewidth modulation scheme based on boolean logic form equations is developed to derive the gating pulses. An effortless extension of the proposed inverter to a higher number of voltage levels is also achieved by generalizing the switching functions. Furthermore, the superior performance of the proposed topology is demonstrated through a comprehensive cost-based analysis. Finally, the validation of the proposed topology is accomplished through experiments on a down-scale prototype, and the measurement results are included. [ABSTRACT FROM AUTHOR]

In order to prevent the power switching devices (e.g., an insulated-gate bipolar transistor, IGBT) from shoot-through in voltage-source converters during a switching period, the dead time is added either in the hardware driver circuits of the IGBTs or implemented in software in pulse width modulation (PWM) schemes. Both solutions will contribute to a degradation of the injected current quality. As a consequence, the harmonics induced by the dead time (referred to as “dead-time harmonics” hereafter) have to be compensated in order to achieve a satisfactory current quality, as required by standards. In this paper, the emission mechanism of dead-time harmonics in single-phase PWM inverters is, thus, presented considering the modulation schemes in detail. More importantly, a repetitive controller has been adopted to eliminate the dead-time effect in single-phase grid-connected PWM converters. The repetitive controller has been plugged into a proportional-resonant-based fundamental-frequency current controller so as to mitigate the dead-time harmonics and also to maintain the control of the fundamental-frequency grid current in terms of dynamics. Simulations and experiments are provided, which confirm that the repetitive controller can effectively compensate the dead-time harmonics and other low-order distortions, and also, it is a simple method without hardware modifications. [ABSTRACT FROM AUTHOR]

This paper investigates power shunt filter topologies composed of three standard three-leg converters applied in either three or four-wire system. Compared with the usual three-phase shunt filter, the proposed ones allow us to reduce dc-link voltages, harmonic distortion or/and the semiconductor losses, and fault tolerant operation. Suitable control strategies to adjust filter and circulating currents, as well as the three dc-link voltages are presented. Two pulse-width modulation techniques are developed for the proposed topologies in order to achieve the best voltage-pulse pattern. Comparisons between these techniques are carried out in this paper. Simulation and experimental results are presented to validate the theoretical approach. [ABSTRACT FROM PUBLISHER]

This paper presents a hybrid pulse width modulation-based discontinuous modulation (D-HPWM) strategy with dc-link voltage balancing for a three-level neutral-point-clamped (NPC) traction inverter drive. The results are then compared with continuous-hybrid-PWM (C-HPWM) to check the performance improvement. The HPWM strategy uses both the advantages of carrier- and space-vector-based PWM strategies. The duty cycles are generated using the carrier-based strategy to reduce the computational time and complexity of the system and redundant vector states are used to keep the two dc-link capacitor voltages balanced. As discontinuous PWM (DPWM) reduces the switching losses considerably compared to the continuous PWM, the DPWM strategy is developed in this paper for the HPWM-based strategy. Detailed comparison studies are then carried out in MATLAB/Simulink and PLECS to show the conduction and switching loss distribution with change in modulation index for different power switches. A 54.0-kW surface permanent magnet synchronous machine (PMSM) is used for this simulation studies. Moreover, the total inverter loss and losses in each insulated gate bipolar transistor (IGBT) are also compared. Detailed experimental performance analysis is also carried out with a scaled down prototype of a 6.0-kW surface PMSM, NPC inverter, and real-time emulator DSpace, to show the capacitor voltage deviation with both control strategies. [ABSTRACT FROM PUBLISHER]

This paper presents a dc capacitor voltage balancing control method for the star-connected cascaded H-bridge pulsewidth modulation converter in the static synchronous compensator applications. With the zero-sequence voltage injection as a basis for dc capacitors voltage balancing, this paper investigates the detailed power flow of the converter as a whole and within individual modules under unbalanced grid voltages and then proposes a method to control the reactive power output and the dc capacitors voltage by precisely managing the power flow. This approach enhances the low-voltage ride-through capability, which is very critical as the penetration of distributed energy resources grows rapidly. The proposed control method is verified by a scaled-down prototype in the laboratory. [ABSTRACT FROM PUBLISHER]

Three optimized pulse-width modulated (PWM) techniques for the overmodulation region of two-level inverter-fed ac drives are introduced and investigated from the harmonic loss minimization point of view. The optimization is elaborated for the lowest loss-factor, which is proportional to the square of the root mean square value of current harmonics. The loss-factors are computed for different switching numbers as the function of the motor fundamental voltage. It is shown that, with respect to the motor heating and torque ripples, the acceptable drive condition can be guaranteed by a relatively low value of an inverter switching frequency up to 96%–97% of maximal possible motor voltage. Furthermore, it is shown that the so-called three-vector methods have considerably better performance in the lower part of the overmodulation region than the so-called two-vector method for the same number of switching. The performance of the techniques is compared with other existing PWM techniques. This paper discusses the implementation details of the proposed optimal PWM techniques. The theoretical results are verified by experimental and simulation tests. [ABSTRACT FROM AUTHOR]

Medium-voltage drives are regularly used in the petrochemical industry. These drives often vary in topology, semiconductor design, and principles of operation. They each have their own merits, not only in terms of structure, design, and reliability, but also with regard to suitability to specific applications. This paper presents a technology overview of commercially available medium-voltage drive topologies with a view on how they match to petrochemical applications. The operating and performance characteristics of each drive topology are reviewed while manufacturer-specific implementation details are excluded. Common industry and application requirements such as harmonics, motor compatibility, regeneration capability, dynamic performance, and robustness to system power disturbances are used as comparison criteria. Application aspects such as commissioning and operation challenges are highlighted from a practical point of view. [ABSTRACT FROM AUTHOR]

This paper presents an optimized topology for a \text3-\phi three-level inverter with complete elimination of common-mode voltage (CMV). The proposed multilevel inverter (MLI) configuration is realized by modifying a T-structure \text3-\phi inverter. The proposed configuration is an optimized solution with respect to the pulse-width modulation strategy used for CMV elimination. The given three-level inverter structure uses only 16 power semiconductor switches, which is much lower than the existing configurations. A reduced number of power semiconductor devices results in a diminished number of driver circuits, less installation space, and low cost. Further, due to the complete elimination of CMV, the proposed MLI is free from issues such as electromagnetic interference and leakage current with a reduction in filter requirement. The presented topology is also compared with other existing topologies to prove its advantage. It is an optimized solution with respect to the dc bus voltage requirement and the total voltage rating of the devices or the components used in the system. Simulation and experimental results are presented to confirm the capability of the proposed MLI. [ABSTRACT FROM AUTHOR]

As a result of dead-time, device on-state voltage drop, dc bus voltage measurement error, etc., volt-second errors degrade precise control of torque and flux linkage, particularly at low speeds. This is true for deadbeat-direct torque and flux control, which directly manipulates the volt-second vector sourced by inverters, as well as for indirect field oriented control drives. This paper introduces a real-time sensing scheme to measure the motor terminal volt-second vectors for each switching period with negligible phase lag. Based on the volt-second sensing, a model reference adaptive system-based approach is developed to decouple the volt-second errors from inverter nonlinearity, and dc bus voltage fluctuation and measurement error. By delivering an accurate volt-second vector for each switching period, torque and flux control accuracy, self-sensing performance, and parameter estimation accuracy are significantly enhanced. [ABSTRACT FROM AUTHOR]

This paper presents time-optimal control of an interior permanent-magnet synchronous machine (IPMSM) in voltage-limited and current-limited conditions using deadbeatdirect torque and flux control (DB-DTFC). A commanded air-gap torque and flux can be achieved by the end of each pulse width modulation (PWM) period using the DB-DTFC. However, it may take several PWM periods to achieve a desired torque that is physically infeasible in one step when operating near the voltage limit. The large torque command can be shaped as a feasible trajectory so that the deadbeat torque and flux is achieved for every sample time instant (switching period) along the trajectory. In this paper, the feasible trajectory is dynamically optimized to achieve a large torque command in the shortest time during the voltage-limited and current-limited operation. A loss-minimizing stator flux linkage is used during steady-state operation to reduce the computational complexity of the dynamic optimization and to operate the IPMSM at the loss-minimizing condition. The voltage-limited and current-limited operation of IPMSM drives is evaluated in both the simulation and experiment in this paper. [ABSTRACT FROM PUBLISHER]

Pulsewidth modulation (PWM) ac drives generate high line–line motor voltage, up to twice dc bus voltage, due to the reflected-wave phenomenon. Under certain conditions, motor voltage greater than twice the dc bus voltage can occur, resulting in winding insulation failure. It is well known that by suitably adjusting the PWM pulse pattern, the occurrence of voltages greater than twice the dc bus voltage can be avoided, up to a certain maximum cable length; beyond which, output filters are typically used to limit peak motor voltage. It will be shown in this paper that when the inverter operates in the pulse dropping region, voltages greater than twice the dc bus voltage will occur, with existing methods for pulse pattern compensation. A method to adjust the PWM pulse pattern in the pulse dropping region to ensure the same reflected-wave performance as the linear PWM region is presented in this paper. Experimental results are provided to demonstrate the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

Zero-sequence circulating current (ZSCC) has been a major concern for the operation of paralleled converters. Existing ZSCC reduction methods in the literature either suffer poor performances or are too complicated for modular implementation in an arbitrary number of interleaved converters. This paper investigates the application of interleaved carrier phase-shift (ICPS) pulse-width modulation (PWM) in modular interleaved converter system for ZSCC peak value reduction. The generalized study based on the derived ZSCC analytical expression reveals that the ICPS PWM can achieve superior ZSCC peak value reduction performance regardless the number of interleaved converters. Moreover, the impacts of ICPS PWM on the output voltage and current quality are also analyzed based on double Fourier integral. Compared with the conventional interleaved sinusoidal PWM (ISPWM), the output quality with the ICPS PWM can be comparable or even better. Simulation and experimental results show good agreement with the theoretical analysis, verifying the performance of the ICPS PWM. [ABSTRACT FROM AUTHOR]

Early detection of incipient faults in ac drives is one of the most difficult challenges for condition monitoring, especially for faults related to insulation degradation of the windings. In low power motors, the insulation degradation is principally due to the steep voltage variations caused by the voltage source converters that drive the machines. In the last years, with the coming to market of new no-Si based power devices, which achieve great values of dv/dt, fast tracking of electrical fault has became a topic of primary importance. In this paper, a new method to detect the presence of incipient faults in ultrareliable electric machines is presented and compared with a previous solution. The different methods were extensively evaluated by means of experimental results. It is shown that potential winding faults can be detected at an early stage of fault inception and thus measures can be taken to limit propagation. [ABSTRACT FROM PUBLISHER]

This paper proposes four open-end nine-phase conversion systems with a reduced number of controlled switches. For this to be achieved, a converter is shared among the three three-phase groups that compose the machine. In addition, in order to reduce the number of controlled switches even more, three of the studied topologies with a shared converter make use of diodes replacing some of the switches. Because of the shared converter, the configurations that make use of diodes are only applied for machines with no spatial shift between the machine three three-phase groups. Analysis of harmonic distortion for equal and unequal dc-link voltages is presented. It is shown that the harmonic distortion for configurations with diodes are higher when unequal dc-link voltages are used. Besides, study of machine torque ripple is performed and a pulse-width modulation strategy modification is made aiming torque ripple reduction for two of the proposed conversion systems. Simulation and experimental results are presented to validate the theoretical approach. [ABSTRACT FROM AUTHOR]

This paper proposes and investigates a new three-phase ac–dc–ac multilevel conversion system obtained from cascaded three-leg converters. Such configuration presents advantages in terms of reduced switch blocking voltages and consequently lower dc-link voltage rating. Operating principles, a pulse-width modulation (PWM) technique based on vector approach, and a control strategy are presented. The operation with different dc-link voltage values and a balancing method are discussed, and is supported by simulation and experimental results. The PWM technique is able to generate multilevel voltage waveforms, which permits reducing the switching frequency stress leading to reduced semiconductor losses. Simulation results are used to compare the proposed configuration with a conventional solution in terms of harmonic distortion and semiconductor losses. Experimental results demonstrate the feasibility of the studied converter, and were obtained by using a downscaled prototype with insulated gate bipolar transistors with dedicated drives and a digital signal processor with appropriated plug-in boards and sensors. [ABSTRACT FROM PUBLISHER]

This paper proposes a hybrid modular multilevel drive system based on a modular multilevel cascade inverter (MMCI) with double-star chopper cells (DSCC) and a two-level (2L) inverter to feed three-phase induction motors with open-end windings (OEWs). The proposed system is an alternative for high-speed motor drives based on a small-scale DSCC topology. A voltage reference technique is presented based on the analysis of the degrees of freedom of the system for generating the output voltage references, considering any voltage ratios of the dc links. The proposed system is evaluated in a symmetric scenario, in which the dc-link voltages are equal. Thus, the 2L inverter is set up to operate at the fundamental frequency, while the DSCC inverter synthesizes the output voltage references from high-quality waveform with a significant number of voltage levels. Experimental results obtained from a downscaled 10-kVA 380-V prototype driving a full loaded 3.7-kW OEW induction motor are provided to verify the viability of the proposed system. [ABSTRACT FROM PUBLISHER]

Common-mode voltage (CMV) in voltage-source inverters (VSIs) has been well defined and is frequently referred to in the literature. While often referred to, there is no real consistency with respect to how the CMV properties of an individual modulation scheme are evaluated, lacking tools to assess the relative merits or disadvantages of a certain topology or modification of a control scheme. The way that it is analyzed is still mostly a matter of the different authors' foci. In this paper, we propose a metric for the analysis of the CMV, aiming to fill the aforementioned gap. Thereby, the CMV in VSIs is quantified by the number of possible levels and the step sizes between different levels, as well as the respective frequencies of occurrence. The first two are given by the number of levels and the number of phases of the inverter. Depending on the modulation (control) schemes, all possibly available levels or a few of these levels are present in the CMV. We illustrate the use of the tool by applying it to thoroughly study the CMV properties intrinsic to the topologies of multilevel multiphase single- as well as double-ended diode-clamped VSI drive systems. As part of this analysis, we uncover new relationships concerning the existence of zero CMV level. Furthermore, we exemplarily apply the developed tool to the assessment of the CMV properties of selected pulse width modulation (PWM) control schemes and translate the findings into an interpretation of the endangerment of a given drive to suffer damage from inverter-induced bearing currents. The theoretical findings are supported by measurements. This paper also reviews the literature on CMV in multilevel multiphase VSI systems. With the proposed metric in mind, the CMV being mostly discussed as an element of different foci becomes even clearer, confirming again the need for the development of such a tool. [ABSTRACT FROM AUTHOR]

This paper presents a modified two-level three-phase inverter for the reduction of the leakage current. With respect to a traditional two-level inverter, the proposed solution reduces the common-mode voltage (CMV), both in amplitude and frequency. Between the dc source and the traditional three-phase bridge, two active dc-decoupling devices and a voltage-clamping network have been added. A dedicated control strategy was developed adopting a modified space vector pulse-width modulation, oriented to the reduction of the CMV. Simulations showing the good performance of the solution are presented. A preliminary prototype was developed and experimental results are presented. [ABSTRACT FROM PUBLISHER]

Inserted between the inverter and the ac motor for the purpose of providing clean sinusoidal voltage at the motor terminals, the pure sine filter (PSF) involves common-mode and differential-mode suppression components. When using PSF in a motor drive and employing advanced pulsewidth modulation (PWM) techniques with discontinuous modulation waveforms, a large common-mode current may circulate through the inverter and the filter resulting in overcurrent stress in the inverter and significant acoustic noise in the filter inductors. This paper first discusses the PSF and advanced PWM techniques, then investigates the performance issues that may arise when combining advanced discontinuous PWM methods with PSF and provides a curement for the overcurrent stress problems by means of a rate of change limiter. The simulations and detailed experimental studies illustrate the inverter overcurrent stress problems and the feasibility of the proposed method to cure the problems. Via experimental performance evaluation of various PWM methods, the paper also suggests, along with PSF, the use of advanced continuous and discontinuous PWM methods with reduced common-mode voltage for the purpose of performance enhancement and filter size reduction. [ABSTRACT FROM AUTHOR]

Three-level neutral point clamped (NPC) inverters exhibit a natural balancing property that can self-regulate the intermediate neutral point voltage to half the overall dc-link voltage. However, the underlying mechanisms of this process are not well understood, its performance under various load conditions has not been properly explored, and the requirements and benefits of ( $RLC$) balance booster filters to enhance the natural balancing response are not clear. This paper presents a generalized model of an NPC natural balancing process that allows these issues to be explored for various load structures and balance booster configurations (i.e., isolated wye, wye with a grounded star point, etc.). The model accurately predicts the dominant balancing time constant, identifies the harmonics that drive the balancing process, and can quantify the steady-state balance booster losses for a designed target natural balance response. Extensive simulation and experimental tests have been performed to validate the theoretical model. [ABSTRACT FROM PUBLISHER]

High-resistance ground (HRG) systems have gained popularity in process applications due to their ability to continue operation after a single line-to-ground fault and to limit the escalation of a single line-to-ground fault to a multiphase event. Part I of the companion paper has set the guidelines for designing safe and reliable HRG systems on industrial power systems used with linear loads and the effect of increased line–ground voltage stress on motor loads during fault conditions. However, literature on characteristics and pitfalls of HRG systems when used with nonlinear power converter systems is limited. Part II investigates anomalies of HRG systems used with nonlinear power converters such as neutral voltage shifting, increased line–ground transient fault voltages for both motor and ac source terminals and their voltage compatibility issues, increased neutral grounding resistor power dissipation, susceptibility of ground fault sensing equipment to nuisance tripping, and dc-bus voltage resonance on faults. Part II also investigates HRG zero-sequence fault current characteristics and paths observed under various fault locations in a common ac or a common dc-bus pulsewidth-modulated adjustable speed drive (ASD) system. Part II concludes with a summary of application guidelines when using ASD HRG systems. [ABSTRACT FROM PUBLISHER]

Current measurement and pulsewidth modulation (PWM) are critical components of modern current-controlled voltage source inverters. Current measurements enable accurate and robust closed-loop control of current, while PWM enables the efficient high-bandwidth regulation of the voltage. These two components do not operate independently, however. The synthesized voltage from PWM, a sequential series of discrete voltage levels, from a predefined finite set of possible levels, is only equivalent to the desired voltage on an average basis. As a result, the response of the electrical current to this synthesized voltage deviates from the response to the desired voltage. This deviation from the desired response, when combined with the standard synchronous sampling method, results in current measurement errors. This paper will present an analytical derivation of this current response deviation. This can be used to model the current measurement errors. A better understanding of this phenomenon will result in better design and control of power converter systems. The analytical work will be evaluated and verified using simulations and experimental measurements. [ABSTRACT FROM PUBLISHER]

This paper presents a saliency-based position sensorless drive of permanent-magnet (PM) machines using a single current sensor for cost-effective applications. For the single current sensor system, the dc-link current is measured for the reconstruction of three-phase currents. The phase current reconstruction can only be realized when active voltages are applied. This limitation results in six immeasurable areas for the current reconstruction using the pulsewidth modulation. In order to implement the saliency-based sensorless drive, a square-wave voltage is injected to minimize the harmonics of reconstructed saliency current for the rotor position estimation. By injecting a square-wave voltage on the direction of the rotor $d$-axis, the injection voltage vector is nearly perpendicular to the fundamental voltage vector at low speed. The saliency reflected current or the fundamental current can be separately reconstructed by the dc-link current, leading to the reduced reconstruction errors and improved sensorless performance. By using the proposed signal injection technique on a single sensor system, the saliency-based sensorless drive can work on an interior PM machine with a salient ratio of L_{q}/L_{d} = 1.35 at 1% rated speed (60/6000 r/min) under full torque load based on the experimental evaluation. [ABSTRACT FROM PUBLISHER]

This paper proposes a novel modulation technique and a new balancing control strategy for a single-phase five-level flying-capacitor (FC)-based active-neutral-point-clamped (ANPC) converter. The proposed modulator can control the FC voltage to follow the requested reference value and simultaneously generate the required ac output voltage regardless of the values of the dc capacitor voltages of the converter. By implementing this method, smaller values of the dc-link capacitor and FC can be used even in applications that could experience ripple or transient in the capacitor voltage. In a single-phase five-level ANPC converter applications, where the capacitors can experience pulsation power and dc-link balancing issues, such as grid-connected photovoltaic system, the selection of the reference voltage value for the FC can play an important role to balance the average values of the dc-link capacitor voltage. The proposed new control strategy uses a new reference voltage for the FC to be applied by the new modulator to have an average balanced dc-link voltages as well as an ac output voltage with good power quality. Simulation studies and experimental results demonstrate the effectiveness of the proposed modulation technique and control strategy even with relatively small dc capacitors to produce high-quality output voltage and current waveforms while maintaining an average balanced dc-link voltages. [ABSTRACT FROM PUBLISHER]

Although the operation of a three-phase current source rectifier (CSR) for ac-to-dc conversion using phase control or low-frequency pulse control is well established in a wide variety of applications, CSR realization using high-frequency pulsewidth-modulation control has been recently studied as a potentially competitive alternative to a voltage source rectifier. In the CSR, reverse blocking gate turn-off switches are realized using series-connected diodes, which prevent any reversal of the dc-link current. A significant consequence of this limitation occurs at light load conditions. The dc-link inductor current enters the discontinuous mode of operation and leads to the loss of the control of the output voltage and a highly distorted input current, which compromise the potential advantages of the approach. This paper characterizes the CSR while operating in the discontinuous conduction mode and proposes a modulation strategy that restores the control of the output voltage and ensures a nearly sinusoidal current at light loads. Simulation and hardware results are provided for a 3-kW laboratory-scale prototype system. [ABSTRACT FROM AUTHOR]

Buck-converter-based topologies are used to generate high-frequency sinusoidal outputs. Buck-based inversion circuits such as voltage source inverters or class-D amplifiers have inherent control-to-output linearity in large-signal sense. However, in these topologies, the instantaneous output is always smaller than the dc-input during linear modulation. A differential boost inverter (DBI) is a boost-based topology that is used to generate a sinusoidal output. In DBI, the instantaneous output can be higher or lower than the dc-input voltage. DBI exhibits nonlinear control-to-output behavior in large-signal dynamic sense. Therefore, generating a high-frequency sinusoidal output using this topology is a challenge. The issues associated with a DBI for high-frequency sine wave generation are characterized in this paper. Conventional linear and nonlinear control techniques fail to produce a high-quality sine wave output at higher operating frequency. A nonlinear feedback linearization technique is proposed, which forces the output to be linear with respect to the reference even at higher operating frequency. This leads to a high-frequency high-quality sine wave generation using a DBI. The proposed modulator is verified using a laboratory prototype to generate a sine wave up to 2 kHz. A triangular wave of 100-Hz frequency is also generated by the proposed technique. Superior dynamic responses of a dynamic linearizing modulator controlled DBI for a step change in frequency, load current, input voltage, and reference are also experimentally verified. [ABSTRACT FROM AUTHOR]

The paper presents a novel fixed switching frequency predictive current control method for switched reluctancemachines (SRM). The proposed deadbeat predictive current controller accurately predicts the required duty ratio for thePWM pulse for a given reference current in each digital time step over the entire speed range of operation. The pulsewidth depends on the operating conditions, machine parameters and the rotor position. The controller utilizes themachine inductance profile as a function of current and rotor position to accurately predict the required voltage. Thecontrol method is studied through computer simulation and followed by experimental validation. The method is suitablefor torque ripple sensitive applications requiring accurate tracking of a given current profile and mitigating theaudible noise due to the switching of the inverter. [ABSTRACT FROM AUTHOR]

In this paper, an online method to calculate the optimum dc bus voltage for motors and inverters with variable dc bus voltages is proposed. The required dc bus voltage in the low-speed region is much lower than that for the rated-speed region. As a result, the machine drive system efficiency can be improved with lower dc bus voltage since the switching losses in the inverter are reduced. To achieve both desired machine output torque and minimized losses simultaneously, an optimum dc bus voltage is required. However, machine parameter estimation errors and spatial harmonics in the machine result in calculation errors for the required dc bus voltage. A voltage disturbance state filter (VDSF), which is formed by a Luenburger-style closed-loop stator current vector observer with voltage command feedforward, is used to mitigate the calculation errors. Voltage errors caused by the parameter deviations and machine spatial harmonics will inherently be estimated by the observer's state feedback controller. Therefore, the calculation voltage error can be corrected by the VDSF's disturbance voltage so that the optimum dc bus voltage can be obtained. [ABSTRACT FROM PUBLISHER]

A new hybrid five-level inverter topology with common-mode voltage (CMV) elimination for induction motor drive is proposed in this paper. This topology has only one dc source, and different voltage levels are generated by using this voltage source along with floating capacitors charged to asymmetrical voltage levels. The pulsewidth modulation (PWM) scheme employed in this topology balances the capacitor voltages at the required levels at any power factor and modulation index while eliminating the CMV. This inverter has good fault-tolerant capability as it can be operated in three- or two-level mode with CMV elimination, in case of any failure in the H-bridges. More voltage levels with CMV elimination can be realized from this topology but only in a limited range of modulation index and power factor. Extensive simulation is done to validate the PWM technique for CMV elimination and balancing of the capacitor voltages. The experimental verification of the proposed inverter-fed induction motor is carried out in the linear modulation and overmodulation regions. The steady-state and transient operations of the drive are verified. The dynamics of the capacitor voltage balancing is also tested. The experimental results demonstrate that the proposed topology can be considered for industrial drive applications. [ABSTRACT FROM AUTHOR]

The advancement in power electronics has made the use of any number of phases in ac machines possible since with the inverter, any number of phase voltages can be realized as long as the corresponding inverter exists. To supply multiphase drives requires multiphase voltage source inverters (VSIs) whose output voltages depend very much on the methods of generating the pulses to turn on and turn off the inverter devices appropriately. This paper presents an analytical technique for the determination of the expressions for the modulation signals used in the carrier-based sinusoidal and generalized discontinuous pulse width modulation schemes for two-level, five-phase voltage source converters. These expressions can be used for both balanced and unbalanced phase voltages generated by any two-level multiphase inverter, in generating the required reference signals appropriately. An example of a five-phase VSI is presented to illustrate the strategy. Simulation and experimental results are presented in which a close examination shows that both results are similar for the balanced and unbalanced load voltage cases. [ABSTRACT FROM AUTHOR]

Operating a dual three-level inverter system from a single dc link circuit is an economic solution for generating five-level output voltage waveforms and to double the output power compared to a single three-level inverter. Such an inverter system is used for feeding a drive motor with open stator windings. A mechanism is then required to reduce the common-mode voltage components of the motor voltages. This paper describes an offline optimization method that minimizes both the harmonic distortion of the motor currents and the common-mode voltage components. The optimization permits reduction of the switching frequency to a very low value of 200 Hz without compromising the harmonic distortion. High performance operation of the drive system at low switching frequency is experimentally demonstrated. [ABSTRACT FROM PUBLISHER]

The inherent low switching frequency in medium-voltage alternating-current industrial drives presents power-quality and filter-design challenges. In this paper, four multilevel pulsewidth-modulation methods; phase disposition (PD), switching-loss minimization (SLM), and selective harmonic elimination (SHE) up to the 17th and 29th harmonics, respectively, are considered. The characteristics of long-cable effects on common-mode voltage (CMV) and differential-mode voltage (DMV), inverter losses and efficiency, induction machine voltage, and current harmonics are analyzed. Very little has been published in these quantitative comparisons. It is shown that the SHE method has reduced CMV as compared with the PD and SLM algorithms. Elimination of up to the 29th harmonic achieves the best harmonic performance without needing an output filter, at the expense that the losses are higher with a lower efficiency. Analytical and simulation results using the Piecewise Linear Electrical Circuit Simulation for the power-electronic circuits and MATLAB/Simulink for control systems are experimentally verified with a 1000-hp 4160-V neutral-point-clamped adjustable-speed-drive system that includes a 24-pulse front-end voltage source converter. [ABSTRACT FROM AUTHOR]

Red–green–blue (RGB) light-emitting diodes (LEDs) are finding widespread use due to recent advances in the LED technology. In this paper, a microcontroller-based RGB driver was designed to drive a 3 \times 3 RGB display panel. The proposed driver maintains the minimum drive voltage across the LEDs and current controllers required to keep it in regulation by selecting the minimum drain voltage of the MOSFETs of the current controllers; leading to reduced power dissipation in the MOSFET and increased efficiency in the LED string. The proposed LED driver system is also able to dim each individual LED in the pixel through a dimming controller circuit. Efficiencies of 85%, 90%, and 90% for the red, green, and blue LEDs, respectively, were experimentally verified at the maximum rated current for the RGB driver. [ABSTRACT FROM AUTHOR]