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The pump-back test is widely adopted in the industry for characterizing and qualifying high-power converters. One popular pump-back test configuration is to tie the dc links of two converters together and circulate the current through the inductor connected between the ac terminals. In this configuration, one of the converters operates in the voltage mode to generate the virtual grid and the other converter regulates the circulating current, where hysteresis control could be applied. However, the switching characteristics of hysteresis control are unique due to the pulsewidth modulation type voltage being the virtual grid. This paper contributes to analyzing the switching frequency characteristics of the hysteresis control in this pump-back test configuration. The switching frequency tracking phenomenon is revealed and reported in this paper for the first time. Theoretical analysis, simulation validation, and experimental demonstration are provided to support the major conclusions. [ABSTRACT FROM AUTHOR]

In this paper, the characteristics of ripple current of a multimegawatt drive system fed by a pulse-width modulation (PWM) inverter are investigated. Based on the investigation, a novel PWM scheme is devised to reduce the switching loss of the inverter under an identical amount of torque ripple of a motor. The proposed PWM is composed of two parts. The first is minimum torque ripple PWM (MTRPWM), which is optimized in terms of the minimum torque ripple in high modulation index (MI). The second determines the minimum switching frequency while holding the average torque ripple less than the allowable value under various operating conditions. It is termed reduced switching frequency PWM (RSFPWM). Consequently, by simply changing the PWM method from conventional fixed switching frequency continuous PWM to the proposed PWM, MTRPWM and RSFPWM, simulation results show that the switching loss of the inverter driving a 3.5 MW induction motor is reduced to 51.6% while keeping the torque ripple in the allowable boundary, where MI is 1.12. This approach is applied to small-scale experimental sets consisting of an interior permanent magnet synchronous machine (IPMSM) motor-generator set, and an induction machine MG set in an effort to verify the validity and feasibility of the proposed method. Based on these experimental results, the cost indexes of the IPMSM and the induction machine, as defined in this paper, decrease by up to 66% and 77%, respectively, when the proposed method is applied when MI is 1.12 compared with the outcome with the conventional PWM. [ABSTRACT FROM AUTHOR]

In this paper, it is described how the circulating current flows between inverters that have isolated dc link such as cascaded H-bridge (CHB) topology when they are operating in parallel. In this case, zero sequence circulating current, which normally flows through shared dc link, cannot flow between inverters in parallel. However, circulating current is provoked by asynchronous switching instant of devices, difference of dc-link voltages of parallel inverters, and unbalanced impedance. The circulating current should be suppressed by a sharing inductor that is inserted between inverters. Generally, all of the inverters should synthesize the same output voltage reference for load current control to minimize the size of this sharing reactor. However, this conventional method cannot guarantee diminishing circulating current in the transient state and even in the steady state. In this paper, in order to reduce sharing reactance, after deriving circulating current model from general case of n-parallel operation, circulating current control method is devised based on the model. This proposed algorithm is applied to active front end five-level-CHB inverter system for medium voltage drive. Simulation and experimental results are provided to verify the effectiveness of the proposed control scheme. [ABSTRACT FROM AUTHOR]

This paper proposes a new inverter topology based on the active neutral-point-clamped (ANPC) converter with capability to integrate one energy storage system (ESS) per inverter leg with an independent state of charge control, so that each inverter leg has two dc ports and one ac port. The primary dc port is common to all inverter legs and it is connected to the main power source. The secondary dc port is suitable for ESS connection because of its two-quadrant operation, with bidirectional current capability, so that the ESS can be charged and discharged with regulated current. Integration of a secondary dc port with independent control also allows the use of different ESS technologies for each inverter leg to compose a hybrid ESS. Redundant switching states of the proposed structure are used to balance the energy exchanged between the secondary dc port and the dc bus capacitors. Theoretical propositions were experimentally validated through a 1-kW single-phase inverter with a secondary dc port connected to a 230-V ESS and ac port connected to an LC filter feeding a linear load. Low total harmonic distortion (THD) sinusoidal current is generated at the ac port while charging or discharging the ESS with a constant current. [ABSTRACT FROM AUTHOR]

Recently multilevel inverters (MLIs) have received wide attention from industry and academia, as they are changing into a viable technology for diverse applications. To produce high-quality output using less switch count, development of novel reduced switch MLI (RS MLI) topologies has been a focus of current research theme. This paper presents design and control of a switched-diode dual source single switch MLI (SDDS MLI). The generalized SDDS MLI is first designed using an asymmetric basic unit. Proposed SDDS MLI requires less switch count and driver circuit count compared with the few recently developed RS MLI topologies. To improve the voltage quality by eliminating targeted low-order harmonics, a modified version of fish swarm optimization algorithm is examined for computing optimum switching angles required to control the SDDS MLI. Moreover, suitability and superiority of the derived algorithm are established by comparing with traditional selective harmonic elimination techniques. The developed topology is investigated through several MATLAB simulations as well as experimental tests in the laboratory applying the modified control approach. [ABSTRACT FROM AUTHOR]

A gate driving for power devices is a key technology to further improve switching characteristics. With the help of digital gate driver IC, the switching behavior of power devices can be enhanced even under high-speed switching. In this paper, an evaluation platform for determining the optimal switching pattern of an active gate drive control is proposed for an inverter circuit. A high speed optimization system is built up to search for an advantageous switching pattern that reduces total switching loss of two power devices in an inverter circuit and constrains surge voltage simultaneously. The proposed online optimization demonstrates its feasibility for the full-bridge inverter circuit, which is rated at 500 V with digital active gate drive control. Experimental results show that the proposed optimization system is able to obtain optimal switching pattern from $64^{60}$ possible combinations of switching patterns within 15 min, which is 6 times faster than the previous study. Optimizations can also conducted under different load current conditions. Eventually, the obtained optimal pattern yields up to 42% reduction in the total switching loss when it constrains surge voltage to minimum compared with the conventional driving pattern. [ABSTRACT FROM AUTHOR]

Three-phase voltage-source inverters typically feature a significant amount of dc energy storage to maintain a stiff dc bus. In these cases, the dc-link capacitor is sized to store enough energy to maintain several tens of cycles of ac output at the rated power. In this paper, we propose to reduce the size of the dc-link capacitor dramatically to store enough energy to provide just one high-frequency switching cycle of the ac output power. The dc bus is no longer stiff, and hence, classical sinusoidal pulse-width modulation cannot be used. However, the stored energy modulation (SEM) proposed herein synthesizes high-quality sinusoidal output voltage waveforms, even with such tiny dc-link capacitors. In SEM, the switching intervals of the interconnecting switches are carefully determined nonlinear functions of various operating parameters such as reactive component sizing, switching frequency, load levels, etc. This paper presents the analytical and detailed design development of the SEM approach along with circuit simulation, experimental results, and comparative evaluation of a dc-to-three-phase system example. [ABSTRACT FROM PUBLISHER]

One of the main challenges of the solid-state transformer (SST) lies in the implementation of the dc–dc stage. In this paper, a quadruple-active-bridge (QAB) dc–dc converter is investigated to be used as a basic module of a modular three-stage SST. Besides the feature of high power density and soft-switching operation (also found in others converters), the QAB converter provides a solution with reduced number of high-frequency transformers, since more bridges are connected to the same multiwinding transformer. To ensure soft switching for the entire operation range of the QAB converter, the triangular current-mode modulation strategy, previously adopted for the dual-active-bridge converter, is extended to the QAB converter. The theoretical analysis is developed considering balanced (equal power processed by the medium-voltage (MV) cells) and unbalanced (unequal power processed by the MV cells) conditions. In order to validate the theoretical analysis developed in the paper, a 2-kW prototype is built and experimented. [ABSTRACT FROM PUBLISHER]

Paralleled inverters have the merits of high power rating, improved reliability, and convenient maintenance. However, zero-sequence circulating current (ZSCC) will occur and lead to current distortion and system loss. The ZSCC control is more complicated when three-level topology is utilized and paralleled number is increased. Therefore, this paper proposes a simplified ZSCC suppression scheme for multi-paralleled three-level T-type inverters (3LT2Is). A novel equivalent model is developed and the ZSCC controller based on the new model is easier to implement. Thus, the number of paralleled inverters can be increased without complicating the control scheme and the inverters could be switched on or off optionally. Besides, Feed-Forward (FF) strategy is adopted to eliminate the ZSCC spikes caused by symmetrical three-level space vector modulation. The effectiveness of the proposed control scheme is verified by both simulation and experimental results. [ABSTRACT FROM AUTHOR]

This paper introduces a three-phase grid-connected inverter for commercial-scale photovoltaic systems. The circuit topology combines an ac-inductor-less active bridge with a parallel-connected pulsewidth modulation inverter acting as an instantaneous reactive power compensator. The active bridge, called a 120° conduction inverter, operates at a switching frequency equal to the grid frequency and outputs a 120° rectangular current, while the compensator eliminates the harmonic currents included in the rectangular current. The main advantage of this strategy is the reduction in size of the required ac inductor by a factor of 4, as well as the reduction of power losses in the switching devices. The theoretical analysis clearly shows that the compensator can synthesize a sinusoidal output current by controlling only instantaneous reactive power, thus eliminating the need for electrolytic capacitors. A 5-kW experimental setup validates the operating principle and the control method of the proposed inverter and exhibits an inverter efficiency as high as 99.2% with Si superjunction mosfets. [ABSTRACT FROM AUTHOR]

This paper proposes a switching strategy for the Z-source inverter (ZSI), which has unequal short-through intervals to reduce the current ripple in the inductor of its impedance source. A size reduction of the inductor of the ZSI is one of the important issues in improving the power density of the ZSI, and the inductor current ripple reduction is required to achieve it. The proposed method can reduce the inductor current ripple by 27.8% compared with the conventional method that has equal short-through intervals without increasing the number of inverter switching. The proposed operation and ripple reduction were confirmed in experiments with a 3-kW-class laboratory prototype. Its result agreed to the calculated results, and it was confirmed that there is no increase in circuit losses caused by the application of the proposed method. [ABSTRACT FROM AUTHOR]

In this paper, a new zero-sequence current suppression control strategy for the five-phase open-winding fault-tolerant fractional-slot concentrated-winding interior-permanent-magnet (FTFSCW-IPM) motor drive system with a common dc bus is proposed. By unequal distribution of the zero voltage vector, the proposed method can well suppress the zero-sequence current caused by the dead-time effect that the conventional eliminating method cannot be achieved. First, the dead-time effect to the zero-sequence current is discussed. Then the zero-axis controller is designed to obtain the reference common-mode voltage. Last, according to the principle of the unequal zero voltage vector distribution, the switching sequence of the two inverters can be calculated, and the maximum modulation index is also first deduced in detail. The proposed method is proved by the simulation and experimental results. [ABSTRACT FROM AUTHOR]

A discontinuous pulsewidth modulation (DPWM) strategy for three-level neutral-point-clamped (NPC) traction inverter drive for electric vehicles (EVs) with minimum switching loss for the full power factor (PF) range is developed and presented in this paper. Considering the dynamic loading conditions in an EV propelled by an induction motor (IM), the discontinuous modulation strategy is generalized to obtain minimum switching loss for a wide variations in load PF and modulation depth. The dynamic operating conditions in EV may render frequent unbalances in dc-link capacitor voltages in NPC inverter. It is demonstrated that the addition of an appropriate offset signal with the reference discontinuous signals generates compensating neutral current in the right direction, which can be used to mitigate existing unbalance in two dc-link capacitor voltages. Minimum switching loss at variable PF is attained by positioning the nonswitching clamped regions of the reference auxiliary signals according to the load PF. The effectiveness of the proposed scheme for a wide range of torque/speed variations is studied through simulation by developing a MATLAB/SIMULINK model of an IM traction inverter drive with field-oriented control strategy for closed loop control. Finally, the modulation scheme is validated through experimentation in a small-scale prototype NPC inverter with motor loads. [ABSTRACT FROM AUTHOR]

In this paper, a multipulse ac–dc converter fed multilevel inverter (MLI)-based indirect vector controlled induction motor drive (IVCIMD) is proposed for medium-power application. A 54-pulse ac–dc converter is utilized at the supply side to suppress the input current total harmonic distortion, as per the IEEE-519 standard. Mainly three separate isolated transformers are utilized and each transformer is configured as an 18-pulse ac–dc converter. Due to the phase shift in primary windings, these three transformers are reconfigured as a 54-pulse ac–dc converter. A 15-level binary-based cascaded MLI is utilized at the motor side to enhance the required performance of IVCIMD. A 15-level inverter is switched at fundamental frequency, which ensures the very low switching losses in the proposed IVCIMD. A modified nearest level modulation strategy is proposed to achieve fundamental switching frequency. The performance of the proposed IVCIMD is simulated at various operating conditions by utilizing Simulink/MATLAB platform. Simulated results are validated with experimental results on a developed prototype in the laboratory to show its usefulness for medium-power applications. [ABSTRACT FROM AUTHOR]

This paper presents a new least-mean-square (LMS) algorithm based deadtime compensation method to suppress the current distortion in permanent-magnet synchronous motor (PMSM) field-oriented control (FOC) drives. Compared to conventional average value compensations, the proposed method is robust to switching device parameter variations thanks to the online adaptation capability of the LMS algorithm. Similarly, the disturbance observer compensators are also immune to switching device parameter variations; however, varying motor parameters degrade their compensation performance. Without prior knowledge of switching device or motor parameters, the proposed method can directly reduce the deadtime current harmonics by generating compensation voltage references. In addition, the proposed method is easy to implement since it does not require voltage errors estimation or current harmonics extraction, which are necessary for disturbance observer and adaptive filter based methods. The proposed method is tested on a 2.5-kW voltage-source inverter PMSM drive controlled by an FOC algorithm. Its effectiveness is validated by both experimental results and spectrum analysis. [ABSTRACT FROM AUTHOR]

An adaptive control of DPWM implementable in clamped-three-level inverters with two strings of photovoltaic (PV) panels in cascaded connection is proposed in this paper. The proposed modulation is developed based on the so-called circuit-level decoupling concept. It is able to provide balance line voltage even under unbalanced dc links. The unequal dc voltages appeared due to asymmetric maximum point of power trackings (MPPTs) are controlled by proper injection of zero-sequence voltage to the common mode voltage, while the total dc voltage is regulated based on the voltage commands generated by the MPPT of each string. Thus, both PV strings are able to be operated based on their MPPTs while there is almost no low-order harmonic distortion at the inverter output current. Compared with the previous methods, the high capability of the proposed method is evaluated by simulation study and experimental tests. [ABSTRACT FROM AUTHOR]

Inverter dead-time is known to make open-loop induction motor drives oscillatory, while operating at light-loads in particular. While dead-time compensation schemes exist, precise compensation of the same is often challenging as it involves factors such as device and driver delays and switching transition times, which are difficult to be quantified accurately. Hence, the effect of dead-time could be under or overcompensated. This paper presents a comprehensive analysis of the impact of such undercompensation and overcompensation on the stability of a 100-kW induction motor drive, along with experimental investigations of the same. The effects of undercompensation and overcompensation on the inverter output voltage are analyzed on a switching-cycle average basis. Further, small-signal models are proposed for an open-loop drive, when it is undercompensated and overcompensated. Stability analysis of the above motor drive is reported, which predicts oscillatory behavior with both under and overcompensation, over certain fundamental frequency ranges, respectively. Further, two different types of oscillatory behavior, characterized by different oscillating frequencies, are observed for the cases of under and overcompensation. The analyses are supported by simulations. Experimental investigations carried out also support the analyses and simulation results. [ABSTRACT FROM AUTHOR]

This paper investigates a multilevel inverter composed of series/parallel-connected H-bridges. The presented structure can be used for applications in which the use of semiconductor switches with low-voltage and low-current ratings is intended. A comprehensive system model, an overall control strategy to adjust the output voltage with constant magnitude and frequency, and a level-shifted PWM (LS-PWM) strategy based on a voltage vectors unidimensional analysis and a plane analysis are presented. The LS-PWM is capable of mitigating the low-frequency circulating current, thus generating multilevel voltage signals with low harmonic distortion, maximum number of levels, and low dv/dt. In addition, considering a wide range of values of voltages and currents and various power levels, the total converter losses are reduced compared with the conventional multilevel converters. Two multilevel conventional inverters with the same number of semiconductor switches are used for comparison. Simulation and experimental results demonstrate the feasibility of the studied converter. [ABSTRACT FROM AUTHOR]

This paper presents a nine-level transformer-based inverter requiring only eight switches. The envisaged structure consists of two standard H-bridges fed from a single dc source. Besides, a single-phase transformer is employed to aid the process of intermediate voltage level generation. An ad-hoc pulsewidth modulation scheme based on boolean logic form equations is developed to derive the gating pulses. An effortless extension of the proposed inverter to a higher number of voltage levels is also achieved by generalizing the switching functions. Furthermore, the superior performance of the proposed topology is demonstrated through a comprehensive cost-based analysis. Finally, the validation of the proposed topology is accomplished through experiments on a down-scale prototype, and the measurement results are included. [ABSTRACT FROM AUTHOR]

The requirements for peripheral circuits of power converters are becoming more restrictive due to the enhancement of Si-based power devices and due to practical use of SiC device. In the design of modern high-speed switching converters, the stray inductances and capacitances both in the device package and in the gate drive circuit in addition to those in the main circuit of the power converter must be considered. In these situations, the gate driving technique represents the key technology for enhancement of high-speed switching ability of power devices, as there are design limitations to reduce the stray inductances and capacitances. So far, several active gate control methods have been proposed. Most conventional active gate drivers are configured using analog circuits such as transistors and diodes. Thus, it is difficult to reconfigure their control parameters to fit the stray inductances and capacitances after the implementation of power converter and gate circuits. As a solution to these problems, the authors have proposed a programmable gate driver IC, which is a digitally controlled circuit. This gate driver IC can control the gate current at 63 separate levels, operated by programmable fully digital 12-bit and clock signals. In this paper, an active gate current control based on the load current in a half-bridge inverter with two programmable gate driver ICs is demonstrated. This developed gate control is different to the general current feedback control followed the reference value. It is verified that the proposed active gate control can effectively improve the tradeoff relationship between the surge voltage and switching loss of the pulsewidth modulation half-bridge inverter circuit. [ABSTRACT FROM AUTHOR]

An optimal current control strategy for asymmetrical hybrid multilevel inverters (MLIs) is proposed in this paper enabling their use on motor drives, static synchronous compensators, and photovoltaic and wind generators, where a fast and precise current regulation is required. A key feature of these highly efficient converters is that an ac machine (motor or transformer) operates according to an open-end winding configuration, connected on one side to a main MLI and, on the other side, to an auxiliary two-level inverter (TLI). The first efficiently controls the main power stream operating at a low switching frequency, while the TLI acts as an active power filter, exploiting a conventional high-frequency two-level pulsewidth modulation (PWM) technique. The proposed control scheme optimally exploits the key features of the two inverters by suitably sharing the control task. In fact, a predictive current control is assigned to the MLI, which can be accomplished by low switching frequency operations, while the high switching frequency of the PWM-operated TLI is exploited to accomplish a fast and precise closed-loop current control, processing only a part of the power stream flowing through the system, thus producing low power losses. Simulations and experimental results confirm the consistency of the proposed approach. [ABSTRACT FROM AUTHOR]

This paper proposes new angles constraint for selective harmonic elimination-pulsewidth modulation (SHE)-PWM utilized in single-phase inverter applications. The proposed angles constraint naturally eliminates all triplen harmonics, whereas they conventionally appeared in all single-phase output voltages. The harmonic amplitude formula is developed based on the obtained angles constraint, and then modified single-phase SHE equations are defined to eliminate only specified low nontriplen harmonics. Therefore, more harmonics would be eliminated with the same switching frequency in modified SHE-PWM. Five-level voltage waveform has been opted to implement the introduced method, but it can be applied on all multilevel voltage waveforms such as seven-level with even number of angles. Unlike the conventional SHE technique, THD is analyzable in modified SHE to find optimum values for switching angles in order to control noneliminated harmonic amplitudes and minimize THD. Moreover, the cancellation of triplen harmonics empowers a single-phase inverter to supply nonlinear loads beside linear ones. Some experimental tests are accomplished using a single-phase five-level modified packed U-cell (MPUC) inverter. Results are discussed to prove the excellent performance of a single-phase MPUC inverter under both normal and harmonic loads and accurate elimination of determined triplen and nontriplen harmonics by applying the presented angles constraint. [ABSTRACT FROM AUTHOR]

This paper illustrates the application of a solving method of linear systems to a multilevel inverter. This study applies a generic pulsewidth modulation (PWM) method to a multilevel topology. This method finally highlights some specific modulation schemes. First, the study describes the mathematical model of the inverter leg. The leg is made of three level T-type structure. The model is extended to the three-phase inverter. The generalized inverse is used to generate the solution set of the conduction rates. Among the modulation strategies possible, three specific modulation schemes are proposed. The modulation schemes are applied to simulate a PWM three-phase inverter. Finally, some experimental results complete the analysis. [ABSTRACT FROM AUTHOR]

This paper presents an improved dc-link voltage balancing algorithm for a three-level neutral-point-clamped inverter by considering phase current direction. Detailed studies on the effects of change in load current direction on the dc-link capacitor voltages are presented. A maximum value of power factor is numerically derived, above which it affects the capacitor voltage balancing capability. Compared with the previously presented research work, the inputs to the space-vector pulsewidth-modulation block are the three phase currents and the difference between the two capacitor voltages. Depending on the states of the two dc-link capacitor voltages and phase current direction, redundant voltage vector sequences are selected. The selected vectors keep the capacitor voltage deviations within 5% of the total dc-link voltage. Two zero switching vectors (i.e., PPP and NNN) are also removed from all subsectors of the earlier proposed strategy, which one used to produce higher common-mode voltages. Detailed simulation and experimental results are presented in this paper for a 6.0-kW surface permanent-magnet synchronous machine. Both the simulation and experimental results show the required performance of the proposed system. [ABSTRACT FROM AUTHOR]

This paper is concerned with the use of a three-level inverter for a synchronous reluctance machine (SynRM). The SynRM suffers from a poor power factor due to poor machine saliency. This makes it harder to operate the three-level neutral-point-clamped inverter due to a strict requirement to have the two dc-link capacitor voltages balanced. This paper proposes a new nearest three vector modulation algorithm which can balance the two dc-link capacitors even at poor machine saliency ratio (poor power factor). In this paper, a method of sizing the two dc-link capacitors based on the machine power is also proposed. A comparison between two- and three-level inverters was conducted. The SynRM registered lower $d$-axis current ripple with a three-level inverter, indicating lower core losses in the machine. [ABSTRACT FROM PUBLISHER]

This paper proposes a novel bidirectional inverter, named series ac-link inverter. This three-phase inverter belongs to a new class of partial resonant ac-link converters in which the link is formed by a series ac inductor/capacitor (LC) pair having low reactive ratings. The input and output of this converter can be either dc, ac, single-phase, or multiphase. Therefore, they can appear as dc–dc, dc–ac, ac–dc, and ac–ac configurations. In all of these configurations, the ac capacitor is the main energy-storage element, and the inductor is merely added to facilitate the zero-current turnoff of the switches and their soft turn-on. Due to the zero-current turnoff of the switches in the proposed converter, the use of SCRs with natural commutation is possible as well. Since the current and voltage of the link are both alternating, no bulky dc-electrolytic capacitors are required in this converter. This paper mainly focuses on bidirectional dc to three-phase ac conversion. This single-stage inverter can step up or step down the voltage in a wide range. If galvanic isolation is required a single-phase high-frequency transformer can be added to the link. In the proposed inverter, the power can flow in both directions, and therefore, it is an excellent candidate for battery-utility interface and electric vehicle applications. In this paper, the principles of the operation of the proposed inverter, along with its design and analysis, are studied. Moreover, the performance of the proposed configuration is evaluated in this paper. Both simulation and experimental results are included. [ABSTRACT FROM AUTHOR]

This paper proposes a vector control strategy for independent control of two permanent-magnet synchronous motors (PMSMs) using a single four-leg inverter (4LI). An expanded two-arm modulation to obtain a balanced three-phase output voltage is described. This paper also proposes a method to compensate for the fluctuations in the neutral point voltage of two split capacitors in the dc link. The experimental results show that independent speed and position control of two PMSMs can be achieved using a single 4LI with the proposed vector control method. [ABSTRACT FROM AUTHOR]

Paralleled inverters are not only a suitable approach to increase the power capacity, but also have the capability of common mode voltage (CMV) reduction, or even elimination. The original zero CMV modulation scheme for paralleled inverters suffers from the current jump problem in phase-leg currents. This current jump phenomenon amplifies the peak values of differential-mode circulating current (DMCC) and zero-sequence circulating current (ZSCC), which is adverse for the design of coupled inductor and common-mode inductor. This paper introduces the modified modulation scheme, which can keep volt-seconds balance in whole fundamental period and mitigate the current jump in phase-leg currents. In addition, the reduction effect of the DMCC and ZSCC can be achieved. To verify the analysis, both the simulation and experimental results are presented, which validates the proposed methods and show that they are beneficial for DMCC and ZSCC reduction. [ABSTRACT FROM AUTHOR]

Three optimized pulse-width modulated (PWM) techniques for the overmodulation region of two-level inverter-fed ac drives are introduced and investigated from the harmonic loss minimization point of view. The optimization is elaborated for the lowest loss-factor, which is proportional to the square of the root mean square value of current harmonics. The loss-factors are computed for different switching numbers as the function of the motor fundamental voltage. It is shown that, with respect to the motor heating and torque ripples, the acceptable drive condition can be guaranteed by a relatively low value of an inverter switching frequency up to 96%–97% of maximal possible motor voltage. Furthermore, it is shown that the so-called three-vector methods have considerably better performance in the lower part of the overmodulation region than the so-called two-vector method for the same number of switching. The performance of the techniques is compared with other existing PWM techniques. This paper discusses the implementation details of the proposed optimal PWM techniques. The theoretical results are verified by experimental and simulation tests. [ABSTRACT FROM AUTHOR]

This paper presents a new compact three-phase cascaded multilevel inverter (CMLI) topology with reduced device count and high-frequency magnetic link. The proposed topology overcomes the predominant limitation of separate dc power supplies, which CMLI always require. The high-frequency magnetic link also provides a galvanic isolation between the input and output sides of the inverter, which is essential for various grid-connected applications. The proposed topology utilizes an asymmetric inverter configuration that consists of cascaded H-bridge cells and a conventional three-phase two-level inverter. A toroidal core is employed for the high-frequency magnetic link to ensure compact size and high-power density. Compared with counterpart CMLI topologies available in literature, the proposed inverter has the advantage of utilizing the least number of power electronic components without compromising the overall performance, particularly when a high number of output voltage levels is required. The feasibility of the proposed inverter is confirmed through extensive simulation and experimentally validated studies. [ABSTRACT FROM AUTHOR]

A constant switching frequency hysteresis controller based on current error space vector (CESV) for two-level voltage source inverter fed induction motor (IM) drive is proposed in this paper. Here the stator voltages along the α- and β-axes are estimated using current error information and steady-state model of IM. Estimated stator voltages, switching dwell times, and instantaneous voltage error vectors are used in the online hysteresis boundary computations. The steady-state CESV boundaries and the phase voltage normalized harmonic spectrum of the proposed hysteresis controller at different speeds resembles that of a constant switching frequency voltage-controlled bus clamping pulse-width modulation-based drive. The proposed controller exhibits adjacent voltage vector switching, fast dynamic response under transient conditions, and has a simple controller implementation. The superior performance of the proposed controller is simulated using MATLAB/Simulink platform and experimentally verified on a three-phase 2.2 kW IM drive. [ABSTRACT FROM AUTHOR]

This paper reports an elegant approach to address two major challenges of transformerless grid-connected microinverters, common-mode earth leakage current and double-frequency power pulsation across the photovoltaic (PV) terminal. The proposed solution uses an embedded decoupling capacitor in a doubly grounded boost–buck ( $\acute{\mathrm{C}}$ uk) derived topology. An intelligent switching scheme ensures that a large swing of the decoupling capacitor voltage is easily accommodated. Thus, film capacitors can be used instead of electrolytic capacitors, which helps increase equipment lifetime. Details of circuit operation are provided along with dynamic modeling and controller design for close-loop operation. Simulation and experimental results are presented for performance validation of the microinverter. [ABSTRACT FROM AUTHOR]

An observer-based control (OBC) strategy for dual-active-bridge converters is proposed in this paper. The target is not only to handle the active power transferring between two terminals, but also to regulate the phase difference between the primary voltage and current around specific minimum value. The value is chosen to reduce the conduction loss in the system. A reduced-order observer is developed to estimate the direct and quadrature components of the transmission current for use in a decoupled current control system. Since the dc terminal current is the only input of the observer, a low sampling frequency is enough to ensure an acceptable precision. Experiment results show that the proposed OBC strategy can help improve the dynamic performance compared with that when using a single loop voltage mode system. Furthermore, at the high power range, the efficiency obtained when employing the OBC method is improved by up to 7.2%. [ABSTRACT FROM AUTHOR]

In this paper, the direct torque control (DTC) for a three-level five-phase inverter-fed five-phase induction motor is proposed to improve the low-speed performance. The classical DTC scheme (DTC-I) is modified in order to minimize the demagnetization effect during a low-speed operation. According to the modification, the voltage vector space plane is divided into 20 sectors, each of sector 18°. For odd number of sectors, ${{\pm 36^\circ }}$ displaced intermediate voltage vectors, and for even number of sectors, ${{\pm 36^\circ }}$ displaced main voltage vectors are selected instead of classic ${{\pm 72^\circ }}$ displaced voltage vectors. The zero voltage vectors are omitted in the proposed DTC scheme (DTC-II) for the low-speed operation. The DTC-II scheme reduces the demagnetization effect during a low-speed region at the cost of increase in the torque ripple due to avoiding zero voltage vectors. As the speed ramps up, the ${{\pm 72^\circ }}$ displaced voltage vectors are selected through a seven-level torque comparator and are divided into ten sectors. Therefore, in the medium and the higher speed region, the torque ripple is reduced by using the seven-level torque comparator. Simulation and experimental results are presented in order to validate the DTC-II method. [ABSTRACT FROM PUBLISHER]

This paper discusses the use of a cascaded multilevel converter for flexible power conditioning in smart-grid applications. The main feature of the proposed scheme is the use of independent dc links with reduced voltages, which makes such a topology an ideal candidate for medium- and high-power applications with increased reliability. The developed control strategy regulates independent dc-link voltages in each H-bridge cell, and allows the selective and flexible compensation of disturbing currents under a variety of voltage conditions without requiring any reference frame transformation. The selective control strategies are based on the decompositions proposed in the conservative power theory, which result in several current-related terms associated with specific load characteristics. These current components are independent of each other and may be used to define different compensation strategies, which can be selective in minimizing particular effects of disturbing loads. Experimental results are provided to validate the possibilities and performance of the proposed control strategies, considering ideal and deteriorated voltage conditions. [ABSTRACT FROM PUBLISHER]

This paper proposes a new high-gain soft-switching dc–dc topology based on a switched inductor boost converter (SIBC). A conventional SIBC as a high gain boost topology has the issues of high conduction loss in switching diodes and high switching loss in the main switches. Also, it has severe electromagnetic interference (EMI) issue due to high-frequency ringing formed by parasitic inductance and diode junction capacitors. The new topology is derived with the objective of achieving zero voltage switching (ZVS) turn on of the main switch. Instead of adding extra active clamp zero voltage transition (ZVT) path at the switching node, the proposed topology augments the auxiliary ZVT path to the switching diode path. This is achieved by replacing the switching diodes with synchronous switches. The new topology can achieve soft switching for all the switches and alleviate the EMI issue. All the diodes achieve zero current switching (ZCS) turn off without reverse recovery. Auxiliary switches have ZCS turn on and ZVS turn off, and the main switches have ZVS turn on. The soft-switching SIBC also reduces the conduction loss in the switching diodes. A numerical simulation in PLECS and a prototype hardware are built corresponding to a micro-inverter application with 100 kHz switching frequency. Peak power conversion efficiency of 94.76% is achieved in the hardware prototype with Si devices. [ABSTRACT FROM PUBLISHER]

This paper presents a reverse mapping based space vector pulse-width modulation strategy for five- and seven-level diode-clamped multilevel inverters. In this method, the space vector is expressed as a sum of a contender vector and an error vector. Here, the actual sector, which contains the tip of the reference space vector, needs not to be found. The vector nearest to the reference space vector is the contender vector. By calculating the vector difference of the contender vector from the reference vector, the error vector is determined. Using translation method, the error vector is translated to the origin of space vector diagram. There will be (n–1) steps in space vector diagram for an n-level inverter. As the error vector amplitude will be less than one step of the space vector diagram, the two-level space vector method can be applied. To obtain a vector that is very close to the reference vector, the determined switching states can be added to the contender vector. This technique can be extended to any n-level multilevel inverter. The performance of five-level and seven-level diode-clamped multilevel inverters is presented using MATLAB/Simulink. The performance of inverters is evaluated by using induction motor load. The experimental results using field programmable gate array are presented for seven-level diode-clamped multilevel inverter. [ABSTRACT FROM PUBLISHER]

Space vector modulation (SVM) is a widely used method for multilevel inverters. Most of the SVM methods are nearest three vector (N3V) based schemes. Therefore, several researchers have proposed advanced implementation algorithms with reduced complexity for N3V methods. However, topologies like neutral point (NP) clamped inverter (NPCI) require some distinctive methods (called as non-N3V methods) to balance NP voltage for high modulation index and low power factor operations. Currently, the existing non-N3V methods exercise highly complex algorithms for duty ratio calculation and subtriangle identification. This paper presents a new approach, suitable for both N3V and non-N3V methods, with reduced implementation complexity. The proposed algorithm is based on an equivalent two-level space vector diagram and does not require any trigonometry, coordinate transformation, or volt-second balance solution. Unlike other carrier-based methods, it can change the switching sequence as well as the duration of redundant vectors. Moreover, the proposed approach does not require extra steps for implementing hybrid modulation and it can also be extended to multilevel topologies. One N3V, two non-N3V, and hybrid methods are developed using the proposed modulation algorithm, and are compared in detail. Simulation and experimentation on a three-level NPCI verify the validity of the proposed algorithm. [ABSTRACT FROM PUBLISHER]

This paper proposes an interleaved hybrid converter (IHC) with simultaneous dc and ac outputs for dc microgrid applications. The IHC is realized by interleaving two conventional boost converters and replacing the active switch of lower boost converter by an H-bridge voltage source inverter. This arrangement enables the proposed IHC to operate at the condition where the sum of duty ratio (\boldsymbolD ) and modulation index (\boldsymbolM ) can be more than or equal to one, i.e., \boldsymbolD + \boldsymbolM \geq 1, unlike the conventional hybrid converters. The proposed IHC is capable of giving dc with high voltage gain and improved ac with reduced harmonic distortion. Due to interleaving nature of the IHC, input current is shared between the power converters and thus enables the use of low current rated switching devices and lower values of inductors. This results in reduced power losses and increased efficiency as compared to the conventional hybrid converters. The IHC also has inherent shoot-through protection capability, better electromagnetic interference immunity, and reliability. A modified unipolar sinusoidal pulse width modulation technique is used to control the power flow of the IHC. Detailed mathematical modeling of the proposed IHC is carried out and its steady-state behavior is validated through experimental results on a 500 W laboratory prototype. [ABSTRACT FROM PUBLISHER]

In this paper, an ultralow inductance power cell is designed for a three-level active neutral point clamped (3L-ANPC) based on 650-V gallium nitride (GaN) high electron mobility transistor (HEMT) devices. The 3L-ANPC topology with GaN HEMT devices and the selected modulation scheme suitable for wide-bandgap devices are presented. The commutation loops, which mainly contribute to voltage overshoots and increase of switching losses, are discussed. The ultralow inductance power cell design based on a four-layer printed circuit board with the aim to maximize the switching performance of GaN HEMTs is explained. The design of gate drivers for the GaN HEMT devices is presented. Parasitic inductance and resistance of the proposed design are extracted with finite-element analysis and is discussed. Common-mode behaviors based on the simulation program with integrated circuit emphasis (SPICE) model of the converter are analyzed. Experimental results on the designed 3L-ANPC with output power of up to 1 kW are presented, which verifies the performance of the proposed design in terms of ultralow inductance. [ABSTRACT FROM AUTHOR]

The effect of inverter dead time on the inverter output voltage is well studied in the literature. This paper studies the effect of the dead time on the inverter input current. An expression for the switching-cycle-averaged inverter input current including the dead time effect is derived, which shows the dead time effect to primarily result in a reduction in the average value of the inverter dc input current. The effect of dead time on the input current is incorporated into the dc-link dynamic model of a diode-bridge-rectifier (DBR) fed voltage source inverter (VSI). A switching-cycle-average model of a DBR-VSI-fed induction motor is proposed, which considers the effect of dead time on both the ac output voltage and dc input current of the VSI. The proposed average model is used to study the light-load instability phenomenon in a 100-kW open-loop motor drive. The proposed model is shown to predict the region of oscillatory behavior (i.e., region exhibiting light-load instability) with better accuracy than existing average models. The proposed model also accurately predicts the dc-link voltage swing at such oscillatory operating points. While being comparable in accuracy in predicting the system dynamics, the proposed model is much more computationally efficient than the state-of-the-art switching model. The validity of the proposed average model is also confirmed by experimental measurements on a 100-kW induction motor drive. [ABSTRACT FROM AUTHOR]

This paper proposes a novel automatic mode transition control strategy for multiple inverters to operate in grid-connected and standalone modes. When grid is available, these inverters feed power the grid by operating in current control mode. Upon grid failure, all inverters automatically shift to droop control mode for achieving proportional power sharing and shift back to current control mode when the grid becomes available. The synthesis of dual structure control algorithms of various inverters is achieved using novel state machines. These state machines are designed to facilitate smooth mode transition of the inverters. In this way, the control signals for mode transition are generated by state machines specific to each inverter. Unlike existing control methods, the proposed method neither requires communication-based supervisory control of inverters nor it requires dedicated storage facility for achieving smooth mode transition. The proposed control strategy is tested on a simulation model as well as an experimental prototype multi-inverter system. [ABSTRACT FROM PUBLISHER]

This paper proposes a new nine-level inverter for medium- and high-power applications. The proposed topology comprises of a three-level (3L) active neutral-point-clamped (ANPC) inverter connected in series with a floating capacitor (FC) fed H-bridge. Besides, two additional switches operating at line frequency are appended across the dc link of the 3L ANPC structure. Compared with conventional hybrid cascaded inverters, the primary advantage of this addition is doubling of the resulting root mean square output voltage. This amelioration is achieved while preserving the standard 3L ANPC and H-bridge structures with minimum topological modification. A simple logic-gate-based voltage balancing scheme is developed to regulate the FC voltage. The proposed voltage balancing method is independent of load power factor, inverter modulation index, and can balance the voltage across FC instantaneously. The step-by-step formulation of logical expressions for the generation of gating pulses is deliberated in detail and can be generalized for any $n$-level inverter. Further, simulation results as well as the experimental measurements obtained from the laboratory prototype are presented to validate the effectiveness and practicability of the proposed configuration. Finally, the notable merits of the proposed inverter over the prior art topologies is established through a comprehensive comparative study. [ABSTRACT FROM PUBLISHER]

Transformer-less grid-connected photovoltaic (PV) systems face the challenge of keeping low leakage current due to their nonisolation configurations. To better attenuate the leakage current in the single-phase systems, a few neutral-point-clamped (NPC) topologies have been proposed. This paper further proposes an active NPC method by only employing one additional switch to connect the midpoint dc link and the freewheeling circuit of traditional single-phase PV inverters. After exploring the operational principles of freewheeling circuits, the construction method and the implementation of active NPC circuits in transformer-less single-phase inverters are elaborated in detail. Since only the leakage current flows through the additional NPC switch, the presented single-phase NPC inverters could still maintain the high operational efficiency with the further attenuated leakage current. The experimental results verified the theoretical findings. [ABSTRACT FROM PUBLISHER]

In order to increase the output voltage levels and reduce the isolated dc sources, a symmetrical hybrid nine-level inverter for high-speed motor drive applications is presented in this paper. Each phase of this inverter is composed of a five-level dc/dc converter cell and an H-bridge cell. The dc/dc converter is operated at high frequency with low-voltage devices and the H-bridge is operated at fundamental frequency with high-voltage devices. The three phases are connected to a common dc-link and each drives an isolated winding of an open-winding motor. The operating principles and modulation method are introduced. A detailed analysis of the average currents through the flying capacitor and neutral point of the dc-link is presented and a capacitor voltage balancing method based on phase-shifted pulse-width modulation is proposed. Simulation and experimental results are presented to demonstrate the feasibility of this topology and control method. [ABSTRACT FROM PUBLISHER]

This paper presents an original modular plug-in-type assembly approach for a single-phase inverter. The main focus here is, indicatively, on the power range 1–20 kW, but the methodology can be transferred to higher power levels too. At the core of the inverter lies a power-dense double-sided-cooled half-bridge power switch architecture with integrated cooler, which is interconnected to filter elements, gate driver, and control circuitry by means of compact flat connectors. The integration exercise targets, on the one hand, the optimization of the power switch performance and reliability, as well as the reduction of circuit parasitic elements; on the other, the production of a system compatible with maintenance and repairing, featuring minimized impact of single component failure on the system maintenance and repair cost, and, thus, on its availability. Preliminary experimental tests demonstrate the nominal functionality of the inverter. [ABSTRACT FROM PUBLISHER]

Open-switch faults in inverter-driven electric drives have recently gained increasing attention in the scientific community. Since these faults may lead to undesired effects, their fast and unambiguous detection is desirable. This paper proposes a detection algorithm for open-switch faults, which is based on the observation of the current control deviation and a subsequent test procedure. This algorithm detects the fault immediately after its occurrence within a few switching periods, even during transient operation. The proposed method is tested via simulations and experiments at different operating points of a surface permanent magnet drive. [ABSTRACT FROM PUBLISHER]

This paper presents an optimized topology for a \text3-\phi three-level inverter with complete elimination of common-mode voltage (CMV). The proposed multilevel inverter (MLI) configuration is realized by modifying a T-structure \text3-\phi inverter. The proposed configuration is an optimized solution with respect to the pulse-width modulation strategy used for CMV elimination. The given three-level inverter structure uses only 16 power semiconductor switches, which is much lower than the existing configurations. A reduced number of power semiconductor devices results in a diminished number of driver circuits, less installation space, and low cost. Further, due to the complete elimination of CMV, the proposed MLI is free from issues such as electromagnetic interference and leakage current with a reduction in filter requirement. The presented topology is also compared with other existing topologies to prove its advantage. It is an optimized solution with respect to the dc bus voltage requirement and the total voltage rating of the devices or the components used in the system. Simulation and experimental results are presented to confirm the capability of the proposed MLI. [ABSTRACT FROM AUTHOR]

As a result of dead-time, device on-state voltage drop, dc bus voltage measurement error, etc., volt-second errors degrade precise control of torque and flux linkage, particularly at low speeds. This is true for deadbeat-direct torque and flux control, which directly manipulates the volt-second vector sourced by inverters, as well as for indirect field oriented control drives. This paper introduces a real-time sensing scheme to measure the motor terminal volt-second vectors for each switching period with negligible phase lag. Based on the volt-second sensing, a model reference adaptive system-based approach is developed to decouple the volt-second errors from inverter nonlinearity, and dc bus voltage fluctuation and measurement error. By delivering an accurate volt-second vector for each switching period, torque and flux control accuracy, self-sensing performance, and parameter estimation accuracy are significantly enhanced. [ABSTRACT FROM AUTHOR]

In recent years, a three-level T-type inverter has attracted considerable attention due to its advantages, such as simple structure and higher efficiency. However, the reliability of a three-level T-type inverter is particularly important as increased power switches are used. Therefore, a fault-tolerant three-level T-type inverter is proposed in this paper. Fault diagnosis and fault-tolerant control strategies for power switches both in half-bridge and neutral-point bridge are investigated. Under fault-tolerant operation, redundant fourth-leg is used to balance neutral-point voltage and the low-frequency voltage oscillation is eliminated completely. The fault ride-through capability and high-quality output waveforms can be obtained. The effectiveness of the proposed inverter topology and control methods is validated by the simulation and experimental results. [ABSTRACT FROM AUTHOR]