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CMOS RF switches support watt-level RF output power while enabling signal processing with high speed. Typically, RF FET switches offer a tradeoff between a power handling and modulation bandwidth. This paper investigates the cause of compression in a FET switch, and the analysis suggests the optimization of the gate driving impedance for a stacked-FET switch. A design methodology is presented to realize watt-level power handling with high fractional bandwidth (FBW). The measurements demonstrate a BPSK modulator that can handle up to 10 W with wide FBW. The high-power, low-insertion loss, and high-modulation bandwidth demonstrate record performance. [ABSTRACT FROM AUTHOR]

Series stacking of multiple devices is a promising technique that can help overcome some of the fundamental limitations of CMOS technology in order to improve the output power and efficiency of CMOS power amplifiers (PAs), particularly at millimeter-wave (mmWave) frequencies. This paper investigates the concept of device stacking in the context of the Class-E family of nonlinear switching PAs at mmWave frequencies. Fundamental limits on achievable performance of a stacked configuration are presented along with design guidelines for a practical implementation. In order to demonstrate the utility of stacking, three prototypes have been implemented: two fully integrated 45-GHz single-ended Class-E-like PAs with two- and four-stacked devices in IBM's 45-nm silicon-on-insulator (SOI) CMOS technology, and a 45-GHz differential Class-E-like PA with two devices stacked in IBM's 65-nm low-power CMOS process. Measurement results yield a peak power-added efficiency (PAE) of 34.6% for the two-stacked 45-nm SOI CMOS PA with a saturated output power of 17.6 dBm. The measurement results also indicate true Class-E-like switching PA behavior. A peak PAE of 19.4% is measured for the four-stacked PA with a saturated output power of 20.3 dBm. The two-stacked PA exhibits the highest PAE reported for CMOS mmWave PAs, and the four-stacked PA achieves the highest output power from a fully integrated CMOS mmWave PA including those that employ power combining. The 65-nm CMOS differential two-stacked PA exhibits a peak PAE of 28.3% with a saturated differential output power of 18.2 dBm, despite the poor ON-resistance of the 65-nm low-power nMOS devices. This paper also describes the modeling of active devices for mmWave CMOS PAs for good model-hardware correlation. [ABSTRACT FROM PUBLISHER]

In this paper, the stress memorization technique (SMT) effects upon ultra-wideband RF switch performance are investigated for the first time. Low insertion loss (IL), high isolation, ultra-wideband (dc to 50 GHz) single-pole double-throw (SPDT), and single-pole four-throw (SP4T) switches designed with commercial 0.13- \mu \textm high-resistivity (HR) trap-rich SOI technology with/without SMT are presented and investigated. 2.5 V nMOS transistor ( Lg = 0.2~\mu \text{m} ) with low R\mathrm{\scriptscriptstyle ON} {^\ast} C\mathrm{\scriptscriptstyle OFF} from GF 130RFSOI PDK is used. It is found that channel mobility of switch transistor is improved by SMT and thus switch performance can be further improved. Moreover, the impact of transistor channel length, which has dominant effects on both IL and isolation of the switches, under different gate bias on switch performance are also studied and verified experimentally. Low measured IL of less than 2.1 dB and good isolation of better than 27 dB from dc to 50 GHz are obtained for the SPDT switch. For SP4T switch, the measured IL of less than 2.6 dB and isolation of better than 27 dB are achieved from dc to 35 GHz. The active chip areas of designed SPDT and SP4T switches are compact with size of only 0.214 \times 0.19~\text mm^2 and 0.36 \times 0.19~ \text mm^2 , respectively. [ABSTRACT FROM AUTHOR]

In this paper, a highly efficient class-G supply modulator targeting high-power wideband envelope tracking applications is presented. The maximum output power using a 50% duty cycle at 100-MHz switching frequency is 62 W for a switching between 30 and 50 V delivered in a 25- $\Omega $ load. The modulator including its driver circuit reaches an overall efficiency in the range of 97%–88% for switching frequencies from dc to 100 MHz for passive loads in a wide range. The modulator is designed to operate at various supply voltage levels and is evaluated within the range from 20 to 50 V while powering loads from 25 to 100 $\Omega $ . The modulator is characterized in terms of efficiency, switching frequency, and nonlinearities. [ABSTRACT FROM PUBLISHER]

This paper presents the analysis of a novel high-pass filter/low-pass filter (HPF/LPF) switching concept. Since an HPF/LPF switching concept has a periodic structure, its equivalent circuit is almost the same as an LPF for the ON-state and is the same as an HPF for the OFF-state. The broadband isolation characteristics with low insertion loss can be achieved by designing its cutoff frequency. A three-stage single pole single throw InGaAs pseudomorphic high electron mobility transistor monolithic microwave integrated circuit switch based on the HPF/LPF switching concept is successfully demonstrated with an insertion loss of less than 1.6 dB and isolation of more than 82 dB below 6 GHz, with a size of 1.1 mm $\times \,\, 1.0$ mm. The RF performances are in good agreement with the theoretical calculations. The measured input power of 1-dB insertion loss compression, P1dB, and the measured third-order intercept point, IIP3, are 19 and 27.7 dBm, respectively, at 1.95 GHz. The measured ON-time is 5.5 ns without cable delay. The measured rise time is as fast as 1.4 ns. [ABSTRACT FROM AUTHOR]

This paper presents the design and characterization of dc–dc converters operating at microwave frequencies. The converters are based on GaN transistor class-E power amplifiers (PAs) and rectifiers. Three topologies are presented, which are: 1) a PA and synchronous rectifier, requiring two RF inputs; 2) a PA and self-synchronous rectifier with a single RF input; and 3) a power oscillator with a self-synchronous rectifier with no required RF inputs. The synchronous 1.2-GHz class-\E^2 converter reaches a maximum efficiency of 72% at 4.6 W. By replacing the RF input at the rectifier gate with a specific termination, a self-synchronous circuit demonstrates 75% efficiency at 4.6 W, with a maximum output power of 13 W at 58% efficiency. In the third topology, the PA is replaced by a power oscillator by providing correct feedback for class-E operation, resulting in a circuit requiring no RF inputs. This oscillating self-synchronous dc–dc converter is demonstrated at 900 MHz with an efficiency of 79% at 28 V and 12.8-W output power. Self-synchronous class-E transistor rectifier operation is analyzed theoretically in the time domain and validated with harmonic-balance simulations using an improved nonlinear model for a GaN HEMT. The simplified theoretical analysis provides a useful starting point for high-efficiency self-synchronous power rectifier design, which can, in turn, be extended to high-efficiency oscillating power inverter design. [ABSTRACT FROM AUTHOR]

Design and analysis of two high-speed high dynamic-range track-and-hold amplifiers are presented in this paper using 65- and 90-nm CMOS processes. To achieve remarkable circuit performance in the advanced CMOS regime, the cascode topology with an inductive peaking technique and the distributed topology are employed in the track-and-hold amplifiers. The circuit topology is investigated to obtain the design methodology of the CMOS high-speed high dynamic-range track-and-hold amplifier. The theoretical calculation is presented to completely verify the design concept. Moreover, the proposed CMOS track-and-hold amplifiers demonstrate wide bandwidth and good linearity. With a dc power consumption of 197 mW, the 65-nm CMOS track-and-hold amplifier features an input bandwidth of up to 7 GHz, a spurious-free dynamic range (SFDR) of 44.6 dB, and a total harmonic distortion (THD) of -\44.5 dB. With a dc power consumption of 216 mW, the 90-nm CMOS track-and-hold amplifier features an input bandwidth of 19 GHz, an SFDR of 47.5 dB, and a THD of -\44.5 dB. The proposed CMOS track-and-hold amplifiers are suitable for the high-resolution high-speed analog-to-digital converter with low dc supply voltage and power. [ABSTRACT FROM PUBLISHER]

This paper presents two different types of high-power gallium–nitride (GaN) phase shifters designed for X-band (8–12 GHz), but offering good performance over a much wider band. The first is a 22.5^\circ switched-filter phase shifter, which has much wider bandwidth than is typically found with this configuration, while maintaining low insertion loss (<2 dB), good return loss (>11.15 dB), and an amplitude imbalance of less than 1.03 dB across X-band. The 1-dB compression point was higher than laboratory equipment was able to measure (>38 dBm) and the phase shifter monolithic microwave integrated circuit exhibited an input-referred third-order intercept point (IIP3) of 46.2 dBm. The second phase shifter is a novel design, which promises wide bandwidth (in our case, limited by the single-pole double-throw switch we have also designed), but which achieves decent insertion loss (5 dB), good return loss (better than 11 dB), and very low phase variation (1^\circ) across X-band, also with 22.5^\circ phase shift. It offers a 1-dB compression point of 30.1 dBm and an IIP3 of 46.3 dBm. The components for a 45^\circ differential phase shift using the same structure were also fabricated and verified with measurements. The high-power phase shifters have been fabricated in a 0.5-\mu\ m GaN HEMT process and were designed using an accurate customized switch field-effect transistor model. [ABSTRACT FROM PUBLISHER]

In this paper, a dynamic stack-controlled CMOS FET RF power amplifier (PA) is developed to enhance the efficiency of the envelope tracking power amplifier (ET PA) system for low-voltage operation. The power cell used in the two-stage PA is a quadruple-stacked FET structure with dynamic stacking controller to reconfigure the power cell into the quasi-triple or quasi-double stacks according to the magnitude of the input envelope signal. The proposed power cell boosts the peak efficiency in the low VDD region by bypassing the stack entering the triode region and reoptimizing the load impedance so that all the FETs operate under the saturation and the optimum load conditions. A detailed analysis is presented to understand the gain and phase step discontinuities at the stack switching points, and the circuit techniques to equalize the gain and phase between the adjacent stack configurations are developed. The proposed two-stage stack-controlled PA is fabricated with a 0.32-\mu\ m silicon-on-insulator (SOI) CMOS process together with the envelope amplifier (EA). Full long-term evolution (LTE) characterization is performed using LTE signals with a peak-to-average power ratio (PAPR) of 6.7 dB and signal bandwidths (BW) of 10 and 20 MHz. With 10-MHz signals, dynamic stacking provides 3.5% power added efficiency (PAE) improvement over the static stack at 25.7 dBm, resulting in 47.5% PAE with 26.6-dB gain. A 20-MHz LTE test shows an overall PAE of 45.9% with an evolved universal terrestrial radio access (E-UTRA) adjacent channel leakage ratio (ACLR) of -33 dBc with memoryless digital predistortion. Even with the lower efficiency of the EA compared with the state-of-the-art results, the measured overall system efficiency with 3.4 V maximum voltage is comparable with those reported using GaAs HBT's with 5 V supplies, which clearly demonstrates the advantages of the proposed dynamic stack control. [ABSTRACT FROM AUTHOR]

Considering the tradeoff between efficiency and output ripple over a wide load range, a monolithic dc–dc buck converter with switch-on-demand modulation (SODM) and switch size control (SSC) is presented in this paper. SODM achieves a hybrid mode of pulse skip and pulse width modulation (PWM) without mode detection circuit. The converter's on time is adaptively adjusted with the load demand, achieving low output voltage ripple. Detecting the output of the error amplifier by a comparator, the SSC circuit can select appropriate switch size according to load current for reducing switching loss in a light load. The threshold level of the comparator varies with respect to the amount of slope compensation, which maintains a substantially constant switch size changing point. Experimental results show that the fabricated converter with the proposed scheme achieves high efficiency from 83% to 96% over a wide load range from 10 mA to 5 A. The switch size is 1/4 of the maximum value when load current is below 1 A with 0.5-A hysteresis. Also, the measured maximum output ripple is less than 10 mV. [ABSTRACT FROM PUBLISHER]

In a wideband receiver, higher frequency channels may be converted to the frequency of a desired signal by a harmonic mixing mechanism. To alleviate this issue, this paper proposes a topology, called the classBlike converter, to achieve high harmonic mixing rejection in frequency translation without any filtering. The converter is based on a linear commutation with a sinusoidal local oscillator for a small harmonic mixing, while its gain and noise performances are comparable to that of a switching-type converter. Most important, the circuitry of the proposed converter is simple and can be incorporated with other harmonic rejection techniques. The circuit is implemented with a 0.18-\mum 1.8-V CMOS technology and the power consumption is 4.8 mW. Measurement results indicate that the third- to ninth-order harmonic rejections are more than 45 dB in average within a 4-GHz frequency range. A polyphase prototype with the proposed converter achieves higher than 70-dB third-order harmonic rejection even under a 2^\circ phase and 2% gain mismatch. [ABSTRACT FROM AUTHOR]