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Reliability-focused benchmarks are used to test systems in harsh operating conditions, including space and terrestrial radiation environment. The sensitivity to single-event effects of a microprocessor in a radiation environment depends on the set of input vectors used at the time of testing due to logical masking. This article analyzes the impact of the input test set on the cross section of the microprocessor and proposes a mechanism to derive a high-quality input test set using automatic test pattern generation (ATPG) for radiation testing of microprocessor’s arithmetic and logical units.

Integration-technology feature shrink increases computing-system susceptibility to single-event effects (SEE). While modeling SEE faults will be critical, an integrated processor’s scope makes physically correct modeling computationally intractable. Without useful models, presilicon evaluation of fault-tolerance approaches becomes impossible. To incorporate accurate transistor-level effects at a system scope, we present a multiscale simulation framework. Charge collection at the 1) device level determines 2) circuit-level transient duration and state-upset likelihood. Circuit effects, in turn, impact 3) register-transfer-level architecture-state corruption visible at 4) the system level. Thus, the physically accurate effects of SEEs in large-scale systems, executed on a high-performance computing (HPC) simulator, could be used to drive cross-layer radiation hardening by design. We demonstrate the capabilities of this model with two case studies. First, we determine a D flip-flop’s sensitivity at the transistor level on 14-nm FinFet technology, validating the model against published cross sections. Second, we track and estimate faults in a microprocessor without interlocked pipelined stages (MIPS) processor for Adams 90% worst case environment in an isotropic space environment.

The current LHCb readout system will be upgraded in 2018 to a ‘triggerless’ readout of the entire detector at the LHC collision rate of 40 MHz. The corresponding bandwidth from the detector down to the foreseen dedicated computing farm (event filter farm), which acts as the trigger, has to be increased by a factor of almost 100 from currently 500 GBit/s up to 40 TBit/s. The event filter farm will pre-analyse the data and will select the events on an event by event basis. This will reduce the bandwidth down to a manageable size to write the interesting physics data to tape. The design of such a system is a challenging task, why different technologies are considered and have to be investigated for the different parts of the system. For the usage in the event building or in the event filter farm (trigger) an experimental FPGA accelerated computing platform is considered and therefore tested. FPGA compute accelerators are more and more used in standard servers like for Microsoft Bing search or Baidu search. The platform we use hosts a general CPU and an high performance FPGA linked via an high speed link. On the FPGA an accelerator is implemented. The used system is a two socket platform from Intel with a Xeon CPU and an FPGA. The CPU and the FPGA are connected via the point-to-point interconnect QPI, which is used to interconnect CPUs in industry standard server. The FPGA has cache-coherent memory access to the main memory of the server and can collaborate with the CPU. These cache-coherent architectures are better suited for real-time connections between FPGA and CPU as the usual PCIe FPGA accelerators. It is very likely that these platforms, which are built in general for high performance computing, are also very interesting for the High Energy Physics community. As First step it is tested to port the an existing LHCb RICH particle identification algorithm for the Cherenkov angle reconstruction to the experimental FPGA accelerated platform. We will compare the performance of this algorithm running on a Xeon CPU with the performance of the same algorithm, which is running on the Xeon-FPGA compute accelerator platform. This work is done in collaboration with Intel Corporation.

uSOP is a general purpose single-board computer designed for deep embedded applications in control and monitoring of detectors, sensors, and complex laboratory equipment. In this paper, we present and discuss the main aspects of the hardware and software designs and the expandable peripheral architecture built around serial busses. We show the tests done with state-of-the-art $\Delta \Sigma ~24$ -b ADC acquisition modules, in order to assess the achievable noise floor in a typical application. Eventually, we report on the deployment of uSOP in the monitoring system framework of the Belle2 experiment, presently under construction at the KEK Laboratory (Tsukuba, Japan).

Commercial microprocessors could be useful computational platforms in space systems, as long as the risk is bound. Many spacecraft are computationally constrained because all of the computation is done on a single radiation-hardened microprocessor. It is possible that a commercial microprocessor could be used for configuration, monitoring and background tasks that are not mission critical. Most commercial microprocessors are affected by radiation, including single-event effects (SEEs) that could be destructive to the component or corrupt the data. Part screening can help designers avoid components with destructive failure modes, and mitigation can suppress data corruption. We have been experimenting with a method for masking radiation-induced faults through the software executing on the microprocessor. While triple-modular redundancy (TMR) techniques are very effective at masking faults in software, the increased amount of execution time to complete the computation is not desirable. In this paper we present a technique for combining duplication with compare (DWC) with TMR that decreases observable errors by as much as 145 times with only a 2.35 time decrease in performance.

A MIPS 4Kc compliant embedded microprocessor design that incorporates architectural features for software controlled soft-error recovery is presented. The design leverages classical fault tolerance techniques, e.g., error detection and instruction restart, implemented at the micro-architectural level, and added instructions for error recovery. Soft-errors are detected as the instructions commit to architectural state. At this point, an exception is taken and software recovers the correct machine state and restarts execution. The software recovery allows full machine inspection to determine error root causes. Added instructions also facilitate silicon validation of the hardware and software recovery mechanisms. The design is implemented in a commercial low standby power 90-nm bulk CMOS process and the prototype operates at up to 336 MHz. Finally, proton broad beam irradiation results are presented. The processor demonstrates correct recovery, resuming program operation, from over 500 detected soft-errors, with no unrecoverable errors.

The Data Acquisition System (DAQ) and the Front-End electronics for an array of Kinetic Inductance Detectors (KIDs) are described. KIDs are superconductive detectors, in which electrons are organized in Cooper pairs. Any incident radiation could break a pair generating a couple of quasi-particles that increase the inductance of the detector. The DAQ system we developed is a hardware/software co-design, based on state machines and on a microprocessor embedded into an FPGA. A commercial DAC/ADC board is used to interface the FPGA to the array of KIDs. The DAQ system generates a Stimulus signal suitable for an array of up to 128 KIDs. Such signal is up-mixed with a 3 GHz carrier wave and it then excites the KIDs array. The read-out signal from the detector is down-mixed with respect to the 3 GHz sine wave and recovered Stimulus is read back by the ADC device. The microprocessor stores read out data via a PCI express bus (PCIe) into an external disk. It also computes the Fast Fourier Transform of the acquired read out signal: this allows extrapolating which KID interacted and the energy of the impinging radiation. Simulations and tests have been performed successfully and experimental results are presented.

In this paper, we focused on the GTX transceiver modules of Xilinx Kintex 7 field-programmable gate arrays (FPGAs), which provide high bandwidth, low jitter on the recovered clock, and an equalization system on the transmitter and the receiver. We present a frequency agile, auto-adaptive serial link. The link is able to take care of the reconfiguration of the GTX parameters in order to fully benefit from the available link bandwidth, by setting the highest line rate. It is designed around an FPGA-embedded microprocessor, which drives the programmable ports of the GTX in order to control the quality of the received data and to easily calculate the bit-error rate in each sampling point of the eye diagram. We present the self-adaptive link project, the description of the test system, and the main results.

Hybrid error-detection techniques combine software techniques with an external hardware module that monitors the execution of a microprocessor. The external hardware module typically observes the control flow at the input or at the output of the microprocessor and compares it with the expected one. This paper proposes a new hybrid technique that monitors the control flow at both points and compares them to detect possible errors. The proposed approach does not require any software modification to detect control-flow errors. Fault-injection campaigns have been performed on an LEON3 microprocessor. The results show full control-flow error detection with no performance degradation and small area overhead. A complete solution can be obtained by complementing the proposed approach with software fault-tolerance techniques for data errors. This work was supported in part by the Spanish Government under Contract TEC2010-22095-C03-03.

The paper describes the prototype of a synchronous (Master/Slave) data acquisition system for underground muon counters triggered by surface detectors. A water Cherenkov surface detector (Master) when hit by extensive air showers generates and transmits the trigger to the underground system (Slave) to register the muon fraction of the showers which survived the propagation through 3 m layer of soil. The surface and underground segments are built on the Altera field-programmable gate array (FPGA) CycloneIII/CycloneIV platforms, respectively. Both FPGAs are equipped with NIOS processors, which makes previously used external microcontrollers unnecessary. They also generate necessary interfaces: SDRAM controller, UART, SPI, DMA; interfaces which were previously implemented by means of logic elements. Moving several time-consuming tasks from the logic block (coded in the Altera Hardware Description Language) to the NIOS (coded in “C”) dramatically simplifies the system and increases its flexibility. The time margin for all processes managed by the soft-core NIOS for the 100 Hz T1 trigger rate remains sufficient. NIOS processors communicate with each other via UART protocol and by the RS485 standard. The underground CycloneIV FPGA is programmed remotely via additional MAXII CPLD with nonvolatile programmable memory. Tests have shown that a full string of data processing goes smoothly. The above-mentioned string involves the following processes: the transfer of the trigger with a time stamp from the surface detector into the underground segment via a dedicated line with a galvanic barrier, freezing data from 64 channels at 320 MHz sampling in internal DPRAMs, writing/reading data into/from external SDRAM, extracting physical data identified by GPS time stamps sent from Central Data Acquisition System (CDAS) and the data transfer from the underground NIOS via the surface NIOS to CDAS.

This paper presents HETA, a hybrid technique based on assertions and a non-intrusive enhanced watchdog module to detect SEE faults in microprocessors. These types of faults have a major influence in the microprocessor's control flow, causing incorrect jumps in the program's execution flow. In order to protect the system, a non-intrusive hardware module is implemented in order to monitor the data exchanged between the microprocessor and its memory. Since the hardware itself is not capable of detecting all control flow errors, it is enhanced to support a new software-based technique. Also, previous techniques are used to reach higher detection rates. A fault injection campaign is performed using a MIPS microprocessor. Simulation results show high detection rates with a small amount of performance degradation and area overhead.

A microprocessor with an architectural redundancy to achieve high dependability is designed and manufactured to explore the effectiveness of tolerating soft errors without circuit hardening. The processor architecture is based on a modularized pipeline which contains several functionalities to facilitate a real-time error detection and a fast roll-back recovery. As a further extension for a possible increase of hard errors in the future technology, an energy-effective coverage of hard errors by dynamically adapting the redundancy between a dual and a triple module is also included in the processor. A radiation stress test result indicates that the designed redundant but unhardened processor can successfully achieve the same dependability as a hardened processor. Our synthesis and layout results show that radiation hardened circuits increase processor hardware area by 71% and power by 28%, respectively. It is thus possible to use the architectural redundancy instead of circuit hardening to achieve a cost-effective reliability, as suggested by these factors.

This work analyzes the behavior of a designed embedded system composed of microprocessor, memories and SpaceWire (SpW) links under Total Ionizing Dose (TID) synthesized into a commercial flash-based FPGA from Actel. Two tests were performed: one the FPGA is configured just once at the beginning of the irradiation and the other the FPGA is reconfigured every 5 krad (Si). Results evaluate power supply current (Icc), temperature, function operation and performance degradation.

A dual mode redundant (DMR) logic data path with instruction restart that detects errors at register file (RF) write-back is presented. The DMR RF allows SEU correction using parity to detect RF entry nibbles that are correct in one copy but not the other. Detection and backing out incorrect write data are also described. The radiation hardened by design (RHBD) circuits are implemented in 90 nm CMOS. The DMR microarchitecture is described, including pipelining, error handling, and the associated hardware. Heavy ion and proton testing validate the approach. Experimentally measured cross sections and examples of errors due to pipeline SET or RF SEU are shown. Critical node spacing and the mitigation of multiple node collection are also described.

We describe the approach used to calculate and verify on-orbit upset rates of radiation hardened microprocessors. System designers use these error rates to choose between microprocessors and add appropriate system-level recovery and redundancy.

This paper presents a hybrid technique based on software signatures and a hardware module with watchdog and decoder characteristics to detect SEU and SET faults in microprocessors. These types of faults have a major influence in the microprocessor's control-flow, affecting the basic blocks and the transitions between them. In order to protect the transitions between basic blocks a light hardware module is implemented in order to spoof the data exchanged between the microprocessor and its memory. Since the hardware alone is not capable of detecting errors inside the basic blocks, it is enhanced to support the new technique and then provide full control-flow protection. A fault injection campaign is performed using a MIPS microprocessor. Simulation results show high detection rates with a small amount of performance degradation and area overhead.

In this work we propose a method to evaluate the criticality of the components of a circuit with respect to Single Event Transient (SET) effects. Emulation-based fault injection is used to determine the error rate for each individual gate. The method also identifies the optimal set of flip-flops to be hardened using time redundancy techniques. The results enable the selective application of SET mitigation techniques to satisfy soft error rate requirements with reduced overheads. A PIC18 microprocessor with three different workloads has been used as a case study, and results show that just hardening 25% of gates is enough to achieve more than 99% mitigation of SET effects.

In order to increase the robustness of a circuit against SEUs, fault injection is commonly used to locate weak areas. autonomous emulation is a very powerful tool to locate these areas by executing huge fault injection campaigns. In this work, fault injection has been extensively applied to a PIC18 microprocessor, while executing three different workloads. A 80 million fault campaign has been performed, and results show that a failure rate lower than 1% can be obtained by hardening a 24% of the circuit flip-flops, for the given applications.

Single-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. The cross section of the 90 nm SOI processors is smaller than results for 130 and 180 nm counterparts, but the threshold is about the same. The scaling of the cross section with reduction of feature size and core voltage for SOI microprocessors is discussed

Single-event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes and core voltages. Multiple-bit upsets in registers and D-cache were measured and compared with single-bit upsets. Also, the scaling of the cross section with reduction of feature size for SOI microprocessors is discussed.

The LHCb readout unit (RU) is a custom entry stage to the readout network of a data-acquisition or trigger system. It performs subevent building from multiple link inputs toward a readout network via a PCI network interface or alternatively toward a high-speed link, via an S-link interface. Incoming event fragments are derandomized, buffered and assembled into single subevents. This process is based on a low-overhead framing convention and matching of equal event numbers. Programmable logic is used both in the input and output stages of the RU module, which may be configured either as a data-link multiplexer or as entry stage to a readout or trigger network. All FPGAs are interconnected via the PCI bus, which is hosted by a networked microprocessor card. Its main tasks are remote FPGA configuration and initialization of the PCI cards. The RU hardware architecture has been optimized for a throughput of up to 200 MB/s at a 1 MHz trigger rate, as required by the most demanding application, the LHCb level-1 trigger network. A custom traffic-scheduling link is available for applications like pipelined destination address allocation.

Proton and heavy ion upset susceptibility has been measured individually for six types of storage elements in an advanced commercial processor, the PowerPC750, from two manufacturers: Motorola and IBM. Data on interfering program malfunctions was also collected. Compared to earlier PPC603e results, the upset susceptibility has decreased somewhat.

This paper deals with a software modification strategy allowing on-line detection of transient errors. Being based on a set of rules for introducing redundancy in the high-level code, the method can be completely automated, and is therefore particularly suited for low-cost safety-critical microprocessor-based applications. Experimental results are presented and discussed, demonstrating the effectiveness of the approach in terms of fault detection capabilities.

This paper describes a new data acquisition system for the focal plane polarimeter of the Grand Raiden spectrometer at the Research Center for Nuclear Physics (RCNP) in Osaka, Japan. Data are acquired by a Creative Electronic Systems (CES) Starburst, which is a CAMAC auxiliary crate controller equipped with a Digital Equipment Corporation (DEC) J11 microprocessor. The data on the Starburst are transferred to a VME single-board computer. A VME reflective memory module broadcasts the data to other systems through a fiber-optic link. A data transfer rate of 2.0 Mbytes/s between VME modules has been achieved by reflective memories. This rate includes the overhead of buffer management. The overall transfer rate, however, is limited by the performance of the Starburst to about 160 Kbytes/s at maximum. In order to further improve the system performance, we developed a new readout module called the Rapid Data Transfer Module (RDTM). RDTM's transfer data from LeCroy PCOS III's or 4298's, and FERA/FERET's directly to CES 8170 High Speed Memories (HSM) in VME crates, the data transfer rate of the RDTM from PCOS III's to the HSM is about 4 Mbytes/s.

We present single event effect test results for the Intel 80386 microprocessor, the 80387 coprocessor, the 82380 peripheral device, and on the 80486 microprocessor. Both single event upset and latchup conditions were monitored.

In this paper, we investigate the impact of register file errors in modern embedded microprocessors reliability through fault-injection and heavy-ion experiments. Additionally, we evaluate how different levels of compiler optimization modify the usage and failure probability of a processor register file. We select six representative benchmarks, each one compiled with three different levels of compiler optimization. We performed exhaustive fault-injection campaigns to measure the register’s architectural vulnerability factor of each code and configuration, identifying the registers that are more likely to generate silent data corruption or single event functional interruption. Moreover, we correlate the observed reliability variations with register file utilization. Finally, we irradiated with heavy ions two of the selected benchmarks compiled with two levels of optimization, and correlated experimental results with fault-injection analysis.

SEE spaceflight measurements are presented on HM65756 SRAM from Matra-MHS, Seeq 28C256 and Motorola MC68020 microprocessor (bulk version) in the MIR station orbit (350 km altitude, 51.6/spl deg/ inclination). Accelerator testing (heavy ion and proton) of flight spares permits the prediction of the event rates using standard model such as CREME and SPACERAD/sup 1/ as well as characterisations of the flight components allowing the comparison of in-orbit observations. Event rate prediction and ground-testing data are compared. >

The authors discuss methods for reducing the computation time for 3-D PET (positron emission tomography) reconstruction through the use of fast computer hardware, vector and parallel programming techniques, and algorithm optimization. The strengths and weaknesses of i860 microprocessor based workstation accelerator boards are investigated in implementations of 3-D PET reconstruction. One key issue in achieving speed on the SuperCard 2 has been minimizing memory accesses, and eliminating redundant calculations through approximations and look-up tables. This has allowed the calculation time to decrease from 20 minutes on the MicroVax 3200 to 146 seconds on a dual i860 system. >

For nuclear physics experiments at the Julich Cooler Synchrotron COSY, a data acquisition system is under development. With this background, and in order to enhance existing CAMAC systems, an intelligent CAMAC crate controller with CC-A2 functionality was developed. The main enhancement is the replacement of the Branch Highway with a new standard of intercrate connection: the VICbus. The other highlights are the optional use of Motorola 68030 microprocessor as CAMAC list-processor and optimization of CAMAC block transfers, optional Ethernet or Cheapernet connection. >

The authors present the results of a radiation evaluation program carried out on the ADSP2100A, which is a single-chip microprocessor optimized for 12.5 MIPS digital signal processing. Single event upset/latch-up (SEU/SEL) testing using Californium-252 was the primary aim of this program; however, accelerator heavy-ion and proton SEU/SEL data as well as total ionizing dose data are also presented. Californium-252 SEU testing covered both 12. 5- mu m and 21.3- mu m epitaxial layer DSPs, whereas only the 12.5- mu m type was tested with heavy ions and protons. Heavy-ion SEU testing covered the LET (linear energy transfer) range of 3.4 to 79.2 MeV/(mg/cm/sup 2/) and SEU testing covered the proton energies of 200, 500 and 800 MeV. A total ionizing dose rate of 64.0 rd(Si)/min was used for the cobalt-60 testing. The hardware design and software used are described and details of the various tests and test facilities are given. The authors report on the use of the SEU data for the calculation of expected in-orbit upset rates using the CREME suite of programs. >

Proton single event upset (SEU) cross sections and proton total dose hardness of commercially available MIPS R3000 microprocessors (CPU) and R3010 floating point units (FPU) were obtained by exposing these parts to 256 MeV protons from the linear accelerator (LINAC) at the Los Alamos Meson Physics Facility (LAMPF). Parts from several manufacturers were tested. The CPUs and FPUs were tested dynamically during radiation exposure with specially designed assembly language codes which exercised a subset of the available instructions. Cross sections derived from the SEU data were used to calculate expected upset rates for a 500-km, 60-degree inclination orbit during quiet solar conditions and during the August 4. 1972, King solar fire event modeled by J.H. Adams et al. (1981). >