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This paper describes a flow control of the dye in the paper mill with the quasi-Z-source indirect matrix converter (QZSIMC) fed induction motor drive. More than a decade the voltage-source inverter (VSI) and current-source inverter (CSI) have been used to control the speed of the induction motor, which in turns controls the flow of dye. Recently, the matrix converter (MC) has been an excellent competitor for the VSI or CSI for its compactness. The voltage transfer ratio of the VSI, CSI, and MC has been limited to 0.866. Thus, the efficiency of these converters is less. To improve the voltage transfer ratio the quasi-Z-source network (QZSN) is to be used between voltage source and indirect MC (IMC). The modification in the shoot-through duty ratio of the QZSN varies the voltage transfer ratio greater than 0.866. Different voltage transfer ratios are needed for different voltage sag conditions. For a variation of the duty ratio of the QZSN, the fuzzy logic controller has been presented. To control the IMC vector control with space vector modulation has been presented. This paper proposes the implementation of QZSIMC adjustable speed drive for the flow control of dye in paper mill during different voltage sag conditions. A 4-kW prototype has been built and the effectiveness of the proposed system is verified with simulation results and experimental setup. Simulation is done in MATLAB, Simulink platform. Experimental setup is done with the aid of a TMS320F2812 (Texas Instrument) processor. The experimental results validate the maintenance of the speed of an induction motor at the set condition, thus controlling the perfect flow of dye in paper manufacturing technology. [ABSTRACT FROM AUTHOR]

This paper investigates the operation of the back-to-back neutral point clamped (BTBNPC) converters when the ac voltages on both ends are asynchronous. The zero-sequence injection (ZSI) technique has been used to extend the linear modulation range of the pulsewidth modulation operation. This paper investigates the ZSI of the BTBNPC to maximize the dc-bus voltage utilization while the ac voltages of both ends have different magnitudes and phases. This study further explores the reactive current injection to reduce the risk of overmodulation when grid voltages surge. The combination of these techniques can extend the operation range of the BTBNPC over varying ac voltages of both ends with the available dc-bus voltage. In addition, the issue of the neutral-point balance is also taken into consideration. Laboratory test results are provided to verify the proposed technique. [ABSTRACT FROM AUTHOR]

Four-level hybrid-clamped inverter is a newly proposed topology that can operate under a wide voltage range without switches connected in series. However, when it is applied in medium voltage high power conversions, the flying capacitors in each phase will occupy a huge volume and a high switching frequency is required to restrain the voltage ripples. In order to overcome this drawback, a four-level active neutral-point clamped inverter is discussed in this paper, which consists of only six switches and no diodes or flying capacitors are required. In order to balance the neutral-point voltages under the full power factor and modulation index range, a capacitor voltage balance method based on carrier-overlapped pulsewidth modulation is proposed in this paper. The upper and lower dc-link capacitor voltages are balanced by zero-sequence voltage injection and the central dc-link capacitor voltage is balanced by adjusting the duty cycles of switching signals slightly. Simulation and experimental results are presented to confirm the validity of this method. [ABSTRACT FROM AUTHOR]

A new single stage three-phase ac–dc converter with four switches and galvanic isolation is proposed in this paper. The new converter is simple and uses fewer switches than previously proposed ac–dc converters of the same type. It is a bridgeless converter that can operate with continuous input current and with any pulsewidth modulated method suitable for a standard three-phase six-switch voltage source rectifier. In this paper, the operation, control, analysis, and design of the proposed converter are explained and its features are discussed. Experimental results obtained from a prototype that confirm the feasibility of the converter are presented as well. [ABSTRACT FROM AUTHOR]

With the increasing of switching frequency in pulsewidth modulated motor system, common mode current (CMC) seriously affects the reliable operation of motor system and it has become a problem that cannot be ignored. This paper proposes a mathematical model of CMC and conducts detailed time–frequency characteristics analysis of CMC. The influence of several key parameters of motor system, such as distributed capacitance, dc bus voltage, and inverter switching frequency, on CMC characteristics has been analyzed in detail, and the corresponding variation rule of CMC oscillation amplitude and attenuation period/time has been summarized. The experimental results are presented to verify the correctness of theoretical analysis. The conclusions of this paper can lay theoretical foundation for the effective suppression of CMC in various practical applications. [ABSTRACT FROM AUTHOR]

In an open-end winding permanent magnet synchronous machines drive with single dc voltage source, zero-sequence current (ZSC) can lead to a high current stress of power modules and loss of motor. Therefore, some modulation strategies have been employed to alleviate ZSC by suppressing zero-sequence voltage (ZSV). However, ZSC still exists in the system because ZSV can also be generated by other nonlinear factors of inverter such as the dead time of system. In addition, zero-sequence back electromotive force in the zero-sequence path can also enlarge torque ripple and ZSC. In order to deal with above problems, first, this paper proposes a full-order adaptive zero-sequence observer to estimate future ZSC and ZSV, which are able to compensate one-step control delay. Second, to achieve the maximum voltage dc bus utilization, this paper proposes a novel deadbeat predictive current control (DPCC) scheme with alternate sub-hexagonal center pulsewidth modulation strategy to suppress ZSC and torque ripple simultaneously. Finally, this paper presents a comparative study of two types of methods, namely traditional DPCC scheme and the proposed DPCC scheme. Simulation and experimental results are demonstrated to verify the effectiveness of the proposed DPCC scheme. [ABSTRACT FROM AUTHOR]

The dual-active bridge (DAB) topology is commonly preferred in bidirectional applications due to several attractive features, including auto-adjust of power flow, galvanic insulation, wide voltage gain, and zero voltage switching (ZVS) capability over some power ranges. However, the efficiency of the converter drops at light loads because the ZVS range is directly dependent on the circulating current. Assuming that the processed power is variable, the DAB converter's design must find a compromise between extending ZVS ranges and reducing the reactive power processing to ensure higher efficiency. Aiming this compromise, many papers propose hybrid approaches in which the modulation strategy is selected according to the processed power. However, this is not a simple solution because it demands multivariable control and offline optimizations. This paper proposes a modulation strategy to ensure ZVS and reduce the circulating current for the DAB converters. While the usual phase-shift modulation provides ZVS operation in a range of 40% to 100% of rated power, the proposed asymmetrical pulse-width modulation can obtain ZVS operation in a range of 2% to 100% of rated power. Experimental results demonstrated that the proposed strategy improves the converter efficiency for all power ranges, especially at light loads. [ABSTRACT FROM AUTHOR]

This paper proposes a two-degree-of-freedom (2DoF) interleaving scheme based on phase-disposition (PD) PWM for minimizing the high-frequency zero-sequence circulating current (ZSCC) in modular interleaved three-level converters. The method incorporates an internal interleaving by phase-shifting the carriers in each individual converter, and an external interleaving by phase-shifting the carriers of the different converters. A general harmonic distribution analysis which is valid for all types of voltage source converters is carried out to simplify the evaluation of the proposed method. A comprehensive evaluation of the proposed method shows that the PD-2DoF interleaving scheme produces the lowest ZSCC maximum value as compared to existing approaches. Moreover, it can achieve comparable performances as existing methods do in terms of output quality and common mode voltage magnitude, showing a great potential for practical implementation. Simulation and experimental results are obtained to demonstrate the performance of the proposed method. Generalization of the 2DoF interleaving scheme to high-level converter is also discussed in this paper. [ABSTRACT FROM AUTHOR]

This paper investigates a Vienna rectifier as a charger for series-connected battery packs. Focusing on carrier-based pulsewidth modulation (CBPWM), the ripple current flowing through the neutral point (NP) results in the voltage oscillation if the loads are resistive. To reduce the ripple of average NP current with mitigated distortion under balanced and unbalanced dc-link voltages conditions, a novel CBPWM with segmented component injection scheme (SCIS) is proposed in this paper. After dc component injection, continuous intervals for optimized component injection and clamping intervals for compensation component injection are identified. Optimized components are calculated originally based on unbalanced factor to make the average NP current zero-size in one switching period. Moreover, unique compensation components generate suitable NP current to shape the sinusoidal input currents according to the circuit analysis. In consequence, the SCIS not only keeps the input current with low-harmonic distortion, but also minimizes the oscillation of dc-link voltage under balanced and unbalanced conditions. In addition, the value of the NP current during the clamping intervals is analyzed under various operating conditions. The effectiveness and the performance of the proposed SCIS are verified by simulation and experiments. [ABSTRACT FROM AUTHOR]

The modular multilevel converter (MMC) with nearest level modulation (NLM) is widely used in the high voltage applications for low switching frequency and easy implementation. Existing literature has not provided a complete submodule (SM) fault ride-through scheme for MMC with NLM. In this paper, a strategy including fault detection, localization, redundancy, and recovery is proposed to ensure continuous operation of MMC under IGBT open-circuit faults conditions. It only requires a few hardware and software resources. The features of MMC and SMs with three types of failures are studied, respectively. Based on these, the fault detection method is proposed by using a simple hardware circuit, thus high computation complexity is avoided. Since current fault localization schemes are limited to MMC with carrier phase shifted pulse width modulation, this paper further proposes a strategy for MMC with NLM to locate the faulty SM and identify the fault type. After this, the fault redundancy and the proposed fault recovery method are applied to eliminate the fault and then exit the failure state. Therefore, the ability of SM fault ride-through can be realized. Analysis of failure characteristics are verified in simulation. Experimental results based on a single-phase MMC prototype with 11 SMs per arm are presented to demonstrate the validity of the proposed fault ride-through strategy. [ABSTRACT FROM AUTHOR]

A modular multilevel converter (MMC) is regarded as a promising topology in high-voltage direct current systems. However, the MMC consists of numerous submodules (SMs) and switching devices, which lead to a considerable switching loss, and increased cost and size of the heat sink. To mitigate these issues, this paper presents a novel modulation method composed of fundamental frequency modulation (FFM) and multicarrier-based sinusoidal pulsewidth modulation schemes. The main purpose of this modulation method is the reduction of switching loss while maintaining good harmonic performance. However, the FFM scheme leads to the unbalanced capacitor voltage of each SM in the MMC. Accordingly, this paper additionally proposes the rotation method and selective voltage balancing control for SMs to ensure effective performance of the method. Simulation and experimental results verify the effectiveness and performance of the proposed modulation scheme through switching loss and spectral analyses. [ABSTRACT FROM AUTHOR]

This paper presents a new six-level flying capacitor based (FC-based) multilevel converter with one dc source and the capability of operating in all power factors and modulation indexes. Multilevel converters with one dc voltage source are attractive in many applications as they do not need rather expensive and bulky multiwinding input transformer connection at the dc side. On the other hand, not all classic multilevel converters with one dc source can produce any desirable number of output voltage levels at all power factors and/or modulation indexes. In this paper, a hybrid structure is proposed in which six voltage levels can be realized at the ac terminals. The modulation technique and the control strategy for the FC voltage balancing are presented. To show the advantages of the proposed converter, different performance criteria, such as switch count and rating, the size of capacitors, switching frequency, and power losses, are compared with other existing six-level topologies. The results indicate that the proposed structure is superior to other six-level converters from different standpoints. Simulation results are used to further evaluate the performance of the proposed converter. A laboratory-type experimental setup is used to validate the theoretical results. [ABSTRACT FROM AUTHOR]

A recent paper by Hoffmann et al. presents a discrete-time model in a rotating $dq$ reference frame of an R-L filter and its current control. The purpose of this note is, first, to show that the discrete model presented in the paper behaves differently to the sampled continuous-time model of the plant, formulated in the stationary $\alpha \beta$ reference frame; second, to find the proper discretization of the plant in $dq$ coordinates; and third, to verify that there is cross coupling between axes $d$ and $q$ in the closed-loop system if the original model is used, and that this coupling is not present when using the model found in this note. In the note, it is verified that having a precise model of the plant allows us to fulfill the control objective of obtaining the complete decoupling between axes. [ABSTRACT FROM AUTHOR]

Multilevel inverters have created a new wave of interest in industry and research. While the classical topologies have proved to be a viable alternative in a wide range of high-power medium-voltage applications, there has been an active interest in the evolution of newer topologies. Reduction in overall part count as compared to the classical topologies has been an important objective in the recently introduced topologies. In this paper, some of the recently proposed multilevel inverter topologies with reduced power switch count are reviewed and analyzed. The paper will serve as an introduction and an update to these topologies, both in terms of the qualitative and quantitative parameters. Also, it takes into account the challenges which arise when an attempt is made to reduce the device count. Based on a detailed comparison of these topologies as presented in this paper, appropriate multilevel solution can be arrived at for a given application. [ABSTRACT FROM AUTHOR]

The output voltage of power electronic converters is a very important quantity for dynamic control of power electronic systems. In electrical drives without electromechanical position or speed sensor, the terminal reference voltage is used to obtain the rotor position. Dead-time effects and semiconductor voltage drop lead to distortion in the actual output voltage and degrade the control performance when the back electromotive force magnitude is low. Thus, for stable low-speed operation, output voltage sensing becomes necessary. Due to the switching nature of power electronic systems, this is not a trivial task, especially when instantaneous measurement of the terminal voltage is required. In this paper, an instantaneous switching-period average voltage sensing technique is proposed that utilizes a combined approach of oversampling and filtering. Based on the theoretical analysis of the sampling- and filter-induced measurement distortion, a general solution for an optimal filter design is derived. The additional sensing circuit is integrated into the low-side gate driver of the converter outputs. This paper includes details about the hardware implementation and extensive verification measurements. [ABSTRACT FROM AUTHOR]

This paper presents the study of an offline flyback-based light-emitting diode (LED) driver with reduced storage capacitance. An approach called active ripple compensation was used for minimizing the converter bulk capacitance. This technique is oriented to voltage-controlled pulse width modulation converters and is based on the modulation of the duty cycle, which allows for the reduction of the filtering capacitance by increasing the harmonic content of the input current up to the limits established by the standards. By means of the design procedure presented in this paper, the amount of capacitance reduction and input current distortion can be fully controlled and theoretically predicted. In addition, no extra sensors are required to implement the proposed technique, apart from the LED current sensor already available in most LED drivers. Experimental results from a 50-W laboratory prototype supplied from a 220-V 60-Hz grid were carried out. The results were compared with the conventional approach, attesting the superior performance of the proposed methodology. [ABSTRACT FROM AUTHOR]

A new modulated carrier control (MCC) method is proposed in this paper for a power factor correction (PFC) boost converter, which provides high power factor (PF) and low total harmonic distortion (THD) in wide input voltage and load range. The proposed MCC method employs a zero current duration (ZCD) demodulator that detects ZCD in each switching cycle to estimate current conduction duration of the boost inductor. Using the estimated signal of the ZCD demodulator, the proposed controller generates a compensated duty signal with a PFC converter to properly operate in continuous conduction mode (CCM) or discontinuous conduction mode (DCM). Unlike the conventional MCC PFC converter where the line current is distorted in DCM resulting in poor PF and high THD, the proposed MCC method can provide higher PFC performance regardless of CCM and DCM while maintaining the simple control loop of conventional MCC control method that does not require inner current loop and using relatively small inductance. In this paper, the operational principle of the proposed method has been discussed. To verify the proposed method, it has been tested on a 400-W PFC boost converter. [ABSTRACT FROM AUTHOR]

Common-mode voltage output is closely associated with switching states in three-phase three-wire neutral point clamped converter. Detailed analysis shows avoiding redundant states can effectively improve the common-mode voltage, so this paper proposes a pulse width modulation (PWM) technique with zero redundant state to reduce the common-mode voltage output, and evaluates their performance with the conventional PWM schemes. This paper also takes the compensation of neutral point potential deviation into consideration. Laboratory test results are presented to verify the effectiveness of the proposed scheme. [ABSTRACT FROM PUBLISHER]

This paper proposes an active switching harmonic current reduction method within the dc-link capacitor of two-level, three-phase, back-to-back converters. This method is based on the derived analytical solution for switching harmonic currents in the dc-link. It is shown that by controlling the pulse width modulation carrier waveform's phase angles, the harmonics in the second carrier band of the rectifier and the inverter can be synchronized such that cancellation occurs in the dc-link capacitor. This synchronization is provided by harmonic phase feedback control. The feasibility of the proposed approach has been verified experimentally and results are presented in this paper. [ABSTRACT FROM PUBLISHER]

The modeling and control of a buck–boost and stacked dual half-bridge (DHB) integrated bidirectional dc–dc converter have been studied in this paper. This converter features high-voltage transfer ratio, high efficiency, and the minimum number of switches. In this paper, an extended, continuous, full-order, state-space averaging modeling method is proposed. Compared with existing methods, the proposed method exhibits higher coincidence with the switching circuit simulation, in steady and especially dynamic states. Due to its high dynamic accuracy and low complexity, the proposed modeling method provides a better theoretical analysis and a fast simulation tool for transient process and control design of converters with dual-active-bridge units, especially with DHB units. By using this method, the high-frequency transformer series inductance current is directly divided into a sampled dc component and a fluctuant component. Only the sampled dc one is included into state variables, but both components are considered into state equations. Besides, this method regards the entire converter as a linear superposition of its subsections, which provides a stepwise modeling based on linearization of subsections. Moreover, a decoupled proportional-integral control method is proposed to enhance the stability and dynamic response of the converter. This control method is analyzed by the proposed models, which can be regarded as an application of the proposed modeling method. Simulation and experiments have validated both the proposed modeling and the decoupled control strategy. [ABSTRACT FROM PUBLISHER]

This paper presents a new feed-forward strategy for suppressing low-order harmonic circulating currents in pulsewidth-modulated (PWM) based modular multilevel converters (MMCs). The approach is based on the new average model approach established in this paper, which identifies cross-coupling interactions between the system-level and submodule elements using decomposed dependent sources. As well as improving the damping of the system, the major advantage of this approach is that it maintains the natural DC bus balance property of a PWM modulated MMC by considering the upper and lower arms together (unlike existing feed-forward schemes which treat each MMC arm independently). Moreover, unlike existing direct control resonant strategies, which require careful gain tuning and are highly dependent on the ac system frequency, the proposed approach achieves wideband circulating current ripple suppression without requiring knowledge of the circulating current harmonic frequencies and needs only a simple proportional–integral (PI) controller to regulate the circulating current dc component for power balance. This makes it particularly suitable for use in multifrequency or variable-frequency ac systems. Extensive simulation and matching experimental results, including steady-state and transient responses compared against existing circulating current suppression approaches, validate the effectiveness and benefits of this new feed-forward compensation technique. [ABSTRACT FROM PUBLISHER]

This paper presents a hybrid seven-level converter based on T-type converter and H-bridge cascaded suitable for low-voltage and high-power-density applications. The operation principles and conduction paths are analyzed comprehensively. Voltage balance control of the floating capacitors is the key point of this paper. Mathematical expressions of capacitor voltage balance conditions are deduced based on sinusoidal pulse width modulation (SPWM). The results show that floating capacitor voltages are only balanced when the modulation index is below 0.82 under SPWM. In order to enlarge the modulation index ensuring the capacitor voltage balance, space vector modulation (SVM) is also applied to regulate floating capacitor voltages taking advantage of redundant switching vectors. Meanwhile, in SVM, there are no additional control requirements for the capacitor voltage. Taken both SPWM and SVM into consideration, the limit to the range of operation for this seven-level converter is presented, which is a function of the modulation index and the power factor. The merit of dc voltage utilization improvement in this topology is also analyzed based on simulation results. Simulations and experimental results under different modulation index and RL load are presented to verify the modulation strategies illustrated in this paper. [ABSTRACT FROM PUBLISHER]

Two carrier-based unipolar-sinusoidal pulse width modulation (SPWM)-oriented modulation techniques for an isolated bidirectional dc–ac converter are proposed, compared, and validated in this paper. The dc–ac converter is composed of a full-bridge (FB) inverter cascaded with a cycloconverter through a high-frequency transformer. Both modulation techniques proposed in this paper can realize zero-voltage switching (ZVS) for the FB inverter and zero-current switching or ZVS for the cycloconverter in all load range, and are able to suppress the voltage spikes introduced by the transformer leakage inductance as well. In order to increase the converter efficiency and power density, we propose to utilize SiC MOSFETs for the converter. The first modulation technique enables the utilization of Si-SiC hybrid switches with no synchronous rectification (SR), for the purpose of lowering the converter cost. The second modulation technique requires all switches to be SiC MOSFETs, but with SR, which increases the converter efficiency. A 400-V dc to 240-V ac 1.2-kW prototype has been developed to validate the effectiveness and performance of the proposed carrier-based unipolar-SPWM-oriented modulation techniques. [ABSTRACT FROM PUBLISHER]

Wide bandgap semiconductor switches have been increasingly utilized to improve the power density and efficiency of power converters, as such devices are able to operate at very high frequencies, e.g., up to 100 MHz, with reduced power losses. However, such a high-frequency operation may impose a challenge to the digital control system, and the system clock frequency should be up to 100 GHz in high-precision applications, which is difficult to realize in low-cost microprocessors. Instead of using extremely high-frequency clocks, preprocessing-based solutions that utilize digital pulse-width-modulated (DPWM) dither techniques can also enhance the DPWM resolution with moderate frequency clocks. Unfortunately, this is usually achieved at the expense of introducing low-frequency harmonics, which may complicate system controller and output filter design. In this paper, an optimal dither technique is proposed to enhance the resolution of DPWM power converters. The concepts of positive dither and negative dither are first proposed in this paper. Furthermore, vector-diagram-based analysis indicates that with proper utilization of positive dithers and negative dithers and carefully selected dither sequences, the lowest order harmonic introduced by the conventional dither technique can be completely eliminated when the dither period is multiples of six switching periods. In other cases, the proposed optimal dither technique can produce minimized lowest order harmonic. Finally, experimental results obtained from a Gallium Nitride (GaN) devices-based synchronous buck converter validate the feasibility of the proposed dither technique. [ABSTRACT FROM PUBLISHER]

This paper presents a fast and generalized space vector pulse width modulation (SVPWM) scheme for any multilevel inverter. The SVPWM scheme generates all the available switching states and switching sequences based on two simple and general mappings, and calculates the duty cycles simply as if for a two-level SVPWM, thus independent of the level number of the inverter. Because the switching states, duty cycles, and switching sequences are all obtained by simple calculation in the proposed SVPWM scheme, no lookup table is needed and the scheme is computationally fast. The generalized method of generating the switching states (first mapping), calculating the duty cycles, and determining the switching sequence (second mapping) is described in this paper. The scheme is suitable for any reference vector with any modulation index, and can be conveniently extended to meet specific requirements, such as symmetric switching sequences. Compared with prior methods, the SVPWM scheme proposed in this paper provides two more degrees of freedom, i.e., the adjustable switching sequences and duty cycles, thus offering significant flexibility for optimizing the performance of multilevel inverters. The influence of redundant switching sequences in the output phase voltage of inverters is demonstrated for a nine-level inverter. This paper also thoroughly compares the proposed SVPWM scheme with prior methods. Both simulation and experimental results are given. [ABSTRACT FROM AUTHOR]

This paper presents a new single-phase ac–dc–ac three-level three-leg converter composed of three coupled-inductors and six active switches. The system model, operation principles, and a control strategy are presented and discussed. Additionally, a space-vector pulsewidth modulation technique is developed to double the effective frequency of the grid and load voltages and to reduce the switching losses. The proposed converter is compared to other similar converters in terms of switch count, harmonic distortion, and power losses. The results show that the proposed topology has improved power quality and uses fewer switches and gate drive circuits. These characteristics can potentially reduce the costs and the complexity of the system. In addition, the proposed converter eliminates the requirement for dead time to prevent short circuit of the dc-link. In order to validate the theoretical analysis, simulated and experimental results are presented and discussed. [ABSTRACT FROM AUTHOR]

Battery energy storage system based on the modular multilevel converter (MMC-BESS) is able to realize the decentralized management of battery packs, which is suitable for the retired battery utilization to improve the efficiency of battery recycling. With multiple submodules (SM), the corresponding SM fault ride-through method is mandatory to improve operational reliability. This paper proposes a redistributed pulsewidth modulation method for MMC-BESS to ride-through the SM fault through employing the simple logic operation, which could avoid the unexpected carrier shift under various modulation indexes induced by the SM fault or grid voltage rise. MATLAB simulations and experimental results are presented to verify the performance of the proposed method. [ABSTRACT FROM AUTHOR]

DC-to-DC power supplies are critical components for processors in high performance computing and datacenter servers. Conversion from an intermediate bus voltage (e.g., 12 or 48 V) to the core voltage (∼0.9 V) of processors must be efficient, compact, and cost effective. This paper proposes two versions of active-clamp forward converter (ACFC) power blocks to supply core voltage from either 12 or 48 V intermediate bus voltage. The ACFC power block can be individually tested prior to assembly and vertically soldered onto the motherboard to fit in a standard 1U server. A low loss, compact planar transformer is designed into the ACFC power block printed circuit board (PCB). A custom, standing slab inductor not only provides high inductance and high saturation current but also helps to mechanically support the power block. A one-piece copper winding connects the transformer to the inductor, thereby reducing the dc loss in the current path. Thorough analysis is performed to model the conversion loss of the proposed power block. Experimental results show a peak efficiency of 90.4% (12 V input) and 89.5% (48 V input) with 0.9-V output. [ABSTRACT FROM AUTHOR]

Three-phase current reconstruction techniques with a single current sensor have been studied for permanent magnet synchronous machines (PMSMs) drive system due to its reducing cost and volume. In order to minimize the current reconstruction dead zone in the conventional method with a single dc-link current sensor, a strategy to couple multiple available positions through the single current sensor is proposed in this paper. With the proposed method, two independent equations of the stator currents can be obtained by sampling the single current sensor twice in both zero voltage vectors and active voltage vectors. By solving these two equations, the phase current reconstruction can be achieved accurately, which moves the current reconstruction dead zone toward six corner area of the space vector hexagon. Meanwhile, in order to guarantee the proposed method suitable in the whole linear modulation region, the suitable selection of the pulsewidth modulation switching period is analyzed in detail. Furthermore, the optimal selections of multiple sampling positions are discussed to lower the actual implementation difficulty of the proposed method. Finally, the experimental results on the PMSM demonstrate that the reconstructed phase currents with the proposed method can be always in consistent with the actual measured currents under different working conditions. [ABSTRACT FROM AUTHOR]

As research in matrix converters (MCs) has progressed over time, space vector modulation has emerged as the most popular technique for their modulation. Lately, model predictive control (MPC) has also been explored for the modulation and control of MCs, primarily gaining popularity due to the ease in realization of multiple objectives, as desired in MCs. However, multi-objective MPC employs assignment of weights to each control objective, wherein weight tuning is either empirical in nature or computationally cumbersome. This paper proposes a new modulation technique for MCs, inspired from delta sigma modulation for voltage source converters, that can be used for load voltage and source current control of MCs. Since source currents are samples of the load current envelope, it is required that this envelope be known for the control of source current. To eliminate load current sensors, predictive model of the load is used in envelope estimation. Further, independent switching schemes are generated for each objective, and an error minimization approach is used in integrating the two schemes into a final state selection, hence eliminating weighing factors. Unlike MPC, error predictions for all states of MCs, are not needed, hence facilitating easier implementation without significant processor burden, besides ensuring the quality of response. [ABSTRACT FROM AUTHOR]

In the conventional direct power control (DPC) methods, the grid currents are highly distorted, and substantial ripple is present in the dc-bus voltage under unbalanced and distorted grid conditions. Various improved DPC methods have been proposed to address these problems, but these methods are generally complicated and not easy to use because of the complex controlling structures, need for considerable tuning, and so on. This paper proposes an improved DPC method obtained by simply adding a compensation term to the original power references. The compensation power is obtained by analyzing the power ripple in the input line inductance based on extended power theory. The reference voltage vector is subsequently calculated from the new power reference and synthesized by space vector modulation. To improve the robustness of the proposed DPC against inductance variations, an online inductance identification technique based on the gradient correction method is proposed and combined with the proposed DPC. The presented simulation and experimental results demonstrate that the proposed method can achieve sinusoidal grid currents and significantly reduce the dc-voltage ripple even with mismatched inductance under unbalanced and distorted grid conditions. [ABSTRACT FROM AUTHOR]

The pole-phase modulated induction motor (PPMIM) drives facilitate the extended range of speed-torque characteristics, which is an essential requirement for traction and electric vehicle applications. For getting the wider speed-torque variations, $15-\Phi $ PPMIM drive is analyzed, which is capable to operate at 2-pole 15-phase, 6-pole 5-phase, and 10-pole 3-phase modes. In these pole-phase operations, in high-phase and low-pole mode of operation, the increment in the linear modulation range with space vector pulsewidth modulation (SVPWM) is not significant. In the low-phase and high-pole mode of operation, there will be higher torque ripples due to the higher magnitude of space harmonics. In this paper, these issues are addressed by using carrier phase-shifted SVPWM (CPS-SVPWM) and phase grouping concepts. In low-pole operation, the linear modulation is enriched by using conventional $3-\Phi $ SVPWM to drive 15-phase machine by appropriately reorganizing the phase winding connections. Similarly, in 6-pole 5-phase mode of operation, the linear modulation range of PPMIM drive is enriched by using $5-\Phi $ SVPWM. It is known that in high-pole mode of PPMIM drive operation, each effective phase is formed by the multiple number of equal voltage potential coils (EVPCs), which are electrically in phase. The carriers of these EVPCs per phase are phase shifted by an appropriate angle to minimize the harmonics in the effective phase voltage, which results in better torque ripple profile. In addition, the detailed comparison of three possible different CPS-SVPWMs is presented, with their pros and cons for selecting the proper carrier phase shift angle. The performance of the proposed scheme has been validated by ANSYS Maxwell two-dimensional as well as laboratory prototype on 5-hp, $15-\Phi $ PPMIM drive. [ABSTRACT FROM AUTHOR]

Numerous studies show that power semiconductors are significant contributors to the overall failure rate of pulsewidth modulation (PWM) voltage source rectifier (VSR) systems. Aimed at this problem, this paper presents an improved diagnosis system for open-circuit faults of a three-phase PWM VSR based on ac current distortion characteristics, which consists of a diagnosis module, a register module, and a decision module. The diagnostic module employs a hysteresis comparator to judge the change trend of the currents, and thereby diagnoses the single open-circuit (OC) faults. The register module is employed to achieve multi-switch OC fault diagnosis, and the decision module is used to output the final result. The proposed method extends the previous work to multi-switch OC fault conditions as well as improves the diagnosis accuracy. The experimental results show that the proposed method can correctly achieve fault diagnosis, including 6 kinds of single-switch faults and 15 kinds of different double-switch faults. Additionally, the proposed method also shows superior anti-interference performance and high robustness under abrupt load transient conditions, different power factor conditions, unbalanced and/or distorted grid voltage conditions, and different ac filter structure conditions. Furthermore, the average diagnostic time of this method is only 3.68 ms. [ABSTRACT FROM AUTHOR]

The inductance is an important parameter impacting current ripple calculation, usually with the assumption that the designed inductance performs ideally in most of voltage source inverters (VSIs) applications. However, the initial permeability of magnetic material usually descends when the winding current reaches or goes beyond the saturation limit. In such region of saturation, the implemented inductor does not perform as expected in design stages and its value varies with the bias current. In this paper, analysis and calculation of the current ripple are presented for a three-phase VSI with powder cores-based inductors, which reveals the calculation error of current ripple caused by the soft saturation nature of powder cores. Based on the equivalent single-phase model, the influence of inductance saturation on current ripple can be quantitatively evaluated. Then, a comparison of the current ripple calculation between considering and ignoring inductance saturation of implemented inductors is drawn in detail. Furthermore, under the condition of inductance saturation, the output current ripple peak-to-peak value of three phases is used as the constraint for variable switching frequency pulsewidth modulation (VSFPWM) design. A comprehensive method is developed to compensate the effect of inductance saturation in VSFPWM. At last, the effectiveness of the proposed strategy is verified by the detailed simulation and experiment. [ABSTRACT FROM AUTHOR]

Owing to a uniform air-gap distribution of the magnetic powder materials, it is found that the conventional structure of a three-phase inductor made of magnetic powder cores will cause the three-phase magnetic flux paths to be unequal, thereby making the three-phase input voltages of a pulsewidth modulation (PWM) rectifier imbalanced. This paper presents a novel magnetic powder core structure applicable to a three-phase inductor for PWM rectifier. An equal magnetic flux path for the inductor core is designed to solve the imbalance problem of three-phase voltages. The proposed design is based on measuring the maximum flux density and the inductance values, modeled with electromagnetic simulation of a three-dimensional finite-element method. Simulation and experimental results of the proposed design show that it reduces the three-phase voltage imbalance to less than 3%. Furthermore, the unit volume of the three-phase inductor is reduced by 34% and 23%, and the efficiency is increased by 1.2% and 0.9%, compared to those of a conventional three-phase silicon-steel core inductor and three single-phase inductors, respectively. [ABSTRACT FROM AUTHOR]

The pulse-width modulated (PWM) switching rectification that can achieve a high power factor (PF) for increasing the energy transfer efficiency between an LC resonator and a rectifier and voltage step-up and -down conversion is proposed for a wireless power transfer (WPT) receiver. The proposed method can emulate the switching rectifier as a resistive load by using an inductor and integrated phase synchronizers. Additionally, similar to a switched-inductor converter that controls the duty cycle ratio (D), the proposed PWM rectifier can control the output voltage VOUT when the input is a rectified, wirelessly coupled voltage instead of a constant voltage. Thus, unlike a conventional PWM switching rectifier for ac mains, an additional voltage conditioning circuit would not be needed after the proposed rectifier for WPT. The proposed PWM switching rectification is implemented in the AMS 0.18 μm 1.8 V/5 V CMOS process. PF = 1 is measured, indicating the most efficient energy transfer, compared to only 0.55–0.65 in a peak detection rectifier. Additionally, 88.2% of peak power conversion efficiency of the switching rectifier is achieved, and the maximum output power is 80.3 mW at 500 kHz of the WPT frequency. Moreover, the measured voltage conversion ratios ranging between 0.73× and 2× are demonstrated in this paper. [ABSTRACT FROM AUTHOR]

When many distributed parallel inverters are integrated into grid without switching sequence coordinated control capability, the high-frequency harmonics will accumulate randomly at the point of common coupling. Global synchronous pulsewidth modulation (GSPWM) method can significantly attenuate the accumulated switching ripples by intentionally assuming an intelligent optimization algorithm and a communication system. To avoid the dependence on low-latency communication system, this paper proposes a novel phase-locked loop based PWM carrier synchronization (PLL-CS) method for GSPWM system, where the switching sequences can be effectively synchronized as expected without using low-latency synchronization signals. By doing so, the operational reliability of the whole GSPWM system can be significantly improved, while the additional hardware cost of GSPWM can be dramatically reduced, which can enhance the implementation adaptability of GSPWM method. Experimental results have verified the performance of the proposed PLL-CS GSPWM method. [ABSTRACT FROM AUTHOR]

This paper presents a novel seven-level inverter topology for medium-voltage high-power applications. It consists of eight active switches and two inner flying capacitor (FC) units forming a similar structure as in a conventional active neutral-point-clamped (ANPC) inverter. This unique arrangement reduces the number of active and passive components. A simple modulation technique reduces cost and complexity in the control system design without compromising reactive power capability. In addition, compared to major conventional seven-level inverter topologies, such as the neutral point clamped, FC, cascaded H-bridge, and ANPC topologies, the new topology reduces the dc-link voltage requirement by 50%. This recued dc-link voltage makes the new topology appealing for various industrial applications. Experimental results from a 2.2-kVA prototype are presented to support the theoretical analysis presented in this paper. The prototype demonstrates a conversion efficiency of around 97.2% ± 1% for a wide load range. [ABSTRACT FROM AUTHOR]

It is well known that spatial field harmonics will cause high eddy current losses in surface-mounted permanent magnets (PMs) especially for the fractional-slot PM motors. However, the influence of temporal current harmonics, especially of the high-order temporal harmonics caused by pulsewidth modulation voltages from an inverter, lacks attentions. This paper studies the eddy current losses of the PMs caused by high-order current harmonics. In order to simplify the calculation and save computation time, analytical methods are used to predict the current harmonics caused by the PWM inverter, and the armature reaction field, the eddy current density, and losses in the PMs generated by the current harmonics. Finite element analysis, coupling simulation, and experimental studies are used to verify the analytical results. The study results show that the high-order current harmonics cause much higher eddy current losses than those caused by slotting and fundamental current even though the amplitudes of the high-order current harmonics are much lower. [ABSTRACT FROM AUTHOR]

A novel pulsewidth modulation (PWM) scheme for the decoupled and coordinated control of two parallel connected split-phase induction machines is discussed in this paper for the first time. Both the motors are operated from a single six-phase voltage source inverter which acts as a power source, and two switched capacitor-fed auxiliary inverters to limit the flow of nontorque producing currents in each motor. Both the motors can be operated at its full rated power with low switching frequency, and decoupled control for full power range can be achieved with the proposed topology. This is possible because the individual machines do not carry the load/harmonic currents of other machine (unlike the conventional series or parallel connected systems). The converters can be modulated using sine-triangle PWM or space vector pulsewidth modulation (SVPWM). Furthermore, two different schemes of SVPWM techniques are proposed and compared in this paper. Exhaustive experimental results for all the modulation schemes are provided for steady state and transient operating conditions including start-up to validate the proposed topology and modulation schemes. [ABSTRACT FROM AUTHOR]

This paper introduces a novel H-bridge structured ac–ac pulsewidth modulation (PWM) converter topology based on two-level non-differential ac chopper legs, which can work at the non-inverting and inverting modes for the utility voltage compensation. Compared to the traditional bipolar-type H-bridge ac–ac converter, no bidirectional switches are switched in a complementary manner to overcome the commutation problem due to the delayed response of electronic circuits and semiconductor switching devices. The detailed PWM control signals and operational principles are presented to regulate the output voltage in a bipolar manner. Especially the main advantage is that the proposed ac–ac converter has the same buck/boost operation process for non-inverting and inverting modes, which ensures the continuously average current supply to the low-voltage output side without a high-value capacitor to support power. Additionally, due to the common sharing ground of the input and output, the feature that output can reverse or maintain phase angle with input is supported well. Then, the detailed analysis, design conditions, and experimental verification based on a 1 kW experimental prototype are presented. [ABSTRACT FROM AUTHOR]

In the six-step mode control of the interior permanent-magnet machine (IPMSM), inequality of the positive half-cycle length and the negative half-cycle length will bring about dc offset in the three-phase input current. This paper proposes a six-step mode control scheme of IPMSM for railway vehicle traction to eliminate the dc offset in input current. An approximately continuous rotor position signal is reconstructed in the field-programmable gate array chip. This position signal is used to generate the square drive signal for IPMSM in the flux-weaken region. Rotor position signal error of the resolver will also cause dc offset in the three-phase input current. A novel scheme using phase-locked loop to decrease the rotor position signal error is proposed. And using this scheme, the dc offset is eliminated from the three-phase input current. A seamless transition scheme from six-step mode control to space vector pulse width modulation (SVPWM) mode is proposed. The effectiveness of this six-step mode control scheme is proved by the experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes a new class of topologies of single-stage high-frequency ac-link power converters, which is capable of providing both voltage step up/down within a wide frequency and voltage ranges. The proposed family, which supports bidirectional power flow, can interface various single/multi-port dc and/or single/multi-phase ac systems to provide dc–dc, dc–ac, ac–dc, or ac–ac power conversion. In this family of converter, which offers a very modular structure, a small inductor that forms the link exchanges power entirely or partially between the source and load. The proposed family can function in buck, boost, and/or buck–boost modes of operation, and a combination of these modes of operation is also feasible. In comparison to the parallel inductive four-quadrant link converters, the proposed family features a significantly reduced link peak current, reduced switch ratings, and reduced total number of power switches. These features enhance the efficiency, reduce the total cost, and increase the power density of the system. In order to further improve the overall efficiency of the system, minimize the current/voltage stress over all utilized semiconductor devices, and lower electromagnetic interference (EMI), a small capacitor is placed in parallel with the link inductor to realize soft-switching operation for the proposed configurations. Moreover, the proposed converters have the potential to incorporate a lightweight single-phase high-frequency transformer for electrical isolation. The proposed circuit topologies prevent reverse recovery issues and eliminate losses corresponding to body diodes of power switching devices via utilizing power switches in conjunction with external fast recovery diodes. The proposed family offers a very high level of reliability owing to its immunity from short circuit of input and output terminals and open circuit of the link inductor, which may occur in other power converters due to commutation problem resulting from a short deadtime or an overlap time between switches, unwanted control command, delay in electronic circuits, or EMI noise's misgating on or off, in addition to the absence of electrolytic capacitors in the power circuit. A control approach is also developed to regulate input and output currents in one stage of power conversion. A detailed theoretical analysis, operation, design methodology, and control strategy of the proposed family are provided in this paper, and the effectiveness and performance of the proposed converter family are verified via simulation results and experimentally. [ABSTRACT FROM AUTHOR]

In order to reduce switching loss of neutral point clamped three-level inverter (NPC TLI), generally discontinuous pulsewidth modulation (DPWM) is used. But it can result in dc offset and ac ripple on neutral point (NP) voltage. So a novel pulse sequence DPWM (NPSDPWM) is proposed to reduce switching loss and control NP voltage simultaneously in this paper. NP voltage is controlled by choosing proper clamping modes. To avoid unexpected switching action during changing clamping mode, an improved pulse sequence is also presented. The switching loss and NP voltage ripple of NPSDPWM, traditional and proposed DPWM in previous literature are compared, respectively. The experimental results show that NPSDPWM has well NP voltage control ability and the switching losses are reduced effectively. [ABSTRACT FROM AUTHOR]

This paper introduces a novel five-level nested neutral point piloted (NNPP) converter and analyzes the operating principle of five-level NNPP converter. This paper presents a novel space vector pulse width modulation (SVPWM) algorithm based on gh coordinate for five-level NNPP converter. First, the common-mode voltage is reduced by choosing the appropriate redundant switching states. After that, the floating-capacitor voltage balance control strategy is presented. The appropriate switch combinations of each phase are determined by the control requirements of floating-capacitor voltages respectively and the hardware mapping method of the switching states is presented. Furthermore, the neutral-point voltage balance control strategy is presented. In order to balance the dc-link capacitor voltages, the seven-segment switching sequence is selected according to the control requirements of dc-link capacitor voltages and the neutral-point voltage regulatory factor is introduced to regulate the durations of the redundant switching states in a switching cycle. Finally, the validity of the novel SVPWM algorithm with decoupling control strategies of floating-capacitor voltages and dc-link capacitor voltages is verified by the experimental results of five-level NNPP converter under steady-state and dynamic conditions. [ABSTRACT FROM AUTHOR]

Rotor position estimated with high-frequency (HF) voltage injection methods can be distorted by voltage errors due to inverter nonlinearities, motor resistance, and rotational voltage drops, etc. This paper proposes an improved HF square-wave voltage injection algorithm, which is robust to voltage errors without any compensations meanwhile has less fluctuation in the position estimation error. The average position estimation error is investigated based on the analysis of phase harmonic inductances, and deduced in the form of the phase shift of the second-order harmonic inductances to derive its relationship with the magnetic field distortion. Position estimation errors caused by higher order harmonic inductances and voltage harmonics generated by the SVPWM are also discussed. Both simulations and experiments are carried out based on a commercial PMSM to verify the superiority of the proposed method and the investigations in this paper. [ABSTRACT FROM AUTHOR]

This paper proposed a new half-bridge (HB) LLC resonant converter family with pulse-width modulated (PWM) auxiliary switch (sLLC converter) for hold-up mode operation. The proposed sLLC converters could operate with synchronous rectifier, which is suitable for low-output voltage applications. In the proposed converters, an auxiliary switch is added at the primary side to provide charging path for the series resonant inductor. For nominal 400-V input, sLLC achieves same performance as conventional LLC converter, and all the good features such as soft switching are naturally retained. For slight input voltage fluctuation, frequency modulation is used to regulate the output voltage. When the input voltage reduces further, HB switches will operate at constant minimum frequency, and the auxiliary switch will operate in the PWM mode to energize the resonant inductor with the bus voltage directly during hold-up period. Thus, the converter achieves higher voltage gain, and the output voltage can be maintained at desired level. To verify the effectiveness of the proposed sLLC converter, operational principle and equivalent circuits will be carefully explained and analyzed in this paper. A 300-W prototype is built for 250–400-V input 12-V output application. [ABSTRACT FROM AUTHOR]

This paper studies pulse width modulation (PWM) techniques suitable for a four-level five-phase open-end winding (OeW) drive. The drive comprises a five-phase induction machine, supplied using two two-level voltage source inverters with isolated and unequal dc-link voltages, in the ratio 2:1. A decoupled carrier-based (CB) PWM modulation strategy, based on unequal voltage reference sharing between the two converters, is introduced in this paper. The stability of dc-link voltages in OeW drives is investigated next, using a novel analysis technique. Several modulation methods are analyzed and the results show that application of the coupled PWM technique, with carriers having in-phase disposition, leads to overcharging of the capacitor in the dc-link of the inverter intended to operate with the lower dc-link voltage. On the other hand, the proposed decoupled CB PWM scheme naturally eliminates the dc-link capacitor overcharging problem. These findings are verified experimentally, using open-loop V/f control. Two different decoupled CB modulation methods are compared and the best performing modulation method is selected and incorporated further into an OeW drive with field-oriented control. The presented steady state and transient experimental results demonstrate that the decoupled CB PWM technique is suitable for high-performance variable speed drive applications. [ABSTRACT FROM AUTHOR]