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In this research, a new architecture of dynamic latch comparator is presented, which is able to provide high-speed, consumes low-power and low offset voltage. The proposed comparator has been verified in a design, a 12-Bit SAR ADC(Successive Approximation Register Charge-Redistribution Analog-To-Digital Converter). The comparator consists of two stage pre-amplifier and a StrongLatch. The pre-amplifier adopts an inverter-based input pair and a pair of capacitances in output stage to reduce noise. It is shown by simulation and analysis that the offset voltage is significantly reduced compared to a conventional dynamic latched comparator. The proposed circuit is designed and simulated in 28 nm CMOS technology. The results show that, for the proposed comparator, the speed is 2.37 ns and consumes only 426.6 μ W power, at 1.8 V supply voltage and 330 MHz clock frequency. This article presents two kinds of FoM(Figure of Merit) to prove that the comparator has excellent performance. • Analysis of offset source of differential pairs. • Optimize comparator design. • Validate the comparator design. [ABSTRACT FROM AUTHOR]

As a result of increased interest in space applications, radiation-aware circuit design has become a major concern to guarantee the safe operation of electronic systems operating under extreme space conditions. As the first step, several ad-hoc simulation approaches have been developed in analog and digital domains to estimate the functional behavior of circuits exposed to high radiation. However, most of these tools are application specific and stand-alone (not integrated into the simulation tools). Also, several commercial CAD solutions exist; however, access to these tools is limited due to security measures. To this end, we have developed a well-equipped, SPICE-integrated, and free-to-access simulation tool, RadiSPICE, capable of running statistical radiation simulations and performing extended temperature and sensitivity analyses. By using RadiSPICE, one can readily predict the functional behavior of circuits after long-term or short-term radiation effects. Moreover, the sensitivity analysis reveals vulnerabilities of the design against radiation and provides valuable design hints to the designer to make circuits radiation-hardened. To demonstrate the proposed tool, we have performed several experiments on two analog building blocks with different topologies (bandgap reference and comparator circuits) using RadiSPICE and discussed the robustness of the designs in detail. • This article presents RadiSPICE, a SPICE-integrated, free-access simulation tool. • The tool is intended for radiation-aware circuit design, for space applications. • Statistical simulations for long- and short-term radiation effects are covered. • The sensitivity analysis tool provides radiation-aware circuit design insight. • The circuit functionality after long- and short-term effects is demonstrated. • Two analog blocks are simulated and investigated for robustness in detail. [ABSTRACT FROM AUTHOR]

In this paper, a modified successive-approximation-register analog-to-digital converter (SAR ADC) with a novel low power dynamic comparator at 0.2 V supply voltage is presented. The power consumption of SAR ADC has been reduced by 70% with design of proposed low-power comparator and using power reduction techniques such as power gating and reducing the supply voltage. Also, by custom design for unit capacitor in the SAR ADC, the area has been reduced by 46% compared to the conventional structure. The proposed ADC with a sampling frequency of 1 kS/s and power consumption of only 1.21 nW for biomedical applications has been designed and simulated in a TSMC 65 nm CMOS technology and occupies an area of 0.013 m m 2. The proposed biomedical ADC is verified using analog electroencephalogram (EEG) and electrocardiogram (ECG) inputs which demonstrate it is proper to quantize these biosignals. The figure-of-merit (FOM) of the proposed converter is 3.2 fJ/conversion-step. • Designing a modified ADC with an ultra low supply voltage (0.2 V) for biosignals acquisition. • Designing a novel 0.2 V, ultra low power dynamic comparator. • The power consumption of SAR ADC has been reduced by 70% with design of proposed low-power comparator and using power reduction techniques such as power gating and reducing the supply voltage. • 46% reduction of occupied area using custom capacitor design. [ABSTRACT FROM AUTHOR]

This paper presents a 16-bit 1-Msps successive-approximation-register analog-to-digital converter (ADC) with a split-ADC digital calibration scheme based on dynamic element matching. A multi-segment capacitor array with redundant bits is utilised for ensuring that missing-level errors are calibrated in the digital domain, reducing the area and power consumption. The key circuit modules are optimised, such as the low-power dual-mode cascade comparator and dynamic element matching control logic. The prototype is fabricated by a 0.18-μm CMOS technology, and it exhibits 170.47 dB figure of merit Schreier (FoMs), 15.04 bits effective number of bits (ENOB) and 119.50 dB spurs free dynamic range (SFDR). The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.422/0.536 LSB and −0.721/0.758 LSB, respectively. • A 16-bit 1 Msps SAR ADC is manufactured in 0.18 μm CMOS process with 170.47 dB FoMs. • A split-ADC digital calibration scheme based on dynamic element matching can improve the SFDR effectively. • A segmented capacitor array of 4 sub-capacitor arrays decreases the total capacitance of the high-resolution SAR ADC. • A dual-mode automatic zero comparator is utilised to reduce power consumption. [ABSTRACT FROM AUTHOR]

Achieving low propagation delay in comparators under low input overdrive voltage is challenging. To overcome this difficulty, this paper presents a novel rail-to-rail high-speed comparator. By clamping the output node of the current summation circuit relative to a fixed level V C , the overdrive recovery time under large signal is successfully reduced. Moreover,by adopting a cascaded approach with multiple stages of high bandwidth and low gain,not only is the comparator's gain enhanced,but it also acquires higher bandwidth. Ultimately, the comparator's output is transmitted at high speed through an LVDS interface. This design is implemented using 0. 18 μ m SiGe BiCMOS technology. Simulation results show that the comparator has a static power consumption of 26.4 mW, and for 5 mV input overdrive, the average propagation delay is about 1.09 ns. • The input common-mode range is expanded to rail-to-rail. • The propagation delay under small input overdrive is greatly reduced. • The static power consumption of the comparator is 26.4 mW. • The comparator's output is transmitted at high speed through an LVDS interface. • The comparator is implemented using 0.18 μ m SiGe BiCMOS technology. [ABSTRACT FROM AUTHOR]

In the present work, a methodology has been proposed to design analog/mixed-signal circuits using digital-in-concept circuits in digital technology. This paper presents a digital standard cell-based, scalable, highly synthesizable analog voltage comparator designed in 180 nm CMOS technology at the supply voltage of 1.8 V. The digital design requires less design effort and is highly immune to process, voltage and temperature variations. The proposed comparator has been designed and simulated in the Cadence virtuoso analog design environment. It is observed from the simulation results that the total power dissipation and propagation delay is 143.2 μW and 1.07 ns, respectively. The offset voltage of the proposed comparator is 4.98 mV. Also, as a proof-of-concept, the feasibility of the proposed analog voltage comparator is carried out on Artix-7 field-programmable gate array (FPGA) using Xilinx Basys-3 FPGA kit and other off-the-shelf components. The proposed digital-in-concept comparator is suitable for low power and high-speed SoC application with reduced design effort and lesser time-to-market. • A methodology to design analog/mixed signal circuits using digital-in-concept technique in digital technology is proposed. • Digital standard cell-based, highly synthesizable analog voltage comparator has been presented. • The proposed analog comparator has been implemented on Xilinx Basys-3 FPGA using other off-the-shelf components. • The proposed comparator is scalable to lower technologies due to its standard cell-based design methodology. • The proposed design takes less design effort, highly immune to process, voltage and temperature variations. [ABSTRACT FROM AUTHOR]

Power supply noise in current nanometer technologies represents a growing risk, specially because of the uncertainties it produces in the critical paths delays which can result in erroneous computations. Also, these very short variations can affect the functionality of analog circuits like a comparator or an ADC. To tackle with these issues and to have a better power management, on-line power supply monitors have become one common solution. Traditional approaches use an external reference, are very sensitive to temperature and process variations or present high latency. In this work we propose a 3 sigma monitor with a novel detector circuitry that employs a feedback loop that works without an external reference and it is hardened against temperature and process variations. The sensor was designed in the 40 nm CMOS technology node, operating at 1.1 V and has been validated for a temperature range of 0 ∘ C to 85 ∘ C covering all process corners. Also, considering the 3 σ confidence, the sensor is able to detect over/undershoots voltage fluctuations up to 2 GHz in the range of -70 mV to +90 mV from the nominal voltage with a maximum latency of 1.1 ns and an energy consumption per measurement of 0.8 pJ. [Display omitted] • Power supply noise in current nanometer technologies represents a growing risk. • There is a need to tackle the supply voltage noise with a better power management. • On-line power supply monitors have become one common solution. • We propose a 3 σ monitor with a novel detector circuitry. • The monitor is hardened against temperature and process variations. • The sensor covers the commercial temperature range of 0° C to 85° C. • The proposed architecture presents small area and energy per measurement overheads. [ABSTRACT FROM AUTHOR]

In this paper, a rail-to-rail time-domain comparator with low power supply voltage and low power consumption is introduced. The comparator can be employed in low-power converters and biomedical applications. In the proposed time-domain comparator, a rail-to-rail delay element has been employed to generate a significant voltage-to-time gain for the full range of input signals. This circuit is designed, laid out, and simulated in 0.18 μm TSMC technology and powered by 0.6 V and 1 V supply voltages. The simulation results show that the proposed comparator has a rail-to-rail dynamic range and the power consumption of the circuit is 0.6 μW and 19 μW at the clock frequency of 10 MHz and 100 MHz, respectively. The active area of 56 μm × 14 μm shows the compactness of the circuit comparing to the other similar works. The proposed comparator was used in an ADC to show its effectiveness to improve the performance of the ADC. An 8-bit 0.8 V 100 kS/s SAR-ADC is designed and simulated. It consumes 430 nW and the figure of merit is 19.3fJ/conversion-step. • Time-domain comparator is an alternative to conventional voltage-mode comparator. • V-to-T conversion is performed by controlling the capacitor discharging rate. • Offset, noise and power consumption are main problems in comparators. • Figure of merit (FoM) is used to characterize the performance of the comparator. [ABSTRACT FROM AUTHOR]

This work presents an ultra-low-power classifier that can be integrated within energy-constrained bio-sensors to enable rapid analysis for continuous health monitoring. The in-sensor classifier saves significant transmission energy by extracting critical information locally to eliminate the need of transmitting raw data to centralized servers for remote signal processing. The convolutional-neural-network (CNN)-based classifier is built by using reconfigurable delay-locked loops (DLLs) to carry out classification algorithms with time-domain multiply-accumulate (MAC) operations. Pseudo sigmoid activation functions are realized by regenerative comparators that transform weighted timing to probabilities. The presented classifier achieves low-power consumption of 240.34 nW while performing up to 20 k operations per second. The proposed time-domain classifier reduces the energy to 36% of the previous works. • In-sensor classifier that locally extracts critical features for rapid analysis. • Cascaded DLLs to perform precise multiplication and accumulation. • Regenerative comparator output as sigmoid activation function to estimate probability. • Time-domain operations for low supply voltages. • Integrated with edge sensors to enable long-term continuous bio-signal monitoring. [ABSTRACT FROM AUTHOR]

This paper presents a highly efficient ternary flash ADC, designed using the innovative gate-overlap tunnel FET (GOTFET) at the 45 nm technology node. The proposed GOTFETs have on-state currents I on more than double, while the off-state currents I off remaining at least an order of magnitude lower than the corresponding values of the standard 45 nm CMOS technology with the same width. Replacing MOSFETs with the proposed GOTFETs significantly reduces the static power consumption and improves performance. However, the higher I on increases the dynamic power as well. To minimize the dynamic power, we propose a novel complementary GOTFET (CGOT) based comparator design. In addition to the inherent advantages of the GOTFET technology, the proposed design further reduces the dynamic power, such that the final power delay product (PDP) is merely 6.3% of the PDP in conventional CMOS comparator design. In addition to the novelty related to the innovative GOTFET devices, there are at least two-fold circuit-level novelty reported in this work. Firstly, we propose a novel CGOT based comparator circuit design, which, in addition to the advantages of GOTFET, further reduces the dynamic power such that the PDP is less than 1/3rd of the original PDP of the conventional comparator designed with GOTFETs. Secondly, the proposed CGOT based ADC requires only 48 transistors to encode the comparator outputs into the 2-bit ternary output, which is 30% lower than the 70 transistors necessary for the 2-bit CMOS based ternary flash ADC designs reported earlier in the literature. We propose an efficient 2-bit ternary flash ADC with a resolution of 50 mV and input quantized to 9 levels. Subsequently, we benchmark the performance of the proposed CGOT ternary flash ADC with the same ADC circuit implemented using the standard 45 nm CMOS technology library, all corresponding devices having the same width. We demonstrate that in addition to the superior performance than the corresponding CMOS ADC, the proposed CGOT ADC design consumes significantly lower power. The overall PDP of the proposed CGOT ADC is merely 6.3% of the PDP in corresponding CMOS design. • Gate Overlap Tunnel FET : On Current more than double & Off current an order of magnitude lower than 45 nm CMOS. • New GOTFET based Comparator Design: PDP is merely 1/3rd of that of conventional comparator. • New GOTFET based Comparator Design: PDP is merely 1/3rd of that of conventional comparator. • Reduced Transistor Count : Requires only 48 transistors compared to 70 required for conventional designs. • Reduction in PDP : GOTFET based ADC shows 99.7% improvement in PDP. [ABSTRACT FROM AUTHOR]

Digital comparators are important arithmetic components used in digital systems to determine if two numbers are equal, or if one number is greater or less than the other. In this work, the design of magnitude and 2's complement comparators is examined. New OR-based full tree and simplified tree magnitude comparator architectures are proposed. The existing and the proposed comparator architectures are implemented in standard cell technology and evaluated, after extensive experimental analysis, in high performance and relaxed conditions. The proposed comparators operate faster than the existing ones, while operating at the same speed yield significant improvement in area complexity and power dissipation. [ABSTRACT FROM AUTHOR]

In this paper, a low-power method for double-tail comparators is introduced. Using the proposed method, the power consumption of the pre-amplifier which is the dominant part is reduced considerably. Thanks to this method, the pre-amplifier is not able to draw more than required amount of power, therefore, the power is saved. Post layout and corner simulation results show the power consumption is reduced by about 40%. Moreover, several Monte-Carlo (M) simulations suggest the proposed method results in about 20% offset reduction at the cost of 5% area and 10% speed degradation. • In dynamic comparators, the pre-amplifier amplifies the input differential signal to some extent then the latch finalizes the comparison. After some moment from the latch activation, the pre-amplifier is wasting power and sometimes reduces the gain worsening the power consumption and offset voltage. The aim of the proposed comparator is to overcome this issue. In low-offset comparators, the sizing of the input transistors of the pre-amplifier is chosen large for matching purposes so that the pre-amplifier consumes the dominant part of the total power consumption making it a good candidate to work on for low-power applications. In this paper, a low power method for dynamic comparators is presented using which the power consumption of the pre-amplifier is controlled in a proper way. Therefore, not only the power is saved but also the input referred offset voltage is improved. • In the paper, analytical derivations are presented to quantify the amount of power saving. Simulations showed the derivations are consistent with the circuit. The proposed method is able to reduce the power consumption by about 30%-40% and the offset voltage by about 20%. Post layout simulation of the RC-CC extracted circuit confirms the benefits of the proposed comparator. • The proposed method is applicable to different types of the double tail comparators. This method is simple yet effective in power reduction. [ABSTRACT FROM AUTHOR]

This work presents a design flow for asynchronous, self-timed dual-rail circuits which introduces a timing assumption in the return-to-spacer phase. The design flow enables power proportionality and is demonstrated through the design of a 32-bit ripple-carry adder and a 32-bit comparator for internet of things applications. The designs are synthesized to a 65 nm cell library with state-of-the-art transistor sizing for subthreshold. Simulation results show improved performance and energy per computation across operating conditions compared with single-rail equivalents. The design flow allows extension of the power proportional philosophy to a wider range of circuits. • A novel sizing strategy for CMOS cells in subthreshold is presented. • A design flow for dual-rail circuits is presented for IoT applications. • The design flow produces circuits with improved energy and delay over single-rail. • Adder and comparator circuits benefit from early propagation. • Early propagation improves average-case performance. [ABSTRACT FROM AUTHOR]

This paper proposes a new method that compares the magnitude between multiple digital input signals and introduces its logic circuit at RTL (register transfer level). For simultaneously comparing multiple inputs, the proposed algorithm uses a simple digital logic function to provide information of the largest (or smallest) value and position for these inputs. The disadvantage of using this method is that it incurs an increase hardware resource usage. To overcome this, we propose a reuse method for the overlapped logic operation. The proposed method focuses on improving the operational clock frequency, in other words, decreasing combinational delay time. After implementing the comparison method with Verilog-HDL (hardware description language), we conduct an experiment with the 28 nm CMOS library provided by TSMC Inc. In the case of 4, 8, 16, and 32 input signals, the proposed method can increase the operating clock frequency by as much as about 1.65, 2.42, 3.28 and 3.45 times, respectively, with about 1.04, 0.97, 1.84 and 4.26 times the hardware resources. • A new method to compare the magnitude between multiple unsigned digital input signals. • Simultaneously comparing multiple inputs with a simple logic function. • Experiment with the 28 nm CMOS library. • In the case of 4, 8, 16 and 32 input signals, high speed clock frequency as much as 1.65, 2.42, 3.28 and 3.45 times. [ABSTRACT FROM AUTHOR]

Abstract A new leakage tolerant high speed domino gate having higher noise immunity, low power dissipation, and less process variations for wide fan-in OR logic is developed. This paper deals with the design of a high speed comparator based domino gate with low leakage that decides the output on the basis of voltage difference across the pull down network. In order to design mirror of voltage comparator, PMOS is replaced by NMOS for low process variation. Furthermore, stacking of NMOS is accomplished to reduce leakage and total current transfer in cascode fashion. Hence, the proposed domino can be operated in deep submicron regime. The simulation results confirm that the proposed domino gate exhibits about 17.58% power dissipation reduction and 1.21 times noise immunity improvement in contrast with reported voltage comparison based domino. The simulation results are achieved with Cadence Virtuoso environment using SPECTRE simulator in 45 nm CMOS technology. Highlights • A leakage-tolerant high speed comparator based domino wide fan-in OR gate for high speed application, is designed to resolve trade-off between process variation, noise immunity, and power dissipation. • The proposed gate exhibits low power dissipation and power delay product in comparison to reported standard domino and voltage comparison based domino. • The proposed gate shows higher immunity in comparison to reported standard domino and voltage comparison based domino. • The proposed domino gate is more stable against process, volatage and temperature (PVT) effect. [ABSTRACT FROM AUTHOR]

On switching a transmitter at gigahertz rate, the data at the receiver's end gets distorted in terms of pulse width and voltage due to line loss and dispersion originating from channel electrical characteristics. Signalling using current sources is an established approach for high frequency applications, but different receiver circuits have been proposed to effectively sense the low voltage swings around some reference voltage, V T . At first, the V T is identified at the receiver's input by a unique method and the corresponding value is found to be 0.822 V. Thereafter, a signalling scheme has been proposed to have two different current sources capable of generating a low voltage swing around V T at the receiver's end and at the same time compensating the line loss of the channel. The low voltage swings around V T cause leakage current to increase. The proposed methodology reduces the constant short circuit current due to low voltage swings around V T almost close to 0 from 56 μA for 60 mV swing. The PVT analyses of the V T determination circuit and the proposed signalling scheme indicate the sensitivity of the proposed approach while operated at 1 GHz switching frequency. Further, the crosstalk analysis for a 60 mV swing around V T at 180 nm CMOS process and single ended point to point drivers portrays that the desired s/h (s is the edge to edge space between two traces and h is the corresponding height from the ground plane) has to be greater than 2.3 for crosstalk noise to be below the critical value. Measurements and simulations also indicate that the proposed methodology for terminated design consumes only 1.08 mW for data transfer over point to point interconnects compared to conventional schemes. [ABSTRACT FROM AUTHOR]

Comparison is a difficult operation in residue number systems (RNS). Besides the straightforward comparison of binary equivalents of RNS numbers, shortcut methods for moduli-set τ ={2 n −1, 2 n , 2 n +1} have been proposed that only slightly improve the corresponding figures of merit. On the other hand, we have encountered only one hardware realization of 4-moduli RNS comparison, where the corresponding moduli-set does not include any power-of-two modulo. In this paper, we examine and provide shortcut RNS comparators for three moduli-sets with four modulus, all containing τ as a subset. Evaluation results show 15–136% speed-up and 39–366% less energy in comparison to the straightforward reverse-and-compare comparators. [ABSTRACT FROM AUTHOR]

This paper presents a new approach to analysis of residue probability density function (pdf) in pipelined ADCs. This work was performed based on the fundamental theorem for function of a random variable to map stage input pdf to its output density. It will be shown that residue pdf converges to uniformity. For the stages with half-bit redundancy, this uniformity is accompanied with an extra bit of resolution. Also, the minimum number of stages required to achieve a given value of resolution improvement are studied. Investigating the impact of backend stage on this extra resolution, the appropriate backend to maintain the most extra resolution is proposed. Examining the allowable comparator offsets in different stages, we can see that with decreasing the offset errors in final stages, offset errors impact of the first stages on the final residue pdf and the total converter resolution can be eliminated. [ABSTRACT FROM AUTHOR]

In this paper, a new charging scheme for reducing the power consumption of dynamic circuits is presented. The proposed technique is suitable for large fan-in gates where the dynamic node discharges frequently. Simulation results demonstrate that the proposed method is efficiently controlling the internal voltage swing and hence decreasing the power consumption of the wide fan-in OR gate without sacrificing other circuit parameters such as gate speed, area or noise immunity. The power-delay product of a simulated 8-input OR gate is reduced by 46%, compared to its conventional dynamic counterpart in the 90 nm CMOS technology. Another important benefit of the proposed approach is 99X reduction in power dissipation of the gate load by limiting its switching activity. Furthermore, the delay of the proposed circuit experiences only 0.94% variation over 10% fluctuation in the threshold voltages of all transistors for a 32-bit OR gate. Using the proposed technique, a 40-bit tag comparator is simulated at 1 GHz clock frequency. The power consumption of the designed circuit is as low as 1.987 µW/MHz, while the delay and unity noise gain (UNG) of the circuit are 244 ps and 499 mV, respectively. [ABSTRACT FROM AUTHOR]