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The successful implementation of artificial intelligence algorithms depends on the capacity to execute numerous repeated operations, which, in turn, requires systems with high data throughput. Although emerging computing‐in‐memory (CIM) eliminates the need for frequent data transfer between the memory and processing blocks and enables parallel activation of multiple rows, the traditional structure, where each row has only one identical input value, significantly limits its further application. To solve this problem, this study proposes a dual‐SRAM CIM architecture in which two SRAM arrays are coupled such that all operands are different, thus rendering the use of CIM considerably more flexible. The proposed dual‐SRAM array was implemented through a 55‐nm process, essentially delivering a frequency of 361 MHz for a 1.2‐V supply and energy efficiency of 161 TOPS/W at 0.9 V supply. [ABSTRACT FROM AUTHOR]

Transition metal dichalcogenide field‐effect transistors (TMDFETs) as a replacement for conventional metal–oxide–semiconductor field‐effect transistors (MOSFETs) have attracted the attention of researchers in recent years. The efficiency of these devices should be investigated in different aspects in digital systems. One of the important components of such systems is dynamic random‐access memory (DRAM), which is used in most computers and many electronic systems as the main memory due to its small area and simple structure, compared to static memory (SRAM) cells. In this paper, a regular DRAM cell is designed based on TMDFET devices and its performance is compared with a similar cell in conventional MOSFET technology from various aspects, including DRAM‐specific timing characteristics considering changes in design and environmental parameter variations using Monte Carlo simulations. The simulations have been carried out in HSPICE with 16 nm technology under fair conditions for different technologies, at room temperature with a 0.7‐V power supply. The results show that the TMD‐DRAM has 3.55×, 3.08×, and 2.23× faster bitline recovery, merge time, and sense time than Si‐MOS‐DRAM, respectively. The Si‐MOS‐DRAM, on the other hand, has 1.65× faster write time compared to TMD‐DRAM. However, TMD‐DRAM consumes overall higher power than Si‐MOS‐DRAM, and shows higher average read power variability with the σ/μ = 0.476. The TMD‐DRAM also shows higher variability in the studied timing characteristics than Si‐MOS‐DRAM except merge and sense times. [ABSTRACT FROM AUTHOR]

The excessive power usage in modern digital equipment is triggered by memory arrays, mainly including Static Random‐Access Memory (SRAM) chips. Many scientists are working to create an SRAM cell that is fast, highly stable, and uses little power. However, the traditional SRAM cells have instability and read/write failure at scaled technology nodes. This study proposes a Differential Power Schmitt‐Trigger Logic 9 Tcompute SRAM (DPSTL‐9 TCSRAM) cell design with high read‐and‐write stability and low energy consumption. In SRAM cells, the sensing amplifier (SA), pre‐charge circuit, row decoder, and column decoder are the primary operational elements. Through the use of a single‐bitline (SBL) configuration and a one‐sided Schmitt‐trigger (ST) inverter (STI), the proposed deisgn cell achieves an outstanding read stability performance. In this work, the differential Power Generation (DPG) technique is employed to improve the architecture's writing capacity. The standard AND gates are combined with Schmitt‐trigger logic AND gates to improve noise tolerance while consuming less power and taking up less space. Instead of using a power‐gating mechanism, this research focuses on modifying a power delay product (PDP) circuit to increase the cell's read‐and‐write operation efficiency. The modified decoupled SA plays a major role in the access time and provides significant benefits in terms of read latency. Tanner EDA Tool platform version 16.0 can be used to execute the specified design. The performance metrics of stability, area, latency, and power analysis are examined, and also, the Monte Carlo simulation and reliability simulation are conducetd to show the efficacy of the proposed design. [ABSTRACT FROM AUTHOR]

Summary: Static Random Access Memory (SRAM) is vital in aerospace applications, but it may experience soft errors in strong radiation environments. This paper proposes a reconfigurable radiation SRAM with two operating modes catering to different environmental requirements: (1) traditional triple modular redundancy mode used when the radiation environment is strong and (2) SRAM cell expansion mode used when the radiation is not very strong. For example, when the memory capacity of a single module is 8 k, the memory capacity is 8 k in traditional triple modular redundancy mode, but it can be tripled to 24 K in extended mode. As can be obviously seen, this design can adjust the size according to the needs. In SRAM cell expansion mode, the proposed 14T SRAM cell enables the memory to maintain radiation resistance. Compared with DICE, RHBD‐12T, and WHIT, the read speed is improved by 3.8%, 5.7%, and 11.5% respectively, but compared with WE‐QUATRO, the read speed is reduced by 1.9%. The hold static noise margin is 1.378 times than DICE, 1.201 times than WE‐QUATRO, 1.045 times than RHBD‐12T, and 1.14 times than WHIT, respectively. The proposed 14T cell in this paper exhibits the highest critical charge value compared with the other cells. Combined with the expansion mode of the reconfiguration design, it shows great stability. [ABSTRACT FROM AUTHOR]

Summary: As the scale of the integrated circuit increases, the distance between transistors decreases, a trend that reduces the critical charge of the sensitive nodes of the memory cell. Consequently, Static Random Access Memory cells in high radiation environments are very prone to soft errors. A novel radiation‐hardened memory cell, the Polarity Reinforcement Feature (PRF)‐18T, is proposed in this paper, which uses the polarity reinforcement feature to reduce the number of sensitive nodes in the memory cell and can entirely and effectively tolerate single event upset and double node upset. A comparison is made in this paper with DICE‐12T, Quatro‐10T, SEA‐14T, RHBD‐14T, NASA‐13T, and SCCS‐18T memory cells in a simulation environment with Semiconductor Manufacturing International Corporation 55 nm process, the supply voltage of 1.2 V, and temperature of 25°C. In comparison, the PRF‐18T proposed in this paper has the highest critical charge value, improving by more than 15× and 3.1× compared to the DICE‐12T and RHBD‐14T, respectively, and by more than 79% and 17.6% compared to the Quatro‐10T and SEA‐14T, respectively. In the high hold static noise margin comparison, the improvement over the SEA‐14T, DICE‐12T, RHBD‐14T, and Quatro‐10T is 26.7%, 3.8×, 1.5×, and 1.2×, respectively. In the write static noise margin comparison, the results were similar to the Quatro‐10T, DICE‐12T, and SEA‐14T, with a 68.5% improvement compared to the RHBD‐14T. Finally, the robustness of the proposed cell to process, voltage, and temperature variations is verified by temperature change experiments and 2000 Monte Carlo model simulations. [ABSTRACT FROM AUTHOR]

Summary: In this paper, a highly stable and low‐cost 12T (HSLC12T) radiation hardened static‐random‐access‐memories (SRAM) cell is proposed in 55 nm CMOS technology. Based on polarity reversal design and read/write separation structure, the proposed HSLC12T cell can recover from any single event upsets (SEUs) induced at all its sensitive nodes and even single event double‐node‐upsets (SEDNUs) induced at its internal storage node pair Q‐QN, while also having the maximum read static noise margin (RSNM) and lower static hold power, as well as excellent write speed and write‐ability. Though the HSLC12T cell exhibits a larger read delay, it has the best overall performance of all other cells. This is proven by having the highest electrical quality metric (EQM) value, thus making the proposed HSLC12T cell a better choice for aerospace applications. [ABSTRACT FROM AUTHOR]

Summary: Static random‐access memory (SRAM) is a cornerstone in modern microprocessors architecture, as it has high power consumption, large area, and high complexity. Also, the stability of the data in the SRAM against the noise and the performance under the radian exposure are main concern issues. To overcome these limitations in the quest for higher information density by memory element, the ternary logic system has been investigated, showing promising potential compared with the conventional binary base. Moreover, carbon nanotube field effect transistor (CNTFET) is a new alternative device with proper features like low power consumption and threshold voltage dependency on diameter. This paper proposes a new design for ternary SRAM using CNTFET and its evaluation by comparing it against two other designs in many aspects. Moreover, we investigated the static noise margin for the three designs to discuss their stability. Furthermore, we studied the reliability of the designs by evaluating the soft errors effect. [ABSTRACT FROM AUTHOR]

Summary: As transistor feature size is scaling down, the probability of charge sharing in a space‐radiation environment increases because of the reduced distance between adjacent transistors. The single‐event multiple‐node upset (SEMNU) caused by charge sharing is a major source of data errors in high‐density static random‐access memory (SRAM). In this paper, a radiation‐hardened SRAM using polarity hardening is proposed. Compared to other cells (RHPD‐12T, RSP14T, SEA14T, We‐Quatro, QUCCE12T, SARP12T, SIS10T, and 12T), the proposed RHC‐14T cell saves 8.47%, 91.34%, 162.71%, ‐20.63%, −20.50%, 113.18%, 63.27%, and 20.60% of the read‐delay time and 7.96%, 66.17%, 68.16%, 57.71%, 22.39%, 12.44%, 1,010.45%, and 13.43% of the write‐delay time, respectively. Moreover, this excellent performance entails only minimal power consumption. The proposed cell can work well in the radiation‐intensive space environment. [ABSTRACT FROM AUTHOR]

This paper presents a one‐sided 10‐transistors static‐random access memory (SRAM) cell appropriate for the internet of things (IoT) applications in which energy‐efficient SRAM cells are necessary to raise the battery lifetime. The bit‐cell core of the proposed SRAM cell is composed of two inverters with different structures based on the gate‐wrap‐around (GWA) carbon nanotube (CNT)‐gate‐diffusion input (GDI) technique and only one‐bit line to perform both read and write operations to minimize active power consumption. The proposed bit‐cell uses a transmission gate network and write‐assist schemes to significantly improve the write‐ability and stack read‐decoupling technique to enhance hold‐/read‐stability. Moreover, a memory mini‐array has been implemented using the proposed cell along with all the principal circuitries. Extensive Monte Carlo (MC) simulations show that write/hold/read static noise margins (SNMs) are improved by about 1.252, 1.196, and 1.152 times, respectively. Also, the results of evaluating the write‐ and read‐yield parameters for the proposed SRAM bit‐cell are about 22% and 13% better than counterpart bit‐cell designs, respectively. In addition, the bit error rate (BER) and energy dissipation parameters for the proposed memory cell are almost 61% and seven times higher than the studied SRAM bit‐cell in the same simulation process. Finally, to evaluate the effectiveness of the proposed SRAM bit‐cell in the real‐world application, a memory array architecture with an online (or off‐chip) adaptive power supply voltage based on a hardware algorithm for storing digital images at a minimum energy dissipation is proposed. Our simulation results emphasize that the proposed memory array can be a good candidate for energy‐efficient and noise‐immunity IoT platforms. [ABSTRACT FROM AUTHOR]

The modern system‐on‐chips require stable and low‐power SRAM cells due to technology scaling and limited sources of energy. Therefore, a stability‐ and power‐improved 11T SRAM cell is proposed in this study. The proposed cell core is composed of a strong cross‐coupled structure of a conventional inverter with a N‐type stacked transistor and a Schmitt‐trigger (ST) with a double channel‐length pull‐up network. This coupled with a separate read path enhances the read static noise margin (RSNM). Moreover, a feedback‐cutting N‐type transistor is placed inside the cell core to improve the write static noise margin (WSNM)/write margin (WM). Though the presence of stacked transistors in access paths increases read delay (TRA)/write delay (TWA), it reduces leakage. This metric further minimizes with the aid of a stacked structure of latch core and double channel‐length of pull‐up transistor in the ST inverter. The moderate read/write frequency and single‐ended structure of the suggested cell result in low dynamic power. Simulated results by using 16‐nm CMOS at VDD = 0.7 V show that the proposed cell has the second‐best RSNM/WSNM, which is 4.65/1.44 times higher than that of the fully differential 8T (FD8T) cell, as the basic cell. Moreover, it reduces leakage power by at least 2.01 times and consumes moderate read/write power, nearly 1.44/1.81 times lower than that of FD8T cell, at the cost of 1.61 times area overhead. The proposed cell can eliminate read/write‐half‐select‐disturbance issues to support bit‐interleaving architecture to increase soft error immunity. [ABSTRACT FROM AUTHOR]

This paper presents a robust low‐power 10T SRAM cell (RLP10T) with a novel read/write assist mechanism, improving both read static noise margin (RSNM) and write static noise margin (WSNM) simultaneously. To assess its relative strength, we compared the proposed cell with recently published SRAM cells such as WRE8T, 10T‐P1, HFBS10T, WALP11T, and SE11T in 16‐nm CMOS technology node. The RLP10T cell shows 3.55/1.07 times higher/lower RSNM compared to the WRE8T/WALP11T cell and offers at least 1.10 times higher WSNM. Due to the presence of three series‐connected transistors in its read path, which includes a strong pull‐down transistor, the proposed design shows 1.23 times shorter read delay (TRA) than that of 10T‐P1/HFBS10T cell. The proposed cell incurs a penalty of high write delay (TWA) due to its long write path. However, it exhibits the fourth (second)‐best read (write) power, attributed to its single‐ended structure and lower read (write) frequency. It also dissipates acceptable leakage power due to its single‐bitline structure and the presence of stacked transistors in its read path and pull‐down path of one of the inverters in the cell core. Subjected to the severe process, voltage, and temperature variations, the RLP10T cell offers at least 1.31/1.09/1.03 times lower variability in RSNM/WSNM/TRA at VDD = 0.7 V, at the cost of 1.22 times area overhead compared to the WRE8T cell. [ABSTRACT FROM AUTHOR]

A memory Alias Table holds a major role in Register Renaming Unit (RRU), which is responsible for maintaining the translation between logical registers to physical registers under the given instruction(s). This work presents the design of the memory Alias Table based on the SRAM‐based 8T‐Cell with multiport write, read, and content‐address operations for two‐way three operands machine cycle. The design of the memory Alias Table of size 32‐row × 6‐bit has SRAM‐based CAM cell of type 21T‐Cell that comprises four‐read ports, two‐write ports, and two‐content‐address ports. The content‐address examines the register under‐test against all contents of the memory Alias Table in parallel and releases the associated match index address. Results show that the four read ports operate simultaneously within the half‐cycle, while the two write ports operate simultaneously within the other half‐cycle. The operation of the two content‐address ports is managed during the half‐cycle of the read phase. Thus, the three operations occur within a single cycle without latency. HSPICE simulations using 90 nm/1 V CMOS process reveal that the memory Alias Table provides the three operations within a one‐cycle of 1 GHz consuming an average power of 0.13 mW. [ABSTRACT FROM AUTHOR]

Summary: This work presents a robust and low leakage new 8T static random access memory (SRAM) cell without any half‐selection disturbance. The proposed cell removes write disturbance by eliminating the trail from supply and ground. Furthermore, it removes the read disturbance by separating the read trail from the storage node. The proposed cell addresses the challenge of half select by using different control signals. The cell achieves low leakage because of virtual ground (VGND), series connected tail transistor, and access series stack transistors. To study the usefulness of the proposed SRAM, it is compared with 6T, 10T, 9T, PG9T, 7T, and 8T SRAM cells. The proposed SRAM minimizes leakage power, write power, and read power by 12.4%, 21.62%, and 29.06%. Furthermore, the proposed cell improves read and write noise margin by 57.19% and 19.96%, respectively, as compared to a conventional 6T SRAM. Again, the write energy consumption lowers to about 43.86× while read energy consumption 28.95× as compared to 10T SRAM. [ABSTRACT FROM AUTHOR]

The design of power‐efficient SRAM cells is necessary for biomedical applications such as body area networks (BANs) to extent their battery life. SRAM cell's power consists of two main components, including leakage power and dynamic power, in which the former overcomes the latter in advanced technology. This paper presents a low‐leakage single‐bitline 9T (L2SB9T) SRAM cell. The proposed design is free from read‐disturbance issue and eliminates writing "1" problem. The results are carried out by utilizing HSPICE and 16‐nm CMOS PTM at a 0.7 V, 25°C, and under severe PVT variations. The proposed L2SB9T SRAM cell is comprehensively compared with other recently published SRAM cells including conventional 6T, write/read enhanced 8T (WRE8T), transmission‐gate 9T (TG9T), read‐disturb‐free 9T (RDF9T), fully differential 10T (Chang10T), data‐independent read port 10T (DIRP10T), and single‐bitline 11T (SB11T). It shows at least 1.26X/1.07X/1.01X improvement in read static noise margin (RSNM)/write static noise margin (WSNM)/write margin (WM). Furthermore, the leakage power is reduced by the proposed cell, at least 1.137X. Moreover, the suggested cell consumes the third/second best dynamic read/write power, which is 1.42X/1.37X lower than that of conventional 6T SRAM cell. The proposed L2SB9T SRAM cell performs its read/write operation reliably by showing at least 1.71X narrower speared in RSNM compared to the best SRAM cell and third best WM variability. For all these improvements, the proposed L2SB9T SRAM cell incurs a 4.20X/1.06X/1.808X penalty in read delay/write delay/layout area when compared with the best SRAM cells, that is, the Chang10T/6T/6T. [ABSTRACT FROM AUTHOR]

Conventional static random‐access memory (SRAM) suffers from high leakage power in advanced complementary metal‐oxide‐semiconductor nodes. Meanwhile, gain‐cell embedded dynamic random‐access memory (GC‐eDRAM) is an area‐efficient alternative to SRAM, although it requires periodic refresh cycles. In this regard, this study proposes a fin field‐effect transistor (FinFET)‐based 5T GC‐eDRAM bitcell that addresses the leakage power issue of SRAM while avoiding the bandwidth‐consuming refreshes of GC‐eDRAM. Furthermore, for the feasibility of scaling down transistors, the gain‐cell design is based on the FinFET, which overcomes short‐channel problems. The proposed 5T bitcell provides additional internal feedback relative to the 4T all‐nMOS fully depleted‐silicon on insulator (FD‐SOI) gain cell to ensure the static retention of both "1" and "0" data. The 2‐kB array was simulated by employing a 7‐nm FinFET predictive technology model (PTM) using HSPICE. The simulation results show that the proposed 5T bitcell (at 0.7 V) enables over 13× smaller data retention power and 10× area reduction compared to the 4T all‐nMOS GC‐eDRAM cell in a 28‐nm FD‐SOI technology. [ABSTRACT FROM AUTHOR]

This paper presents a process voltage temperature (PVT)‐variation‐tolerant Schmitt‐trigger‐based 12T SRAM cell at 32 nm. The cell uses a modified Schmitt‐trigger action in all operating modes for performance improvement, a characteristic that is not exhibited by existing SRAM cells. The action improves the stability of stored data in read and hold modes and assists the write process to enable a faster and low‐voltage write operation. Additionally, the cell uses negative bitline technique and fully‐gated grounded scheme for achieving further improvement in write ability and ION/IOFF ratio. The proposed cell shows 34.9% reduced deviation in switching threshold voltage in comparison to conventional structure. Further, improvement of up to 211% in write ability and 169% in ION/IOFF ratio is obtained over existing SRAM cells operating in sub‐threshold region. The cell takes up to 86% and 99% lesser read and write access time, respectively. The Monte‐Carlo simulations show the robust performance of proposed cell. The cell has reduced write, read, and hold failure probabilities resulting in overall Vmin of 425 mV, which is the least among the cells considered for comparison, thus making it an amenable design suitable for sub‐threshold operation under PVT‐variations. [ABSTRACT FROM AUTHOR]

Graphene nanoribbon and transition metal dichalcogenide field‐effect transistors (GNRFETs and TMDFETs) have emerged as favorable candidates to replace conventional metal‐oxide‐semiconductor (MOS) transistor in future technologies. Their competence must be proven through the study and evaluation of various circuits, including static random access memories (SRAMs). Therefore, this paper presents a single‐ended 12T (SE12T) SRAM cell designed using GNRFETs and TMDFETs to evaluate their performance. The proposed SE12T cell designed with GNRFETs/TMDFET device improves read static noise margin by 1.95×/3.20× and incurs a penalty of 1.16×/1.14× in read delay compared to the GNRFETs/TMDFET‐based fully differential 8T cell through a read buffer, decoupling the bitline from the storing nodes during the read operation. Furthermore, two transmission gates (TGs) placed inside the cell core cut off the feedback of cross‐coupled inverters pair during the write operation, enhancing write static noise margin by 1.65×/1.71×. These two TGs along with high logic level of virtual ground (VGND) control signal during hold mode reduce leakage power. Existence of a higher number of p‐type MOS (PMOS) devices, the presence of stacked transistors, and being single‐ended bitcell further reduce this metric, nearly 1.48×/1.17× designed with GNRFETs/TMDFET device as compared to FD8T. Furthermore, it is observed from the results that GNRFET‐based designs have better performance than those of their TMDFET counterparts. The proposed cell eliminates write half‐select disturb, and therefore, bit‐interleaving architecture can be applied to reduce multi‐bit errors. [ABSTRACT FROM AUTHOR]

Summary: In advanced technology, static random‐access memory (SRAM) cells used in space are highly sensitive to charge variations caused by high‐energy particle strikes, which cause soft‐error. Therefore, it is imperative for an SRAM to withstand this harsh environment. However, 6T cells are unable to function reliably in such a place. In order to address this, a radiation‐hardened read‐decoupled 12T (RHRD12T) SRAM cell is proposed in this paper. The relative strength of RHRD12T is estimated by comparing it with other contemporary cells such as NS10T, PS10T, RHBD10T, QUATRO12T, QUCCE12T, and RHD12T on various major design metrics. Due to the read‐decoupled nature of RHRD12T, it shows the highest read stability. It also consumes the lowest hold power compared to all other considered cells, except NS10T. Moreover, RHRD12T exhibits the highest write ability due to the use of two extra access transistors and the poor driving ability of the internal nodes. In terms of write delay, RHRD12T shows an improvement of 1.02×/1.06×/1.07×/1.08× over NS10T/RHD12T/PS10T/RHBD10T at VDD = 1 V. Moreover, RHRD12T is capable of tolerating the highest amount of critical charge among all other comparison cells and is the least susceptible to single‐event upsets. All the aforementioned improvements are obtained at the cost of longer read delay. [ABSTRACT FROM AUTHOR]

Summary: A novel SRAM architecture that simultaneously accesses multiple and non‐overlapped memory subregions, located even inside the same memory page, is presented in this work. This new memory architecture is called multi‐field SRAM, and the multiple selection of its subregions—referred to as the memory fields—is succeeded using special designed intra‐encoders, placed as one for every memory field. The block diagram of the typical SRAM model is extended in order to support the addressing of the multi‐field SRAM using a modified crossbar addressing approach. The support of this new memory is based on the automated generation of intra‐encoders that are adjacent to the memory fields. A test circuit, consisting of 16 memory fields, is developed in order to prove the correct operation of this new memory. Each memory storage cell uses an 8T model in order to support the crossbar addressing scheme, which is also presented. Finally, the simulation results of the test circuit are shown, verifying the successful and simultaneous multi‐field access of the memory. [ABSTRACT FROM AUTHOR]

Static random access memory (SRAM) bit cell is a prominent element for portable devices. The popularity of sleek designs and demand for longer battery life has driven memory cell into nanometer domain. This has also bolstered the need for low‐voltage devices. But reduction in operational voltage for cell is limited by process variation. In this work, a single bit line seven‐transistor (7T) SRAM bit cell is reported. The cell is designed for 32‐nm technology node and is functional at 300 mV. The reported cell maintains a 90‐mV hold and read static noise margins (SNMs), while the write margin is 190 mV. The pulse width needed to successfully write into the cell is 30 ns. The performance of proposed 7T cell is compared against different 6T, 7T, 8T, and 10T SRAM bit cells. The hold and read SNMs for proposed 7T are found to be 58.8%, better than single‐ended 6T cell, while the write ability is improved by 71.4%. The leakage current is observed to have decreased by a factor of 14 for Q = 0 (Q being the data storage node) and by factor of 28 for Q = 1, compared to 6T cell. Also, the area footprint of the proposed 7T SRAM cell is 0.442 μm2. [ABSTRACT FROM AUTHOR]

Summary: The conventional 8T SRAM cell with isolated read port is suggested as an alternative to overcome the read‐write conflicts associated with 6T SRAM cell. However, in near threshold and sub‐threshold regions, 8T cell performance is limited by reduced ION/IOFF ratio, deteriorated RBL voltage swing, data dependency, and higher read failures, although the existing SRAM cells address some of these issues but still suffer from degraded performance due to the trade‐off between leakage and read currents. In this paper, a 9T SRAM cell with novel read port is proposed that aims for low and data‐independent leakages, high ION/IOFF ratio, and large RBL voltage swing in near threshold and sub‐threshold regions. The performance of the proposed cell is compared with 7T, 8T, 9T, and 10T cells at 32 nm technology node by simulating a column of 128 cells to demonstrate its versatility over others. The proposed cell shows enhanced ION/IOFF ratio (71.2X), large RBL voltage swing and data‐independent leakages at VDD = 0.3 V in comparison to the conventional 8T SRAM cell. The results at different PVT corners are also captured to validate the impeccable performance of the proposed cell irrespective of operating conditions. [ABSTRACT FROM AUTHOR]

Summary: This paper presents an 11 transistor (SEHF11T) static random access memory (SRAM) cell with high read static noise margin (RSNM) and write static noise margin (WSNM). It eliminates the write half‐select disturb using cross‐point data‐aware write word lines, which can mitigate bit‐interleaving structure to reduce multiple‐bit upset and increase soft‐error immunity. We evaluated and analyzed the effect of process, voltage, and temperature (PVT) variations on various design metrics and compared it with other cells. The SEHF11T performs fast read operation due to its higher read current and slow write operation due to its single‐ended nature. It employs the read decoupling technique to enhance the RSNM. The stacked transistors in the left/right half‐cell increase the RSNM. In addition, the WSNM is improved by eliminating the feedback of cross‐coupled inverters pair during write operation by means of power‐cutoff write‐assist technique. The proposed cell shows 1.11X higher RSNM and 1.37X higher WSNM compared to fully differential 8T (FD8T) cell. The stacked transistors in the cell reduce leakage power dissipation. The SEHF11T consumes 0.47X lower leakage power compared to FD8T at VDD = 0.7 V. Furthermore, it exhibits high reliability against PVT variations in subthreshold region and shows 1.09X narrower spread in leakage power than that of FD8T at VDD = 0.3 V. [ABSTRACT FROM AUTHOR]

Summary: Static random access memory (SRAM)‐based cache memory is an essential part of electronic devices. As the technology node reduces, the power loss and stability has become the major problems. Several SRAM cells had been developed to address the stability and power loss problem. But still, it is a challenge to achieve balance performance among all the parameters of the SRAM cell for sub‐nanometer technology. This paper proposes a novel SRAM cell, which is having comparatively less total, static power loss, less delay, and high stability compared with the conventional cells for 45‐nm complementary metal‐oxide‐semiconductor (CMOS) technology. The total power cost of the proposed 10T cell has been reduced by 90.3%, 85.84%, 51.02%, and 90.9% compared with 6T, N‐controlled (NC), 10T sub, and 10T, respectively. Similarly, the static power cost of the proposed cell has been reduced by 55.17%, 5.72%, ‐41.6%, and 52.9% compared with 6T, NC, 10T‐sub, and 10T, respectively. The proposed cell provides better stability, less delay, and comparable area compared with other considered 10T cells. Finally, the Monte Carlo (MC) simulation and process analysis of SRAM cells validate the efficiency of the proposed 10T cell. [ABSTRACT FROM AUTHOR]

Summary: The proposed 10T SRAM cell design is implemented for different CNTFET parameters like pitch, number of tubes, chirality, dielectric materials, and flatband voltage to analyze its effect on various performance parameters. The channel gate width, average read, and write power increase, but leakage power, read delay, and write delay decrease with the increase in pitch of CNTFET, whereas all these parameters are directly proportional to the number of tubes. Chirality alteration shows inverse effect on threshold voltage, read delay, and write delay although other parameters are directly related to it. The performance parameters are evaluated for various dielectric materials, and HfO2 gives the best results for low power and high‐speed applications. Analysis of flatband voltage on proposed 10T SRAM is performed by keeping flatband voltage constant for n‐CNTFET and varied for p‐CNTFET. Extensive analysis has been done to scrutinize the sharing of powers and delay of 10T SRAM because of variations in supply voltage and temperature. The supply voltage sweeps for a range between 0.6 and 1.2 V, and range of temperature variation is considered from −27 to 127°C. The stability of the proposed SRAM cell is calculated using N‐curve method to find voltage and current information. The CNTFET based 10T SRAM cell depicts that it persists supply voltage and temperature variation significantly superior than CMOS. [ABSTRACT FROM AUTHOR]

Summary: This paper presents a highly stable, low leakage inexact full adder (FA) which is based on top gate carbon nanotube field effect transistors (TG‐CNTFET) for motion detector applications. Inexact arithmetic circuits are highly accepted in low power multimedia applications. Circuit level metrics, ie, average power, propagation delay, power‐delay product (PDP), and leakage power dissipation as well as application level metric such as peak signal to noise ratio (PSNR) are considered to compare the performance of proposed inexact FA. All the simulations are performed using HSPICE tool with Stanford 32‐nm TG‐CNTFET model. The operating frequency used for simulation is 1‐Ghz with 0.9‐V supply voltage. Proposed inexact FA successfully achieve manifold reduction in leakage power as well as consume 89.2% lesser energy as compared with latest existing inexact FA while having other parameters in acceptable range. Simulations using MATLAB show satisfactory image quality and PSNR value for motion detection applications. The effect of variations in voltage and temperature on leakage power is also presented which confirms stability of the proposed circuit. [ABSTRACT FROM AUTHOR]

Summary: In this work, a data‐dependent feedback‐cutting–based bit‐interleaved 12T static random access memory (SRAM) cell is proposed, which enhances the write margin in terms of write trip point (WTP) and write static noise margin (WSNM) by 2.14× and 8.99× whereas read stability in terms of dynamic read noise margin (DRNM) and read static noise margin (RSNM) by 1.06× and 2.6 ×, respectively, for 0.4 V when compared with a conventional 6T SRAM cell. The standby power has also been reduced to 0.93× with an area overhead of 1.49× as that of 6T. Monte Carlo simulation results show that the proposed cell offers a robust write margin when compared with the state‐of‐the‐art memory cells available in the literature. An analytical model of WSNM for 12T operating in subthreshold region is also proposed, which has been verified using the simulation results. Finally, a small SRAM macro along with its independent memory controller has been designed. This work proposes a low‐power 12T SRAM cell with the improved write ability against the PVT variations. The proposed cell employs the read decoupling to improve the read stability and data‐dependent feedback cutting to provide the low‐leakage and improved write ability. The incorporated stacking effect further improves the leakage power. Therefore, the proposed 12T cell may be an attractive choice for today's battery‐operated IoT‐enabled system on chip (SoC) applications. [ABSTRACT FROM AUTHOR]

A novel sub-threshold 9 T Static Random Access Memory (SRAM) cell designed and simulated in 14-nm FinFET technology is proposed in this paper. The proposed 9 T-SRAM cell offers an improved access time in comparison to the 8 T-SRAM cell. Furthermore, an assist circuit is proposed by which the leakage current of the proposed SRAM cell is reduced by 20% when holding '0' and an equal leakage current during hold '1' in comparison to the 8 T-SRAM cell. The proposed circuit improves the access time by 40% in comparison to the 8 T-SRAM cell without any degradation in write and read noise margins, as well. The maximum operating frequency of the proposed SRAM cell is 1.53 MHz at VDD = 270 mV. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

In this paper, we present our decoupled differential read (DDR) port and bitline (BL) pre-charging scheme. The proposed scheme allows the charge sharing between bitlines during the read operation. DDR port isolates the internal nodes, thus improves the read static noise margin and allows the subthreshold operation. BLs are not pre-charged to full VDD. Read port is designed such that for the read '1' operation, BL shares its charge with BLB, and for read '0' operation, BL is charged toward VDD and BLB is discharged to the ground. The proposed non-VDD BL pre-charging and the charge-sharing mechanism provide substantial read power savings. Virtual power rail is used to suppress the BL leakages. A dynamic voltage level shifting pre-amplifier is used that shifts both BLs to the middle voltage and amplifies the voltage difference. Single-ended write driver is also presented that only conditionally charges the write BL. The proposed 10-transistor static random access memory cell using DDR provides more than 2 times read static noise margin, ~72% read power savings, and ~40% write power savings compared with the conventional six-transistor static random access memory. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]