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In this research paper, a miniaturized vertically polarized dual band antenna with its 2x2 MIMO configuration is proposed for 5G communication. The single antenna consists of an off-centered fed, concave-shaped patch surrounded by two mirror-image C-shaped strips. It works as a millimeter wave radiator for 28/38 GHz bands which provide the transmission at ultra-high speed with a gain of 7.46 dBi and 8.56 dBi and an efficiency of 77% and 91% at both frequency bands respectively. The antenna offers a small-scale size of 10 x 10 x 0.254 mm3 and the close compatibility of simulated and measured results shows the practical feasibility of the fabricated prototype for 5G handheld devices. It can be used for device to device communication at 28 GHz and 38 GHz can be used for 5G cellular communications with higher speed, connectivity and low latency. Apart from that an electrical equivalent circuit of the antenna based on its physical structure is designed using AWR software and its results are included and compared with the CST results. The low specific absorption value of 1.05/0.288W/kg at 28/38GHz and the appropriate results of various parameters for MIMO design confirm its relevance for the 5G MIMO applications. [ABSTRACT FROM AUTHOR]

This paper presents a low power and high speed two hybrid 1-bit full adder cells employing both pass transistor and transmission gate logics. These designs aim to minimise power dissipation and reduce transistor count while at the same time reducing the propagation delay. The proposed full adder circuits utilise 16 and 14 transistors to achieve a compact circuit design. For 1.2 V supply voltage at 0.18-μm CMOS technology, the power consumption is 4.266 μW was found to be extremely low with lower propagation delay 214.65 ps and power-delay product (PDP) of 0.9156 fJ by the deliberate use of CMOS inverters and strong transmission gates. The results of the simulation illustrate the superiority of the newly designed 1-bit adder circuits against the reported conservative adder structures in terms of power, delay, power delay product (PDP) and a transistor count. The implementation of 8-bit ripple carry adder in view of proposed full adders are finally verified and was observed to be working efficiently with only 1.411 ns delay. The performance of the proposed circuits was examined using Mentor Graphics Schematic Composer at 1.2 V single ended supply voltage and the model parameters of a TSMC 0.18-μm CMOS. [ABSTRACT FROM AUTHOR]

Current repetitive control strategy for a 4-leg APF is usually of a poor speed in responding to the drastic changes in load harmonic profile. In this paper, a dual closed-loop current controller composed of a repetitive control-based outer loop and a PI-based inner loop is proposed to improve the performance of a 4-leg APF, with a focus on response speed and harmonic current compensation gain. The principle of the dual loop controller is explained in detail, and the stability of the system is analysed thoroughly. To further decrease the inherent time delay associated with the PWM strategy, a zero-sequence-voltage-based PWM strategy is proposed to solve the complexity in the implementation of 3D-SVPWM methods. By formulating the relationship between the duty ratio of the neutral leg control pulse and the zero-sequence-component of the reference voltages, the duty ratios of the other three legs can be calculated conveniently. The simulation and lab experiment results are provided to verify the correctness and effectiveness of the proposed dual closed-loop current controller and the zero-sequence-voltage-based PWM strategy. [ABSTRACT FROM AUTHOR]

This paper examines the closed-loop characteristics of the basic Current-Feedback Operational Amplifier (CFOA), and in particular, the dynamic response. Additionally, it also examines the design and advantages of the CFOA regarding its ability to provide a significantly constant closed-loop bandwidth for closed-loop voltage gain. Secondly, the almost limitless slew–rate provided by the class AB input stage that makes it superior to the voltage-mode operational amplifier (VOA) counterpart. Additionally, this paper also concerns the definitions and measurements of the terminal parameters of the CFOA, regarded as a ‘black box’. It does not deal with the way that these parameters are related to the properties of the active passive and active components of a particular circuit configuration. Simulation is used in terminal parameter determination: this brings with it the facility of using test conditions that would not normally prevail in a laboratory test on silicon implementations of the CFOAs. Thus, we can apply 1mA and 1mV test signals from, respectively, infinite and zero source impedances that range in frequency from d.c to some tens of GHz. Also, we assume the existence of resistors with identical Ohmic value and very high value ideal capacitors. Where appropriate, practical test methods are referred to physical laboratory prototypes. [ABSTRACT FROM AUTHOR]

The test path of solder joint intermittent connection faults under direct-current stimulus is examined in this paper. According to the physical structure of the circuit, a network model is established first. A network node is utilised to represent the test node. The path edge refers to the number of intermittent connection faults in the path. Then, the selection criteria of the test path based on the node degree index are proposed and the solder joint intermittent connection faults are covered using fewer test paths. Finally, three circuits are selected to verify the method. To test if the intermittent fault is covered by the test paths, the intermittent fault is simulated by a switch. The results show that the proposed method can detect the solder joint intermittent connection fault using fewer test paths. Additionally, the number of detection steps is greatly reduced without compromising fault coverage. [ABSTRACT FROM AUTHOR]

This paper deals with the design of a 6-ternary-digit (6-trit) analogue-to-ternary converter (ATC) by employing a 2-trit simultaneous ATC. The circuit used throughout the design is of the Complementary Metal Oxide Semiconductor (C-MOS) type. [ABSTRACT FROM AUTHOR]

A new open circuit step cavity resonator for continuous and contactless monitoring of sheet moisture content is proposed. The return loss as well as the perturbation in the resonant frequency of the resonator due to variations in the moisture content of sample paper passing through the cavity are monitored in real time by terminal devices and interpreted to display the paper moisture content in digital or analog form. [ABSTRACT FROM AUTHOR]

This paper presents the design, fabrication and tested results of an analogue-to-digital converter (ADC) using linear relationship ratio of comparator and resolution. An original N-bit flash architecture uses 2N−1 comparators (N = resolution), while the proposed architecture uses only N comparators for N-bit making it a linear relationship design. This paper also deals with the design of sample and hold circuit that utilises clock bootstrapping technique which allows sampling at peak voltages and helps in minimising charge injection errors, attaining 125 µV for the proposed design. The proof of concept of 4-bit prototype ADC using 1P−2M is fabricated using AMIS 500 nm CMOS C5X technology and the experimental results at a sampling rate of 800 MS/s reveal an effective no. of bit of 3.34 bits, signal-to-noise ratio of 24.44 dB and differential non-linearity and integral non-linearity of 0.42 and 0.40, respectively. The converter consumes 7 mW power when operated on 2.5 V supply and occupies 0.014 mm2chip area. [ABSTRACT FROM AUTHOR]

This paper proposes two designs for current-mode square wave generators based on a current-differencing transconductance amplifier (CDTA). Both the proposed circuits are compact and employ a single CDTA with only two external passive components. The first circuit has a fixed duty-cycle topology and can generate a symmetrical square wave with variable frequency. The second circuit has a variable duty-cycle design and can operate in a current-controlled dual duty-cycle mode with a single-circuit topology. The proposed generators allow independent control of the operating frequency, output amplitude, and duty cycle by tuning diverse circuit parameters. This paper discusses several previous designs for square wave generators and presents the circuit principles, related governing formulas, and nonideal problems for the proposed circuits. In addition, computer simulations and experimental results, which are consistent with those of the theoretical analyses and confirm the feasibility of the new generators, are presented. [ABSTRACT FROM AUTHOR]

This paper presents dynamic positive feedback source-coupled logic (D-PFSCL) style which is derived from positive feedback source-coupled logic (PFSCL). The proposed logic style uses dynamic current source in contrast to constant current source of PFSCL to attain lower power consumption. Two techniques for D-PFSCL style-based multistage applications are suggested. Several D-PFSCL gates are simulated and compared with the respective PFSCL counterparts through SPICE simulations by using Taiwan semiconductor manufacturing company 0.18 µm CMOS technology parameters. A maximum power reduction of 84% is achieved for D-PFSCL gates. The effect of process variation on the power consumption of the D-PFSCL gates shows a maximum variation factor of 1.5 between the best and the worst cases. [ABSTRACT FROM PUBLISHER]

The idea of including non-uniform temperature distribution into power semiconductor device models is not new, as accurate electro-thermal simulations are required for designing compact power electronic systems (as integrated circuits or multi-chip modules). Electro-thermal simulations of a PIN-diode based on the finite-element method, show a non-uniform temperature distribution inside the device during switching transients. Hence the implicit assumption of a uniform temperature distribution when coupling an analytical electrical model and a thermal model yields inaccurate electro-thermal behaviour of the PIN-diode so far. If literature reports procedures regarding complex thermal network modelling, few papers address the problem of mixing adequately electrical and thermal issues. Instead of using a one-dimensional finite difference or element method, the bond graphs and the hydrodynamic method are used to build a 1D electro-thermal model of the PIN-diode. The paper focuses on electrical issues and the proper expression and localization of power losses to feed the thermal network model. The results by this original technique are compared with those given by a commercial finite-element simulator. The results are similar but the computation effort attached to the proposed technique is a fraction of that required by finite-element simulators. Moreover the proposed technique may be applied easily to other power semiconductor devices. [ABSTRACT FROM AUTHOR]

In this paper, two types of power management circuits for self-powered systems based on micro-scale solar energy harvesting are proposed. First, if a solar cell outputs a very low voltage, less than 0.5 V, as in miniature solar cells or monolithic integrated solar cells, such that it cannot directly power the load, a voltage booster is employed to step up the solar cell’s output voltage, and then a power management unit (PMU) delivers the boosted voltage to the load. Second, if the output voltage of a solar cell is enough to drive the load, the PMU directly supplies the load with solar energy. The proposed power management systems are designed and fabricated in a 0.18-μm complementary metal–oxide–semiconductor process, and their performances are compared and analysed through measurements. [ABSTRACT FROM PUBLISHER]

In this paper we propose a novel idea for the synthesis of active circuits. We deal with the use of unity gain cells (voltage followers, voltage inverters, current followers, current inverters) for the design of simulated grounded inductors, multifunction filters and oscillators. The starting point of the proposed idea is the operation on the signal-flow graphs for such synthesis. We show that, thanks to the proposed technique, a wide number of active networks can be synthesised where all used passive components are grounded. [ABSTRACT FROM PUBLISHER]

This paper describes the characteristics of a new 10T structure for SRAM cell that works quite well in the sub-threshold region. This new architecture has good characteristics in write and read delay and energy compared with other new structures. This new 10T topology improves read static noise margin (SNM) and write operation speed with respect to other topologies in the same or even lower power consumption. The new topology has at least 13% lower power consumption compared with the best of recent architectures. Its write characteristics also are similar to those of 6T-SRAM, which has improved write delay and energy. The new 10T SRAM cell also consumes lower power compared with other cells. The stacking is used to suppress the standby leakage through the read path. The simulations were performed using HSPICE 2011 in a 16 nm bulk CMOS Berkeley predictive technology model (BPTM). [ABSTRACT FROM PUBLISHER]

This paper proposes a circuit configuration for realizing current-mode lowpass and bandpass filters using the operational amplifier (op.-amp.) pole. The circuit simultaneously realizes lowpass and bandpass transfer functions using an op.amp., three resistors and a capacitor. The effects of the parastic poles (i.e. second and third poles) of the op.-amp. on the gain of a lowpass filter are also presented. Since the circuit uses the op.-amp. pole, it is suitable for high frequency operation. This paper proposes a circuit configuration for realizing current-mode lowpass and bandpass filters using the operational amplifier (op.-amp.) pole. The circuit simultaneously realizes lowpass and bandpass transfer functions using an op.amp., three resistors and a capacitor. The effects of the parastic poles (i.e. second and third poles) of the op.-amp. on the gain of a lowpass filter are also presented. Since the circuit uses the op.-amp. pole, it is suitable for high frequency operation. [ABSTRACT FROM AUTHOR]

Voltage-controlled oscillator (VCO) significantly influences power and performance in many analog and digital applications. In this era of portable electronics, power consumption has emerged as an important design metric. Intended subthreshold circuits have proven their ability to satisfy this demand of ultra low-power consumption of a multitude of applications such as RFID, microsensors, etc. Double-gate Fin-FET technology is a promising alternative to the CMOS technology for the subthreshold circuits because of its enhanced gate control, improved performance, scalability, and robustness. Therefore, this paper investigates the viability of DG FinFET Current Starved Voltage Controlled Oscillator (CSVCO) in the subthreshold regime. The results indicate the superior performance of DG FinFET-based CSVCO in regard to speed, PDP, EDP, and variability as compared to CMOS-based CSVCO. Seven different CSVCO configurations, viz.. SG, IG, hybrid, hybrid reverse, pignsg, psgnig and MIGFET, designed using different configurations of DG FinFET, are simulated using 32 nm FinFET Predictive Technology Model (PTM) in HSPICE at 150 mv power supply. The proposed pignsg CSVCO shows better results in terms of frequency obtained versus power expended giving least PDP of 1.25E-16J and better immunity to supply voltage and process variations compared to all other CSVCO configurations. [ABSTRACT FROM AUTHOR]

A compact all-digital phase-locked loop (C-ADPLL) based on symmetrical binary frequency searching (BFS) with the same circuit is presented in this paper. The minimising relative frequency variation error Δη(MFE) rule is derived as guidance of design and is used to weigh the accuracy of the digitally controlled oscillator (DCO) clock frequency. The symmetrical BFS is used in the coarse-tuning process and the fine-tuning process of DCO clock frequency to achieve the minimum Δηof the locked DCO clock, which simplifies the circuit architecture and saves the die area. The C-ADPLL is implemented in a 0.13 μm one-poly-eight-metal (1P8M) CMOS process and the on-chip area is only 0.043 mm2, which is much smaller. The measurement results show that the peak-to-peak (Pk-Pk) jitter and the root-mean-square jitter of the DCO clock frequency are 270 ps at 72.3 MHz and 42 ps at 79.4 MHz, respectively, while the power consumption of the proposed ADPLL is only 2.7 mW (at 115.8 MHz) with a 1.2 V power supply. The measured Δηis not more than 1.14%. Compared with other ADPLLs, the proposed C-ADPLL has simpler architecture, smaller size and lower Pk-Pk jitter. [ABSTRACT FROM AUTHOR]

Leakage current increment is a critical challenge in short channel transistors. In this paper, a new high current performance is presented that not only reduces leakage current but also improves the on-current. The key idea in this work is to modify the doping density with inverted-V shape (IVS) in the vertical direction of the channel. By employing IVS doping density, short channel effects such as drain-induced barrier lowering and threshold voltage roll-off improve and the leakage current significantly reduces compared conventional uniform doping double gate MOSFETs. In this paper, by Conduction band energy modification, in weak inversion regime, high potential height is built that carriers cannot inject in to the channel and reduces leakage current. Furthermore, in strong inversion regime, built-in electric field, leads to better channel carriers’ acceleration and transportation which make on-current improvement. So, the high on–off current ratio (Ion/Ioff) is expected. [ABSTRACT FROM AUTHOR]

In this paper, the modelling, analysis and the power electronics simulator (PSIM) simulations of the fractional order Buck–Boost converter operating in continuous conduction mode (CCM) operation are investigated. Based on the three-terminal switch device method, the average circuit model of the fractional order Buck–Boost converter is established, and the corresponding DC equivalent circuit model and AC small signal equivalent circuit model are presented. And then, the equilibrium point and the transfer functions are derived. It is found that the equilibrium point is not influenced by the inductor’s or the capacitor’s order, but both these orders are included in the derived transfer functions. Finally, the comparisons between the theoretical analysis and the PSIM simulations are given for confirmation. [ABSTRACT FROM AUTHOR]

In this paper, we propose a systematic design methodology in the category of hybrid-CMOS logic style. A huge library of circuits appropriate for low-power and high-speed applications can be obtained by employing the proposed design methodology. The methodology is before used for designing XOR/XNOR and demonstrates the excellence of the new design features. The question of whether the method can be taken advantage to design the function of Carry and its complement (Carry and InverseCarry), as the third important module of a full adder, and what to extend the answer contributes to move towards the general systematic design. All the presented designs as before have high driving capability, balanced full-swing outputs with less glitches and small number of transistors. Also these only consist of one pass-transistor in the critical path, which causes low propagation delay and high drivability. As known, hybrid-CMOS full adders can be divided into three modules, e.g., SUM, Carry and XOR. Optimising these modules has reduced power consumption, delay and the number of transistors of full adders. Therefore by embedding the balanced full-swing circuits in carry module, it can be expected that 11 new full adder circuits will possess high performance. Simulation results show that the proposed circuits exhibit better performances compared to previously suggested circuits in the proposed realistic test bench. These circuits, outperform their counterparts, are showing 24–126% improvement in the power-delay product (PDP) and 57–82% improvement in the area. All simulations have been performed with TSMC 0.13-μm technology in new full adder test bench, using HSPISE to achieve the minimum PDP. [ABSTRACT FROM AUTHOR]

In this paper, a new circuit for simulating a mutually coupled circuit is presented. The circuit employs four second-generation current conveyors (CCIIs) as active elements, together with five resistors and two grounded capacitors as passive elements. The values of a primary self-inductance, a secondary self-inductance and a mutual inductance can be chosen arbitrarily. As an application, a double-tuned circuit is simulated using the proposed circuit to confirm its validity. [ABSTRACT FROM AUTHOR]

Classically in the transmission line matrix (TLM) method, the non-existence of a simple and straightforward circuital description of Maxwell equations has only been associated with three-dimensional (3D) nodes describing general phenomena. On the contrary, except for some specific works available in the literature, a direct and simple transmission line circuit is usually employed for describing the full node. This single circuit allows derivation of the scattering matrix and other quantities for nodes in two-dimensional (2D) situations by simply using transmission and reflection coefficients for this circuit. The non-existence of such a simple circuital representation also for general 2D and even for one-dimensional (1D) TLM nodes is considered in this paper. As with the 3D cases, the use of coupled transmission line circuits is required in general 2D and 1D cases, instead. Therefore, except for some particular situations, the classical transmission and reflection coefficients of a single transmission line circuit are not valid for obtaining the scattering matrix or other quantities associated with these 2D nodes. [ABSTRACT FROM AUTHOR]

In this paper we propose an active circuit consisting of two capacitive double-layer uniformly distributed RC lines and an operational amplifier, and present conditions under which the circuit works as the low-pass filter. Furthermore, we present a method for designing the low-pass filter and give a design example where simulation results are included. [ABSTRACT FROM AUTHOR]

This paper presents a novel circuit design technique to reduce the power dissipation in sequential circuits by using T flip-flops. The unwanted triggering action of the master clock to flip-flops can be isolated during T = 0. An example design of a decimal counter demonstrates the large power saving and improved performance of the resulting circuit. [ABSTRACT FROM AUTHOR]

This paper presents an alternative implementation of a chopper-modulated current-mode instrumentation amplifier. The structure provides very low-offset voltage at the output due to chopper modulation and residual offset removal path. The residual offset removal path is based on low-pass filtering using grounded capacitances which provides compact design structure compared to various chopper-modulated instrumentation amplifier designs. Rail-to-rail input common-mode range is possible due to transmission gate-based input chopper switching scheme. The design is made using a 0.35-µm CMOS process with ±1.65 V supply voltage. The area of the amplifier is 234µm × 344 µm, including all the filtering elements. The proposed circuit with residual offset removal path provides less than 1 µV input referred offset voltage. The advantage of the proposed instrumentation amplifier is its large bandwidth, simple design scheme and compact area compared to chopper-modulated voltage mode amplifiers. [ABSTRACT FROM AUTHOR]

The main objective of this paper is to present a direct current to direct current topology with high circuit efficiency. In this studied circuit, two full-bridge circuits and a half-bridge circuit connected in parallel are introduced to achieve the advantages of low switching loss, less primary current, low conduction loss and low filter size compared to the traditional parallel full-bridge converters. The circuit diagram, operation principles, steady-state analysis and experiments are provided to demonstrate the effectiveness of the studied topology. Finally, a 1.44-kW laboratory prototype is constructed to verify the validity of the theoretical analysis. Experimental results show that highest efficiency of 95.3% can be achieved. [ABSTRACT FROM AUTHOR]

This paper presents a novel access-in-turn test architecture (AIT-TA) for testing of very large scale integrated (VLSI) designs. In the proposed scheme, each scan cell in a chain receives test data from shift-in line in turn while pushing its test response to the shift-out line. It solves the power problem of conventional scan architecture to a great extent and suppresses significantly the switching activity during shift and capture operation with acceptable hardware overhead. Thus, it can help to implement the test at much higher operation frequencies resulting shorter test application time. The proposed test approach enhances the architecture of conventional scan flip-flops and backward compatible with existing test pattern generation and simulation techniques. Experimental results obtained for some larger ISCAS’89 and ITC’99 benchmark circuits illustrate effectiveness of the proposed low-power test application scheme. [ABSTRACT FROM PUBLISHER]

In this paper, a coplanar electromagnetic bandgap (EBG) structure is presented to realise with L-bridge unit cell on the power plane that is combined isolation slots with straight/meander-bridge on the ground plane. The proposed structure with meander-bridge on the ground plane possesses an ultra-wide band gap from 0.22 GHz to 20 GHz with isolation below −30 dB, which is remarkable better than traditional EBG. The lumped equivalent-circuit model for the structure is presented and analysed to explain the mechanism of the improvement of noise suppression. The cut-off frequency for the proposed structure is obtained by theoretical analysis. It is shown that the increase of equivalent inductance of the bridge influences the cut-off frequency. The meander-bridge on the ground plane is adopted to broaden the stopband and significantly enhance the suppression depth. The validity of the presented structure is verified by the simulation compared to the measurement. [ABSTRACT FROM PUBLISHER]

To overcome the problem of the diode reverse recovery in a high frequency switching IGBT inverter, a new gate drive scheme with high reliability is proposed in this paper. Using this circuit, the reverse recovery current can be significantly reduced and a faster switching time with lower turn-on switching loss can be achieved for a hard switching inverter. Comparisons of the proposed driver with a conventional one are given. The operation and characteristics of the proposed circuit are investigated and its usefulness is verified through experiments. [ABSTRACT FROM AUTHOR]

Instrumentation amplifier circuits using operational transconductance amplifiers (OTAs) as active circuit elements are proposed in this paper. Two new instrumentation amplifier circuits have been described and experimentally verified, where the first circuit comprises four OTAs and five resistors and the second circuit comprises two OTAs and three resistors. [ABSTRACT FROM AUTHOR]

In this paper, a new lumped element latchup model which includes two extra bipolar transistors is proposed. The divergence between the results of the conventional and the proposed model is explained in terms of the circuit parameters. The output behaviour of CMOS latchup and the output latchup mode are discussed in connection with the proposed model and the predictions of the model are compared to the results of the conventional model using SPICE. [ABSTRACT FROM AUTHOR]

Circuits for realizing serial quaternary-to-analogue converters (QACs) are proposed in this paper. Three techniques are presented based on Shannon-Rack decoder, sample/hold serial digital-to-analogue converter and cyclic digital-to-analogue converter. Circuits for the generation of control signals and the multiplexer required in the realization of the QACs are also described. A comparison of the three methods is made. [ABSTRACT FROM AUTHOR]

This paper describes a simple circuit for dynamic improvement of power factor of a single phase AC voltage controller, based on FC-TCR technique. The step response of the circuit is quite adequate for many industrial applications. Improvement in power factor is achieved by compensating the fundamental component of the lagging VAr of the thyristor-controlled inductive load. Further improvement in power factor is suggested and the scheme may easily be extended for three phase circuit. [ABSTRACT FROM AUTHOR]

The paper deals with a DC drive system in which a separately excited DC motor is supplied from a three-phase semi-converter circuit. During the operation of the system there are well-defined time intervals initiated and terminated by the switching action of thyristors and diodes. Circuit operation during each interval is represented by a set of linear differential equations. The paper presents closed-form solutions for the equations of each interval. The method is general and obtains the solution for either continuous or non-continuous conduction modes of operation. It predicts the behaviour of the system for both transient and steady-state conditions. The results show good agreement with experimental values. [ABSTRACT FROM AUTHOR]

This paper deals with the voltage control of three-phase circuits using inverse-parallel thyristor-diode (thyrode) pairs. A simple and direct method is introduced to determine the firing and extinction angles of the thyristors for the assumed load power factors. To verify the method of analysis, waveforms of load current and voltage are compared with oscillograms obtained experimentally. The circuit is used to control the speed of an induction motor and torque-speed characteristics are presented with the firing angle as a parameter, Motor current and voltage waveforms are also recorded. [ABSTRACT FROM AUTHOR]

This paper deals with the design anti implementation of a hybrid processor. This is useful for processing analogue signals in such a way that the digital output is indicative of the function required. The system described uses four variables. It performs different types of arithmetical operations such as multiplication, division, squaring and analogue-to-digital conversion. [ABSTRACT FROM AUTHOR]

Easily testable functions have been explored in this paper. A method for the reduction of test schedule by the augmentation of the number of input variables has been suggested.
A problem of practical importance in fault detection is the mechanization of the process of finding the minimal test set. Any Boolean function may be expressed as the sum of product or the product of sum form and consequently can be realized by two-level logical gating. The faults considered here are static faults and usually arise from broken interconnections and burnt-out inputs and gates, the affected logic lines thus being permanently stuck at logical 1 or logical 0. Kohavi and Spires (1971) have already presented the tabular approach for detection of such faults at the inputs of two-level networks realizing arbitrary functions by the minimum possible number of tests. This paper presents the exploration of easily testable functions and a method for the reduction of test schedule by the augmentation of the number of input variables, which is basically an extension of the tabular method of Kohavi and Spires (1971). [ABSTRACT FROM AUTHOR]

A miniature high-efficiency fully digital adaptive voltage scaling (AVS) buck converter is proposed in this paper. The pulse skip modulation with flexible duty cycle (FD-PSM) is used in the AVS controller, which simplifies the circuit architecture (<170 gates) and greatly saves the die area and the power consumption. The converter is implemented in a 0.13-μm one-poly-eight-metal (1P8 M) complementary metal oxide semiconductor process and the active on-chip area of the controller is only 0.003 mm2, which is much smaller. The measurement results show that when the operating frequency of the digital load scales dynamically from 25.6 MHz to 112.6 MHz, the supply voltage of which can be scaled adaptively from 0.84 V to 1.95 V. The controller dissipates only 17.2 μW, while the supply voltage of the load is 1 V and the operating frequency is 40 MHz. [ABSTRACT FROM AUTHOR]

This paper describes a versatile composite amplifier in which a current feedback amplifier (CFA) drives an operational amplifier (OPA). In the conventional OPA–CFA composite amplifier, an OPA drives a CFA resulting in a composite structure that combines the DC input stability of the OPA and the high speed capability of the CFA. The proposed composite configuration combines different features of the CFA and OPA, specifically the constant bandwidth property of the CFA and the high power and high current output capacity of the OPA. The new circuit is easily implemented in the standard inverting and non-inverting configurations using commercially available devices, and the accuracy and constant bandwidth features were experimentally verified. Local feedback around the associated CFA ensures that the proposed composite amplifier possesses a higher level of bandwidth constancy than a single CFA. [ABSTRACT FROM AUTHOR]

In this paper, novel voltage-mode (VM) n-channel metal-oxide semiconductor (NMOS) transistor-based analogue adder and subtractor circuits, which, respectively, performV1+V2andV1−V2operations, are presented. The most important feature of the proposed circuits is their extremely simple structures containing only six NMOS transistors. Further, the presented adder and subtractor circuits have high input and low output impedances, resulting in easy cascadability. The post-layout simulations of the proposed circuits have been executed using TSMC 0.25 µm process parameters with ±1.25 V. The area of the suggested circuits is approximately 30 × 13 µm2. Moreover, the topology of a generalised mutator, a versatile 4-port built with an adder and a subtractor, which acts as an ordinary mutator when properly reduced to a 2-port, is offered. A table for simulating lossless inductance, memristor, meminductor, memcapacitor and other elements under suitable termination of the 4-port is given, and three of these elements’ simulations with SPICE are also presented. [ABSTRACT FROM AUTHOR]

The squaring operation is important in many applications in signal processing, cryptography etc. In general, squaring circuits reported in the literature use fast multipliers. A novel idea of a squaring circuit without using multipliers is proposed in this paper. Ancient Indian method used for squaring decimal numbers is extended here for binary numbers. The key to our success is that no multiplier is used. Instead, one squaring circuit is used. The hardware architecture of the proposed squaring circuit is presented. The design is coded in VHDL and synthesised and simulated in Xilinx ISE Design Suite 10.1 (Xilinx Inc., San Jose, CA, USA). It is implemented in Xilinx Vertex 4vls15sf363-12 device (Xilinx Inc.). The results in terms of time delay and area is compared with both modified Booth’s algorithm and squaring circuit using Vedic multipliers. Our proposed squaring circuit seems to have better performance in terms of both speed and area. [ABSTRACT FROM AUTHOR]

Complementary metal oxide semiconductor (CMOS) technology scaling for improving speed and functionality turns leakage power one of the major concerns for nanoscale circuits design. The minimization of leakage power is a rising challenge for the design of the existing and future nanoscale CMOS circuits. This paper presents a novel, input-dependent, transistor-level, low leakage and reliable INput DEPendent (INDEP) approach for nanoscale CMOS circuits. INDEP approach is based on Boolean logic calculations for the input signals of the extra inserted transistors within the logic circuit. The gate terminals of extra inserted transistors depend on the primary input combinations of the logic circuits. The appropriate selection of input gate voltages of INDEP transistors are reducing the leakage current efficiently along with rail to rail output voltage swing. The important characteristic of INDEP approach is that it works well in both active as well as standby modes of the circuits. This approach overcomes the limitations created by the prevalent current leakage reduction techniques. The simulation results indicate that INDEP approach mitigates 41.6% and 35% leakage power for 1-bit full adder and ISCAS-85 c17 benchmark circuit, respectively, at 32 nm bulk CMOS technology node. [ABSTRACT FROM AUTHOR]

This paper describes a highly linear low noise amplifier (LNA) for K-band applications in a 0.18 µm RF CMOS technology. The core of the circuit is a two-stage LNA consisting of a common-source and a cascode stage. By adopting an improved post-linearisation technique at the common-source transistor of the second stage, more than 5 dB improvement in IIP3 is achieved with a minor effect on noise figure and input matching. The circuit level analysis and simulation results are presented to demonstrate the effectiveness of the proposed technique. [ABSTRACT FROM AUTHOR]

In this paper, a new circuit to synthesise negative capacitor by using MOSFETs is proposed. This circuit has been analysed exactly. Output admittance, value of negative capacitor and frequency limitations of proposed architecture, has been investigated accurately and related equations are obtained theoretically in presence of all parasitic capacitors. Also, this new negative capacitor structure is simulated in TSMC 0.13 µm CMOS Technology. Simulation results confirm the analytical predictions. By variation ofgmandCXin proposed architecture, negative capacitor can be obtained in higher frequencies up to 15 GHz. [ABSTRACT FROM PUBLISHER]

In this paper, an all-digital phase-locked loop (PLL) with adaptively controlled up/down counter serves as the loop filter is presented, and it is implemented on a field-programmable gate array. The detailed circuit of the adaptive up/down counter implementing the adaptive search algorithm is also given, in which the search step for frequency acquisition is adaptively scaled down in half until it is reduced to zero. The phase jitter of the proposed PLL can be lowered, yet keeping with fast lock-in time. Thus, the dilemma between the low phase jitter and fast lock-in time of the traditional PLL can be resolved. Simulation results and circuit implementation show that the locked count, phase jitter and lock-in time of the proposed PLL are consistent with the theoretical predictions. [ABSTRACT FROM PUBLISHER]

In this paper, a wide tuning-range CMOS voltage-controlled oscillator (VCO) with high output power using an active inductor circuit is presented. In this VCO design, the coarse frequency is achieved by tuning the integrated active inductor. The circuit has been simulated using a 0.18-µm CMOS fabrication process and presents output frequency range from 100 MHz to 2.5 GHz, resulting in a tuning range of 96%. The phase noise is –85 dBc/Hz at a 1 MHz frequency offset. The output power is from –3 dBm at 2.55 GHz to +14 dBm at 167 MHz. The active inductor power dissipation is 6.5 mW and the total power consumption is 16.27 mW when operating on a 1.8 V supply voltage. By comparing this active inductor architecture VCO with general VCO topology, the result shows that this topology, which employs the proposed active inductor, produces a better performance. [ABSTRACT FROM PUBLISHER]

This paper presents the design and experimental results of a clock generator for high-frequency, continuous-time,converters. The circuit was fabricated in a-V,-nm CMOS technology along with twomodulators intended for the digitisation of UWB signals. The clock generator is based on a PLL frequency synthesiser with a low phase noise LC Voltage-controlled oscillatror (VCO). This kind of oscillator achieves the required low jitter specification with a substantial lower power consumption than a conventional ring VCO. In order to save die area, the VCO was made to operate at four times the desired clock frequency ofMHz, and a compact multi-layer inductor was used. A system clock with a cycle-to-cycle jitter of onlyof its period is obtained. The total circuit area isand the resulting power consumption is. [ABSTRACT FROM AUTHOR]

Transimpedance filter is a filter which realises a transimpedance transfer function. In this paper, the design methods for transimpedance band-pass filter are presented. The circuit topologies and parameter calculation formulas of three bi-quadratic transimpedance band-pass filter topologies with LQ, MQ and HQ are proposed respectively. High order transimpedance filter can be obtained by realising a bi-quadratic transimpedance filter first and then cascaded with voltage mode bi-quads. A high order transimpedance filter design example is given, the simulation and the measured results verify the effectiveness of the proposed transimpedance filter design method. [ABSTRACT FROM AUTHOR]

In this paper, an active-only grounded lossless inductance simulator operating in current-mode is presented. The circuit uses only a current operational amplifier (COA) and an operational transconductance amplifier (OTA). The novelty of the proposed circuit is that it uses a COA instead of a voltage operational amplifier (VOA) to take the wider frequency operation advantage of the current-mode approach. The simulation results obtained through SPICE with 0.5 μm standard CMOS technology verify that the designed circuit can be operated up to 30 MHz, which is much higher than the operation frequency of previously reported inductance simulators utilising VOAs. The inductance value of the presented circuit can be adjusted electronically between 3.9 μH and 37 μH via the biasing current of the OTA. A parallel resonance circuit application is also given validating the operation of the proposed inductance simulator. [ABSTRACT FROM AUTHOR]

In this paper, we propose a method for testing CMOS domino circuits using the transient power supply current. The method is based on monitoring and processing the transient current. We evaluate the effectiveness of this testing method through simulations of various domino circuits of different sizes. Moreover, we propose a normalising technique to mask the process variations effect associated with current testing. Furthermore, we present a test vector generation algorithm for testing large domino circuits, and develop and implement a clustering technique to improve the fault coverage of the test method when used with large circuits. The clustering algorithm divides the circuit into different clusters where each cluster is fed by a different power supply branch. [ABSTRACT FROM AUTHOR]