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We report on the FET properties of 2-decyl-7-phenyl-[1]benzothieno[3,2-b][1]benzothiophene (Ph-BTBT-10) on a HfO2/alicyclic polyimide double-layered gate insulator at an elevated temperature. The patterning of semiconductor and polymeric insulator layers is also discussed using the surface selective deposition of solution onto the wettable region (self-assembled monolayer-coated oxide layer) and unwettable region (bare metal oxide layer) obtained by vacuum ultraviolet light (172 nm) irradiation. A multilayered film of 20–30 nm thick Ph-BTBT-10 and a double-layered gate insulator consisting of 30–40 nm thick alicyclic polyimide on high-k metal oxide films leads to a reduction in the operating voltage and the interfacial trap density at the gate insulator interface. The mobility of the FETs was improved from 0.4 to 2.4 cm2 V−1 s−1 by thermal annealing of Ph-BTBT-10 at 120 °C due to the transition from a monolayer to a bilayer structure and the use of alicyclic polyimide as the polymer gate insulator.

This work illustrates the ample exploitation of ferroelectric through metal-ferroelectric options for nanosheet line tunnel field-effect transistor (NLTFET), for the first time. Here, SiGe and ferroelectric (HZO) are successfully employed to demonstrate the high performance p-NLTFET through simulations. Owing to this, the on-state current (I on = 122.3 μA μm−1) is enormously improved through the reduction of gate-oxide thickness even at low gate bias. In addition, the steep subthreshold swing is effectively minimized to 25.96 mV dec−1 by controlling the off-state current, gate-leakage and trap-assisted-tunneling. Overall, a 2-order boost on the I on is achieved, compared with planar ferroelectric TFETs.

In this study, integrate and fire neuron by using a dual-gate (DG) PN-body tied (PNBT) silicon on insulator field-effect transistor (SOI-FET) was investigated. We found out that the DG PNBT SOI-FET has the integrate and fire function in a single device. The floating body and the positive feedback effect can perform the functions of the capacitor and comparator, respectively. The device can generate a continuous spike and also a single spike signal with the additional reset scheme. The reset action requires a recovery time, which can be controlled by voltage conditions. It has a chance of making a refractory period function. These characteristics mean that it is possible to realize the capacitor-less small footprint neuron circuit with the DG PNBT SOI-FET.

An (AlGa)2O3 back barrier was employed for Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs) with a Si-implanted n-Ga2O3 channel layer. The insertion of the back barrier led to strong confinement of electrons in the channel layer, and a shallower pinch-off characteristic with shifting a threshold gate voltage by +8 V was attained for the MOSFET with the back barrier compared to the conventional one without it. The excellent gate controllability represented by a subthreshold slope of 129 mV/decade was also achieved for the back-barrier MOSFET; whereas it was 337 mV/decade for the non-back-barrier one.

In this research, we propose a method that can significantly improve the linearity of current–voltage characteristics (L–IV) of synapse devices. Considering that analog input data are dependent on the L–IV, synapse devices having non-linear current–voltage characteristics can result in drastic conductance variations during inference operations. It means that the L–IV is one of the key parameters in the synapse device. To improve the L–IV, a triode region of a metal oxide semiconductor field effect transistor (MOSFET) was utilized with a Li-ion-based memristor as a gate voltage divider, which results in gradual channel conductance changes (analog synaptic weights). The channel conductance of the MOSFET can be selectively controlled based on Li-ion intercalation and de-intercalation. A notably improved L–IV and analog synaptic weights were achieved, which enhanced the MNIST data set recognition accuracy from 35.8% to 92.03%.

We investigate the humidity sensing performance and mechanism of few-layer-thick rhenium disulfide (ReS2) field-effect transistors (FETs) under gate bias operation. Consequently, a negative gate bias exhibits the sensor response, exceeding 90% mainly in the low relative humidity (RH) range. Meanwhile, the threshold voltage change was discovered to be a superior sensing parameter to achieve a broad monitoring of RH range with high response and sensitivity. The approach obtained a practical sensitivity of 0.4 V per 1% RH, which exceed a majority of previous studies with the pristine 2D materials. Besides, our devices display reversible adsorption–desorption and long-term stability operations even after a one-month period. This suggests the sensor capacity to function in real-time applications with a short response and recovery times. These outcomes offer support in the development of adaptable tunable humidity sensors based on ReS2 FETs.

This study reposts the fabrication of top-gate molybdenum disulfide (MoS2) field-effect transistor (FET) by the transfer printing of a gate dielectric in conjunction with a poly(vinyl-alcohol) (PVA) coating for carrier doping. The spin-coated PVA film increases the carrier concentration in MoS2, while the back-gate MoS2 FET cannot be turned off. The transferred top-gate structure with the PVA coating makes it possible to turn off the fabricated device without permanent damage to MoS2. The results of this study suggest interesting directions for the research and development of two-dimensional material-based functional devices.

In this paper, we present a compact surface-potential-based drain current model in molybdenum disulfide (MoS2) field-effect transistors (FETs). Considering variable range hopping (VRH) transport via band-tail states in MoS2 transistors, an explicit solution for surface potential has been derived and it provides a good description over different regions of operation by comparisons with numerical data. Based on charge-sheet model (CSM) which applies to drift-diffusion transport, the current expression including contact resistance and velocity saturation effect is developed. Furthermore, the presented model is validated and shows a good agreement with experiment data for MoS2 FETs. Keywords: molybdenum disulfide (MoS2), surface potential, current expression.

The modulus spectra of organic field-effect transistors (OFETs) with electrode overlap and peripheral regions have been experimentally and theoretically investigated. The complex impedance of regioregular poly(3-hexylthiophene-2,5-diyl) (P3HT) OFETs with electrode overlap and peripheral regions was measured with a frequency response analyzer. The complex modulus was derived from an equivalent circuit of OFETs with overlap and peripheral regions using a four-terminal matrix approach. The modulus spectra of the P3HT OFETs were successfully fitted by those calculated using the expression derived from the equivalent circuit. Three structures were found in the modulus spectra of the P3HT OFETs owing to the dielectric properties of the gate insulator, transport properties of the organic semiconductor, and contact resistance from the low to high frequency ranges. The resistivity of the gate insulators and the field-effect mobility of working OFETs were determined using the values of the circuit components of the equivalent circuit obtained by fitting.

We investigated the effects of the post-oxidation annealing in H2O (wet-POA) with various conditions after dry oxidation for p-type 4H-SiC (0001) metal-oxide-semiconductor (MOS) capacitors and 4H-SiC (0001) p-channel MOS field effect transistors (PMOSFETs). Interface state density, fixed charge density, and slow trap density in near-interface oxide were reduced by the wet-POA with additional growth of only < 1 nm oxide at the interface. With those POAs the improved PMOSFET performance was also demonstrated. The degradation of flatband voltage (VFB) stability, which has been regarded as one of the serious drawbacks of wet oxidation of SiC, was efficiently suppressed by a careful selection of the wet-POA conditions with low O2 partial pressure at high temperature. Even though the reason why the VFB stability is so sensitive to the wet-POA condition is not clarified yet, these results give us a guideline to design an appropriate conditions of wet-POA for SiC PMOSFETs.

We demonstrated post-fin-fabrication annealing (PFA) as a recovery process for suppressing plasma-induced damage (PID) in Ge fin field-effect-transistors (FinFETs) after the Ge fin fabrication. There are two key points in the PFA process. One is an annealing temperature (≥600 °C) higher than the recrystallization temperature of Ge for the curing of PID. The other is that a SiO2 film is capped on the Ge fin to prevent GeO desorption. Furthermore, we investigated the impact of PFA at 600 °C–800 °C on the electrical characteristics of Ge FinFETs. The PFA process improves the subthreshold slope and the on current in Ge n- and p-type FinFETs and reduces the off current. We found that the optimum PFA temperature is 600 °C in this experiment because of the minimum thermal expansion between Ge and SiO2.

Time-domain analog computing with transient states (TACT) approaches have been proposed to realize high performance artificial intelligence (AI) processors, which have over 100 times higher energy efficiency than the latest digital AI processors. Such approaches require analog memory devices that can hold and control very high resistance on the order of giga-ohms to tera-ohms, with nonvolatility and rectification. Memory devices with a field-effect transistor (FET) structure can operate in a subthreshold region to realize such high resistance, and can also rectify the current using FET operation. In this paper, we propose using ferroelectric-gate FETs (FeFETs) as a candidate for such devices. We design crossbar circuit architectures for using them, and show measurement results for device characteristics as analog memory devices with pulse control based on TACT approaches, and evaluation results for weighted-sum calculation operation in proof-of-concept FeFET circuits.

Lower limit of operable voltage for Ferroelectric Field Effect Transistor (FeFET) memories using hafnium oxide based ferroelectric gate dielectrics was estimated using circuit simulations. Assuming realistic array architecture, memory weakening by disturbs and restrictions set by sneak current were taken into account. For modeling ferroelectricity, a continuous Preisach model of hysteresis was used. The results show that the lowest possible operation voltage, not including variability and reliability margin, will be around ±2V. It was found that moderate reduction of remanent polarization is beneficial for lowering both operation voltage and interfacial layer electric field stress.

We developed low-temperature (150 °C) processed top-gate and coplanar metal-semiconductor field-effect transistors (MES-FETs) with a stacked In–Ga–Zn–O (IGZO) channel consisting of a hydrogenated IGZO (IGZO:H) on conventional IGZO (IGZO). The IGZO and IGZO:H films were prepared by Ar+O2 and Ar+O2+H2 sputtering, respectively. By applying IGZO:H on IGZO (IGZO:H/IGZO) stacked channel, On-current of the MES-FET significantly increased while maintaining low off-current. On-off current ratio of 4.2×108, turn-on voltage of -5.9 V and subthreshold swing of 155 mV/decade were achieved. The carrier concentration of the IGZO:H/IGZO stacked film dramatically increased to 1.4×1019 cm-3 by stacking the IGZO:H (4.4×1017 cm-3) film on the IGZO (7.6×1017 cm-3) film. It was suggested that diffused hydrogens from IGZO:H to IGZO enhanced carrier concentration in the IGZO near the IGZO:H/IGZO interface, which acts as a pseud two dimensional electron gas. Therefore, the IGZO:H/IGZO stacked channel plays an important role in improving the performance of the MES-FETs.

We investigated the impact of the mechanical uniaxial strain on the inversion channel mobility of lateral n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) on 4H-SiC(0001). We used custom-designed bend-holders to apply a tensile and compressive stress to the chip after MOSFET fabrication. The behavior of mobility with the two different channel directions and was investigated on the bend directions and with the tensile and compressive stress. We found that the inversion channel mobility effectively increases with the uniaxial compressive stress of the perpendicular configuration which is the drain current flow perpendicular to the bend direction. From the temperature dependence of mobility, we deduced that the enhancement of mobility is attributed to the reduction of the effective mass in 4H-SiC by introduced stress.

InGaAs photo field-effect transistors (PhotoFETs) integrated on a half-inch Si wafer have been demonstrated by means of layer transfer technology. According to the Raman measurement and scanning transmission electron microscopy (STEM), the InGaAs layer was transferred onto the half-inch Si wafer without degradation of crystal quality or introduction of strain. The optical performance of InGaAs photoFETs on Si, operating in shortwave infrared (SWIR) region was also investigated. The photoFETs on Si wafer show a responsivity of ~3 A/W at SWIR of 1550 nm with investigated range of bias. These results demonstrate InGaAs layer transfer technology is suitable for SWIR detectors on CMOS compatible platforms for monolithic integration.

Recently, to avoid forward-voltage degradation of body diodes, which is caused by the expansion of stacking faults due to hole-current conduction through the body diodes, silicon carbide (SiC) Schottky barrier diode (SBD) embedded metal-oxide-semiconductor field effect transistors have been actively studied. However, most studies focus on designs that do not allow hole current to flow when reverse current flows from the source to drain, and there are few reports that mention the contact-formation process or contact reliability. A low-resistance ohmic contact and a highly reliable Schottky contact were formed simultaneously by combining the recrystallization of an N+ heavily implanted region to 3C-SiC, opening of a contact hole by dry etching and formation of a titanium electrode followed by post-annealing. Moreover, gate leakage current can be reduced by improving the crystallinity and morphology near the channel by introducing an extension structure, even if the process for simultaneously forming the ohmic and Schottky contacts is applied to the MOSFETs fabrication process. The developed process minimizes the increase in cell pitch due to the incorporation of the SBD and suppresses the conventional increase in on-resistance to about 10%. Regarding diode characteristics, expansion of the stacking faults could be suppressed by eliminating the hole-current conduction, even in the case of a large current density of 500 A cm−2 at 175 °C.

In this work, a polycrystalline silicon (poly-Si) double-gate metal-oxide-semiconductor field-effect transistor (MOSFET)-based stacked multi-layer (ML) one-transistor dynamic random-access memory (1T-DRAM) for the embedded memory is proposed using technology computer-aided (TCAD) simulation. Although poly-Si has advantages of low-cost fabrication and implementation of three-dimensional (3-D) structure, poly-Si devices suffer from low on-state current (Ion) due to the low mobility and the scattering by the grain boundary (GB) trap. The stacked ML structure is proposed to improve low Ion. As a result of simulation, the ML device obtained a high Ion of 87.92 μA/μm. Owing to the enhancement of Ion, the ML achieved a high SM of 30.44 μA/μm. A retention time (RT) of the proposed ML device in the simulation exhibited 2.94 msec even at a high temperature of 358 K. Moreover, the proposed ML device demonstrates superior reliability in terms of memory operations (RT > 100 μsec) for randomly distributed GBs.

In this work, we demonstrated that the 5-nm-thick HfAlO x negative capacitance transistor (NCFET) with optimized Al doping can achieve a minimum 33 mV dec−1 subthreshold swing (SS), an ultralow I off of 7.44 fA μm−1, and a high I on /I off ratio of 1.9 × 108. The NC switching with sub-60 mV dec−1 SS can be implemented from V DS = 0.2 V to 0.8 V due to an ultralow off-state leakage current. The experimental results reveal that well-controlled Al doping in HfAlO x not only reduces off-state leakage of the transistor, but also improves the ferroelectric NC effect to achieve a sub-60 mV dec−1 switching under a favorably low sub-1 voltage. This scaled HfAlO x NCFET with optimized Al doping and fluorine defect passivation shows the great potential for the application of low power logic devices.

We report on the quick deposition technique of the highly oriented 6, 13-bis (trisopropylsi-lylethynyl) pentacene (TIPS-pentacene) crystalline films from the polystylene (PS)/TIPS-pentacene blend solution onto the oxide dielectric films at an elevated temperature for fabricating organic field-effect transistors (FETs). A vertical phase separation between TIPS-pentacene and PS films on high-k metal oxide films leads to the reduction of operating voltage and the interfacial trap density at the gate insulator interface. The polarized optical microscopy image and in-plane X-ray diffrac-tion analysis suggest the pi-stacking of TIPS-pentacene molecules along the direction parallel to the sweeping direction of meniscus coating. The highly oriented TIPS-pentacene crystalline films were obtained at 0.75-2.0 mm/s at 70 oC which was much faster than room temperature (0.01 mm/s). These effects eventually lead to both the improvement of FET properties and device fabrication processes.

Complex modulus spectra of organic field-effect transistors (OFETs) with electrode overlap regions were investigated both experimentally and theoretically. Complex modulus spectra in a poly(3-hexylthiophene-2,5-diyl) (P3HT) FET were measured using an impedance analyzer. An equivalent-circuit of OFETs with the overlap between gate and source/drain electrodes was proposed to interpret the experimentally-obtained complex modulus spectra. The complex modulus spectra calculated from the equivalent circuit were successfully fitted to the experimentally-obtained spectra of P3HT FETs. It is shown that the dielectric properties of the gate insulator, the field-effect mobility of the organic semiconductor, and the contact resistance are obtained by means of the fitting of the theoretically-obtained modulus spectra to the experimentally-obtained spectra.

We investigate the impacts of channel curvature induced by atomistic surface roughness on electronic-transport properties in monolayer transition-metal dichalcogenide field-effect transistors (FETs) through ab initio calculations. By focusing on the channel current, we demonstrate that the I on current and I on/I off ratio are both significantly suppressed in n-type and p-type MoS2 FETs when increasing the channel curvatures. We also evaluate the performance of CMOS inverters and demonstrate that the channel curvatures can dramatically reduce the inverter performance. These findings point to the fact underlining that surface engineering for channel roughness optimization at the atomic level is strongly required in MoS2-based devices.

4H-SiC n-channel metal oxide semiconductor field effect transistors (NMOSFETs) with a Ba-silicate interface layer were irradiated with gamma-rays up to 850 kGy at room temperature. Above 600 kGy, the field effect mobility increased from 12 to 18 cm2 V−1 s−1. The narrower channel in the NMOSFETs enhanced radiation responses, such as mobility enhancement and threshold voltage shift. These results indicate that the edge of the channel significantly modifies the electrical characteristics.

We have evaluated specific on-state resistance (R on,sp) and switching performance of various GaN power field-effect transistors (FETs) with 600 and 1200 V ratings using analytical calculation and numerical simulation. The normally-off GaN power FET family includes lateral p-GaN gate high electron mobility transistors (HEMTs), lateral metal-oxide-semiconductor (MOS) channel HEMTs, current aperture vertical electron transistors (CAVETs) and vertical U-shaped trench-gate MOS field-effect transistors (UMOSFETs). This study shows the advantages of vertical GaN power FETs over lateral GaN power HEMTs. These advantages include lower R on,sp and smaller switching energy loss, especially at higher blocking voltages (1200 V). At 600 V, lateral P-GaN gate HEMTs are competitive with vertical power FETs. Vertical GaN CAVETs perform better than both lateral HEMTs and vertical UMOSFETs at both voltage ratings, benefiting from its lowest R on*Q G figure-of-merit.

An asymmetric Schottky tunneling source field-effect transistor (STS FET) is a prospective device structure to suppress the short-channel effect. Recently, we succeeded in the fabrication and operation of a Ge-STS n-channel FET with TiN and PtGe asymmetric metal source/drain (S/D) on a bulk Ge substrate. However, the Ge-STS p-channel FET has not been demonstrated yet. In this study, we fabricated an asymmetric metal S/D FET with the same S/D structure on a bulk Ge and a Ge-on-Insulator (GOI) substrate. The GOI was made by using the Smart-CutTM technique. The device fabricated on a bulk Ge did not operate. On the other hand, the fabricated FET on a GOI, which has a taper-shaped TiN/Ge source interface, showed STS p-FET behavior. These results suggest that the carrier injection can be improved by the optimization of the device structure. As an auxiliary effect, conventional metal-oxide-semiconductor (MOS) FET operation was also observed, thanks to GOI introduction. We demonstrated both STS mode and MOSFET mode operation in the same device on GOI.

The effects of post-annealing processes for normally-off GaN metal-oxide semiconductor heterojunction field-effect transistors (MOS-HFETs) with a thin AlN barrier layer are investigated. These annealing processes are post-deposition annealing (PDA) after oxide deposition, post-metallization annealing (PMA) after gate metallization, and positive-bias annealing (PBA) after wafer processes. PMA and PBA are effective in enhancing the drain current density and threshold voltage shift. The most effective method is PBA and the obtained threshold voltage and drain current density are +3.0 V and 0.7 A mm−1, respectively. This is attributed to improvements in interfacial trap states which is confirmed by an investigation of the frequency dependence of capacitance–voltage characteristics.

In this paper, we investigated the effects of the post-deposition annealing (PDA) on the threshold voltage (V th) of AlGaN/GaN MOS heterojunction field-effect transistors with atomic-layer-deposited Al2O3 using H2O vapor or oxygen plasma as the oxidant. By PDA, the V th shifts positively with the V th variations depending on the oxidants. The capacitance–voltage measurements reveal that the V th variation is attributed to the differences in the initial fixed charge density in the Al2O3 or/and the Al2O3/AlGaN for both oxidants.

We have investigated the scaling of top-gate (TG)/bottom-contact (BC) pentacene-based organic field-effect transistor (OFET) with amorphous rubrene (α-rubrene) gate insulator utilizing lift-off processes for source/drain (S/D) and gate patterning. The TG/BC OFETs with the channel length below 10 μm were successfully fabricated. The fabrication yield of 100% was achieved for the OFET with minimum channel length of 2.3 μm by using the Au-7.4%Ge S/D electrodes. The mobility of 5.1 × 10–3 cm2 V−1 s−1 was obtained for the TG/BC OFET with channel length of 2.3 μm. However, it was found that the device characteristics markedly degraded below the channel length of 6.5 μm. This was probably due to the defective region in the pentacene channel formed at the S/D regions with approximately 3 μm width from both sides of the S/D interface. The back-gate OFET with the channel length of 2.4 μm did not show the remarkable degradation. Therefore, the worse interface properties at α-rubrene gate insulator and defective region caused the degradation of scaled pentacene-based TG/BC OFET characteristics.

In this study, we investigated the potential drift and sensitivity in an extended-gate (EG) field-effect-transistor (FET)-based potentiometric sensor with junctionless (JL) and inversion-mode (IM) gate-all-around (GAA) nanowire (NW) FETs. An EG electrode (EGE) coated with Al2O3 via plasma-enhanced atomic-layer deposition exhibited high stability. Both JL and IM GAA NWFETs were prepared in the same batch and exhibited high electrical performance, including a steep subthreshold swing of approximately 63 mV dec−1 and a high ON/OFF current ratio of approximately 3 × 107 at V DS = 0.1 V. However, JL GAA NWFETs exhibited higher drift stability than did IM GAA NWFETs under various working regions over a long period of operation. Furthermore, JL GAA NWFETs with EGEs (JL GAA NWFETs w-EGEs) exhibited the highest sensitivity when operating under the subthreshold region in pH sensing (ΔI/I 0 = ~4410%). The readout sensitivity reached S out = 82%. A JL GAA NWFET w-EGE was also demonstrated as a potentiometric biosensor for streptavidin real-time detection at concentrations of 42 fM to 4.2 nM.

Polarization-doped field effect transistors (PolFETs) were realized with an unintentionally doped Al x Ga1− x N channel layer graded over Al compositions 0.70 ≤ x ≤ 0.85 and ohmic contact formation to the Al0.85Ga0.15N surface. Current density of 24 mA/mm was attained for a modest threshold voltage of −3.95 V owing to the high sheet charge concentration (n s) of 5.4 × 1012 cm−2 and average electron mobility (μ) of 210 cm2 V−1 s−1 for the channel region along with ohmic contacts with a specific contact resistivity of 1.1 mΩ cm2 and a large Schottky barrier height of 3.0 eV for the metal–semiconductor gate. The combination of ultra-wide band gap energy, high μ, and high n s, linear ohmic contacts, and large Schottky barrier for AlGaN PolFETs makes them attractive for both high voltage switches and high power rf devices.

The threshold voltage (V th) fluctuation induced by ion implantation (I/I) in the source and drain extensions (SDEs) of a silicon-on-insulator (SOI) triple-gate (Tri-Gate) fin-type field-effect transistor (FinFET) was analyzed by both three-dimensional (3D) process and device simulations collaboratively. The origin of the V th fluctuation induced by the SDE I/I is basically a variation of a bottleneck barrier height (BBH) due to implanted arsenic (As+) ions. In particular, a very low and broad V th distribution in the saturation region is due to percolative conduction in addition to the BBH variation. Moreover, it is surprisingly found that the V th fluctuation is mostly characterized by the BBH of only a top surface center line of a Si fin of the device. Our collaborative approach by 3D process and device simulations is dispensable for the accurate investigation of variability-tolerant devices. The obtained results are beneficial for the research and development of such future devices.

Stacked gate dielectrics consisting of wide bandgap SiO2 insulators and thin aluminum oxynitride (AlON) interlayers were systematically investigated in order to improve the performance and reliability of AlGaN/GaN metal–oxide–semiconductor (MOS) devices. A significantly reduced gate leakage current compared with that in a single AlON layer was achieved with these structures, while maintaining the superior thermal stability and electrical properties of the oxynitride/AlGaN interface. Consequently, distinct advantages in terms of the reliability of the gate dielectrics, such as an improved immunity against electron injection and an increased dielectric breakdown field, were demonstrated for AlGaN/GaN MOS capacitors with optimized stacked structures having a 3.3-nm-thick AlON interlayer.

An analytical model of surface potential profiles and transfer characteristics for hetero stacked tunnel field-effect transistors (HS-TFETs) is presented for the first time, where hetero stacked materials are composed of two different bandgaps. The bandgap of the underlying layer is smaller than that of the upper layer. Under different device parameters (upper layer thickness, underlying layer thickness, and hetero stacked materials) and temperature, the validity of the model is demonstrated by the agreement of its results with the simulation results. Moreover, the results show that the HS-TFETs can obtain predominant performance with relatively slow changes of subthreshold swing (SS) over a wide drain current range, steep average subthreshold swing, high on-state current, and large on–off state current ratio.

We present a novel methods of fabricating low-temperature (180 °C), solution-processed zinc oxide (ZnO) transistors using a ZnO precursor that is blended with zinc hydroxide [Zn(OH)2] and zinc oxide hydrate (ZnO H2O) in an ammonium solution. By using the proposed method, we successfully improved the electrical performance of the transistor in terms of the mobility (μ), on/off current ratio (I on/I off), sub-threshold swing (SS), and operational stability. Our new approach to forming a ZnO film was systematically compared with previously proposed methods. An atomic forced microscopic (AFM) image and an X-ray photoelectron spectroscopy (XPS) analysis showed that our method increases the ZnO crystallite size with less OH− impurities. Thus, we attribute the improved electrical performance to the better ZnO film formation using the blending methods.