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A self-aligned gate fabrication technique utilizing silicon-on-insulator technology is developed for the fabrication of large uniform arrays of diamond field emitters with self-aligned gate and sharp tip cathode. A uniform array with millions of gated diamond microemitters was reproducibly achieved. The diamond field emitter array, tested in triode configuration with an external anode, has a low turn-on gate voltage of 26 V. A high emission current of 1 μA per tip was obtained at a gate voltage of approximately 60 V and an anode voltage of 200 V. The ability to modulate emission current at low gate voltage allows more practical usage of a diamond field emitter in vacuum microelectronics.

An electron emission behavior of field emission arrays based on a new bulk/surface silicon micromachining method of fabrication was studied. The process developed is simple and allows self-aligned gate electrode formation. The field emission of the emitter tips is enhanced by a 50 nm diamond-like carbon (DLC) film formed by chemical vapor deposition. Detailed Raman, Auger, and transmission electron microscopy (TEM) investigations of the deposited DLC films will be presented. Results about the presence of nanocrystalline diamond obtained with Raman spectroscopy could not be confirmed by the TEM investigations (the nanocrystalline diamond is smaller than 10 nm).

Metal-insulator-semiconductor (MIS) field effect transistors were fabricated on InP substrates using a planar self-aligned gate process. A 700-1000 A gate insulator of Si02 doped with phosphorus was deposited by a direct plasma enhanced chemical vapor deposition at 400 mTorr, 275 C, 5 W, and power density of 8.5 MW/sq cm. High frequency capacitance-voltage measurements were taken on MIS capacitors which have been subjected to a 700 C anneal and an interface state density of lxl0(exp 11)/eV/cq cm was found. Current-voltage measurements of the capacitors show a breakdown voltage of 107 V/cm and a insulator resistivity of 10(exp 14) omega cm. Transistors were fabricated on semi-insulating InP using a standard planar self-aligned gate process in which the gate insulator was subjected to an ion implantation activation anneal of 700 C. MIS field effect transistors gave a maximum extrinsic transconductance of 23 mS/mm for a gate length of 3 microns. The drain current drift saturated at 87.5% of the initial current, while reaching to within 1% of the saturated value after only 1x10(exp 3). This is the first reported viable planar InP self-aligned gate transistor process reported to date.

Since the first reported use of TiW gate as a stopping mask for n+ implantation for GaAs self‐aligned gate field effect transistors (SAGFET) in 1981, refractory metal compounds and silicides have found a widespread use in the GaAs SAGFET technology. However, the technique requires that the refractory metal (silicide)/GaAs interface be subjected to a high temperature postimplantation annealing, typically 750–900 °C. The mechanical, metallurgical, and most sensitively the electrical stabilities and reproducibility of the refractory metal (silicide)/GaAs Schottky barrier characteristics have become the major issues confronting the high temperature SAGFET technology. The use of a dielectric substitutional gate, which allows the refractory metal gate to be formed at a low temperature, typically room temperature to 400 °C, for fabrication of SAGFET was reported in 1983. With the advance of well controlled dry etching and photoresist planarization techniques, the low temperature SAGFET process becomes a potentia...

We report the first results on superlattice modulation‐doped field‐effect‐transistors (FET’s) fabricated using self‐aligned gate by the ion‐implantation process. The charge control superlattice layers consisted of Si‐doped GaAs (N=4×1018/cm3) and undoped Al0.36Ga0.64As of period 50 A. 1 μ gate enhancement‐mode MODFET’s exhibited an extrinsic transconductance as high as 335 mS/mm and a source resistance of 0.7 Ω mm at 300 K. From x‐ray diffraction analysis, conventional furnace anneal was found to intermix the superlattice layers. However, sharp 〈200〉x‐ray diffraction satellite peaks were preserved after rapid anneal, which indicate that rapid thermal annealing does not degrade the structures significantly. Photoluminescence analysis indicated a shift in the emission peak of only 15 meV at 300 K, indicating interfacial broadening of less than one monolayer. Shifts in the threshold voltage Vt in these superlattice MODFET’s in the temperature range of 300–77 K were reduced to a range of 100–140 mV, as compar...

It was found that the barrier height of thermally stable WNx /GaAs Schottky contacts can be enhanced by a high‐temperature annealing technique. In this study, the WNx /GaAs contact was annealed under different conditions including (i) furnace annealing under SiO2 encapsulant with N2 and arsine ambient, (ii) furnace annealing under arsine‐overpressure capless annealing, and (iii) rapid thermal annealing (RTA) under SiO2 encapsulant and argon ambient. The temperature range for furnace annealing was 700–850 °C and for RTA, 700–950 °C. RBS analysis of all samples revealed no detectable interdiffusion at the WNx /GaAs interface up to an annealing temperature of 850 °C for furnace annealing and 950 °C for RTA. The Schottky barrier height increased from 0.59 eV, as deposited, to the commonly reported value of 0.72 to 0.74 eV, at the optimum temperatures for all the annealing conditions mentioned, with one exception. Barrier heights as high as 0.8 eV were obtained using furnace annealing under SiO2 encapsulant an...

A refractory metal silicide process has been developed for the fabrication of self‐aligned gate (Al,Ga)As/GaAs FET’s (MODFET’s). Completely planar, self‐aligned gate by ion implantation MODFET’s have been fabricated and have demonstrated typical transconductances of 180–200 mS/mm at room temperature and over 300 mS/mm at 77 K. Self‐aligned gate ring oscillator test circuits have demonstrated gate propagation delays as low as 17.6 ps/gate at 2.65 mW/gate at room temperature.